ENGR00155958: MX6: Fix bug in setting parent of periph_clk

periph_clk mux should be set only after the periph_clk2 mux is set.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index cfc5f1bb5fe375c3c447f71033f188ec17194cc4..5328e60824c019ce10ab5c3d321995c6cdfdb2f3 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -937,7 +937,7 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
                reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
                __raw_writel(reg, MXC_CCM_CBCMR);
 
-       /* Set the periph_clk_sel multiplexer. */
+               /* Set the periph_clk_sel multiplexer. */
                reg = __raw_readl(MXC_CCM_CBCDR);
                reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
                __raw_writel(reg, MXC_CCM_CBCDR);
@@ -945,9 +945,6 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
                reg = __raw_readl(MXC_CCM_CBCDR);
                /* Set the periph_clk2_podf divider to divide by 1. */
                reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
-               /* Clear periph_clk_sel to select periph_clk2. */
-               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-
                __raw_writel(reg, MXC_CCM_CBCDR);
 
                /* Set the periph_clk2_sel mux. */
@@ -955,11 +952,16 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
                reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
                reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
                __raw_writel(reg, MXC_CCM_CBCMR);
+
+               reg = __raw_readl(MXC_CCM_CBCDR);
+               /* Set periph_clk_sel to select periph_clk2. */
+               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+               __raw_writel(reg, MXC_CCM_CBCDR);
        }
 
        if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
             & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
-               panic("pll _clk_axi_a_set_rate failed\n");
+               panic("_clk_periph_set_parent failed\n");
 
        return 0;
 }