vme: tsi148: CR/CSR logic arround the wrong way

The logic in the init routine for the TSI148 is inverted. It isn't switching
on the CR/CSR space when it should be and is reporting it's on when its not.

Correct the logic to do the right thing.

Reported-by: De Roo, Steven <steven.deroo@arcelormittal.com>
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/vme/bridges/vme_tsi148.c b/drivers/vme/bridges/vme_tsi148.c
index 94ce64d7a5f6a6c46a2a1bff0102744e07fca437..c04600e26a38d5492738f4918f2aa9b873cf8462 100644 (file)
--- a/drivers/vme/bridges/vme_tsi148.c
+++ b/drivers/vme/bridges/vme_tsi148.c
@@ -2300,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
        dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
 
        crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
-       if (crat & TSI148_LCSR_CRAT_EN) {
+       if (crat & TSI148_LCSR_CRAT_EN)
+               dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
+       else {
                dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
                iowrite32be(crat | TSI148_LCSR_CRAT_EN,
                        bridge->base + TSI148_LCSR_CRAT);
-       } else
-               dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
+       }
 
        /* If we want flushed, error-checked writes, set up a window
         * over the CR/CSR registers. We read from here to safely flush