D: Fixed the shm swap deallocation at swapoff time (try_to_unuse message)
D: VM hacker
D: Various other kernel hacks
-S: Via Cicalini 26
S: Imola 40026
S: Italy
M: ralf@linux-mips.org
W: http://www.linux-mips.org/
L: linux-mips@linux-mips.org
-S: Maintained
+T: git www.linux-mips.org:/pub/scm/linux.git
+S: Supported
MISCELLANEOUS MCA-SUPPORT
P: James Bottomley
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 16
-EXTRAVERSION =-rc6
+EXTRAVERSION =
NAME=Sliding Snow Leopard
# *DOCUMENTATION*
int apicid, ret;
lock_cpu_hotplug();
+
+ /*
+ * On x86, CPU0 is never offlined. Trying to bring up an
+ * already-booted CPU will hang. So check for that case.
+ */
+ if (cpu_online(cpu)) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
apicid = x86_cpu_to_apicid[cpu];
if (apicid == BAD_APICID) {
ret = -ENODEV;
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
-cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
+cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
+ -fno-omit-frame-pointer
#
# Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>)
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/bootinfo.h>
#include <asm/system.h>
-extern void *sgiwd93_host;
-extern void reset_wd33c93(void *instance);
-
VOID
ArcHalt(VOID)
{
bc_disable();
local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
- reset_wd33c93(sgiwd93_host);
-#endif
ARC_CALL0(halt);
never: goto never;
}
{
bc_disable();
local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
- reset_wd33c93(sgiwd93_host);
-#endif
ARC_CALL0(pdown);
never: goto never;
}
{
bc_disable();
local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
- reset_wd33c93(sgiwd93_host);
-#endif
ARC_CALL0(restart);
never: goto never;
}
{
bc_disable();
local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
- reset_wd33c93(sgiwd93_host);
-#endif
ARC_CALL0(reboot);
never: goto never;
}
{
bc_disable();
local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
- reset_wd33c93(sgiwd93_host);
-#endif
ARC_CALL0(imode);
never: goto never;
}
void au1000_halt(void)
{
-#if defined(CONFIG_MIPS_PB1550)
+#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
/* power off system */
- printk("\n** Powering off Pb1550\n");
+ printk("\n** Powering off...\n");
au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
au_sync();
while(1); /* should not get here */
-#endif
+#else
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
#ifdef CONFIG_MIPS_MIRAGE
au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
#endif
+#ifdef CONFIG_MIPS_DB1200
+ au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
+#endif
#ifdef CONFIG_PM
au_sleep();
"wait\n\t"
".set\tmips0");
#endif
+#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
}
void au1000_power_off(void)
unsigned long j;
unsigned int count;
+ write_seqlock(&xtime_lock);
+
count = mips_hpt_read();
mips_timer_ack();
* CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be
* called as close as possible to 500 ms before the new second starts.
*/
- write_seqlock(&xtime_lock);
if (ntp_synced() &&
xtime.tv_sec > last_rtc_update + 660 &&
(xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
last_rtc_update = xtime.tv_sec - 600;
}
}
- write_sequnlock(&xtime_lock);
/*
* If jiffies has overflown in this timer_interrupt, we must
}
}
+ write_sequnlock(&xtime_lock);
+
/*
* In UP mode, we call local_timer_interrupt() to do profiling
* and process accouting.
struct flush_cache_page_args {
struct vm_area_struct *vma;
unsigned long addr;
+ unsigned long pfn;
};
static inline void local_r4k_flush_cache_page(void *args)
struct flush_cache_page_args *fcp_args = args;
struct vm_area_struct *vma = fcp_args->vma;
unsigned long addr = fcp_args->addr;
+ unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
int exec = vma->vm_flags & VM_EXEC;
struct mm_struct *mm = vma->vm_mm;
pgd_t *pgdp;
* Do indexed flush, too much work to get the (possible) TLB refills
* to work correctly.
*/
- addr = INDEX_BASE + (addr & (dcache_size - 1));
if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
- r4k_blast_dcache_page_indexed(addr);
- if (exec && !cpu_icache_snoops_remote_store)
- r4k_blast_scache_page_indexed(addr);
+ r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
+ paddr : addr);
+ if (exec && !cpu_icache_snoops_remote_store) {
+ r4k_blast_scache_page_indexed(paddr);
+ }
}
if (exec) {
if (cpu_has_vtag_icache) {
args.vma = vma;
args.addr = addr;
+ args.pfn = pfn;
on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
}
switch (c->cputype) {
case CPU_20KC:
case CPU_25KF:
+ c->dcache.flags |= MIPS_CACHE_PINDEX;
case CPU_R10000:
case CPU_R12000:
case CPU_SB1:
* Do indexed flush, too much work to get the (possible) TLB refills
* to work correctly.
*/
- page = (KSEG0 + (page & (dcache_size - 1)));
if (cpu_has_dc_aliases || exec)
tx39_blast_dcache_page_indexed(page);
if (exec)
#define IMR_IP3_VAL K_INT_MAP_I1
#define IMR_IP4_VAL K_INT_MAP_I2
+#define SB1250_HPT_NUM 3
+#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
+#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
+
+
extern int sb1250_steal_irq(int irq);
+static unsigned int sb1250_hpt_read(void);
+static void sb1250_hpt_init(unsigned int);
+
+static unsigned int hpt_offset;
+
+void __init sb1250_hpt_setup(void)
+{
+ int cpu = smp_processor_id();
+
+ if (!cpu) {
+ /* Setup hpt using timer #3 but do not enable irq for it */
+ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
+ __raw_writeq(SB1250_HPT_VALUE,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
+ __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
+
+ /*
+ * we need to fill 32 bits, so just use the upper 23 bits and pretend
+ * the timer is going 512Mhz instead of 1Mhz
+ */
+ mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
+ mips_hpt_init = sb1250_hpt_init;
+ mips_hpt_read = sb1250_hpt_read;
+ }
+}
+
+
void sb1250_time_init(void)
{
int cpu = smp_processor_id();
int irq = K_INT_TIMER_0+cpu;
- /* Only have 4 general purpose timers */
- if (cpu > 3) {
+ /* Only have 4 general purpose timers, and we use last one as hpt */
+ if (cpu > 2) {
BUG();
}
- if (!cpu) {
- /* Use our own gettimeoffset() routine */
- do_gettimeoffset = sb1250_gettimeoffset;
- }
-
sb1250_mask_irq(cpu, irq);
/* Map the timer interrupt to ip[4] of this cpu */
/* Disable the timer and set up the count */
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
#ifdef CONFIG_SIMULATION
- __raw_writeq(50000 / HZ,
+ __raw_writeq((50000 / HZ) - 1,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#else
- __raw_writeq(1000000 / HZ,
+ __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#endif
int cpu = smp_processor_id();
int irq = K_INT_TIMER_0 + cpu;
- /* Reset the timer */
+ /* ACK interrupt */
____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
}
/*
- * We use our own do_gettimeoffset() instead of the generic one,
- * because the generic one does not work for SMP case.
- * In addition, since we use general timer 0 for system time,
- * we can get accurate intra-jiffy offset without calibration.
+ * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
+ * again. There's no easy way to set to a specific value so store init value
+ * in hpt_offset and subtract each time.
+ *
+ * Note: Timer isn't full 32bits so shift it into the upper part making
+ * it appear to run at a higher frequency.
*/
-unsigned long sb1250_gettimeoffset(void)
+static unsigned int sb1250_hpt_read(void)
{
- unsigned long count =
- __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
+ unsigned int count;
- return 1000000/HZ - count;
- }
+ count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
+
+ count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
+
+ return count - hpt_offset;
+}
+
+static void sb1250_hpt_init(unsigned int count)
+{
+ hpt_offset = count;
+ return;
+}
return "SiByte " SIBYTE_BOARD_NAME;
}
+void __init swarm_time_init(void)
+{
+ /* Setup HPT */
+ sb1250_hpt_setup();
+}
+
void __init swarm_timer_setup(struct irqaction *irq)
{
/*
panic_timeout = 5; /* For debug. */
+ board_time_init = swarm_time_init;
board_timer_setup = swarm_timer_setup;
board_be_handler = swarm_be_handler;
return -EINVAL;
}
+ if (((uint32_t)ti->len) & (chunk_size - 1)) {
+ ti->error = "dm-stripe: Target length not divisible by "
+ "chunk size";
+ return -EINVAL;
+ }
+
width = ti->len;
if (sector_div(width, stripes)) {
- ti->error = "dm-stripe: Target length not divisable by "
+ ti->error = "dm-stripe: Target length not divisible by "
"number of stripes";
return -EINVAL;
}
To compile this driver as a module, choose M here: the
module will be called cx8800
-config VIDEO_CX88_DVB
- tristate "DVB/ATSC Support for cx2388x based TV cards"
- depends on VIDEO_CX88 && DVB_CORE
- select VIDEO_BUF_DVB
- ---help---
- This adds support for DVB/ATSC cards based on the
- Connexant 2388x chip.
-
- To compile this driver as a module, choose M here: the
- module will be called cx88-dvb.
-
- You must also select one or more DVB/ATSC demodulators.
- If you are unsure which you need, choose all of them.
-
config VIDEO_CX88_ALSA
tristate "ALSA DMA audio support"
depends on VIDEO_CX88 && SND && EXPERIMENTAL
To compile this driver as a module, choose M here: the
module will be called cx88-alsa.
+config VIDEO_CX88_DVB
+ tristate "DVB/ATSC Support for cx2388x based TV cards"
+ depends on VIDEO_CX88 && DVB_CORE
+ select VIDEO_BUF_DVB
+ ---help---
+ This adds support for DVB/ATSC cards based on the
+ Connexant 2388x chip.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cx88-dvb.
+
+ You must also select one or more DVB/ATSC demodulators.
+ If you are unsure which you need, choose all of them.
+
config VIDEO_CX88_DVB_ALL_FRONTENDS
bool "Build all supported frontends for cx2388x based TV cards"
default y
em28xx_capture_start(dev, 1);
em28xx_resolution_set(dev);
+ /* device needs to be initialized before isoc transfer */
+ video_mux(dev, 0);
+
/* start the transfer */
errCode = em28xx_init_isoc(dev);
if (errCode)
if (test_and_clear_bit(nd->if_port,
&sge->stopped_tx_queues) &&
netif_running(nd)) {
- sge->stats.cmdQ_restarted[3]++;
+ sge->stats.cmdQ_restarted[2]++;
netif_wake_queue(nd);
}
}
if (unlikely(credits < count)) {
netif_stop_queue(dev);
set_bit(dev->if_port, &sge->stopped_tx_queues);
- sge->stats.cmdQ_full[3]++;
+ sge->stats.cmdQ_full[2]++;
spin_unlock(&q->lock);
if (!netif_queue_stopped(dev))
CH_ERR("%s: Tx ring full while queue awake!\n",
return NETDEV_TX_BUSY;
}
if (unlikely(credits - count < q->stop_thres)) {
- sge->stats.cmdQ_full[3]++;
+ sge->stats.cmdQ_full[2]++;
netif_stop_queue(dev);
set_bit(dev->if_port, &sge->stopped_tx_queues);
}
msleep(10);
+ pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
+ RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
+
if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
skb->data, ETH_DATA_LEN))
err = -EAGAIN;
err_loopback_none:
mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
nic->loopback = lb_none;
- e100_hw_init(nic);
e100_clean_cbs(nic);
+ e100_hw_reset(nic);
err_clean_rx:
e100_rx_clean_list(nic);
return err;
e1000_rx_checksum(adapter,
(uint32_t)(status) |
((uint32_t)(rx_desc->errors) << 24),
- rx_desc->csum, skb);
+ le16_to_cpu(rx_desc->csum), skb);
skb->protocol = eth_type_trans(skb, netdev);
#ifdef CONFIG_E1000_NAPI
}
e1000_rx_checksum(adapter, staterr,
- rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
+ le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
skb->protocol = eth_type_trans(skb, netdev);
if (likely(rx_desc->wb.upper.header_status &
- E1000_RXDPS_HDRSTAT_HDRSP))
+ cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
adapter->rx_hdr_split++;
#ifdef CONFIG_E1000_NAPI
if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
#endif
next_desc:
- rx_desc->wb.middle.status_error &= ~0xFF;
+ rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
buffer_info->skb = NULL;
/* return some buffers to hardware, one at a time is too slow */
}
}
- /* Find msi capability. */
+ /* The EPB bridge inside 5714, 5715, and 5780 cannot support
+ * DMA addresses > 40-bit. This bridge may have other additional
+ * 57xx devices behind it in some 4-port NIC designs for example.
+ * Any tg3 device found behind the bridge will also need the 40-bit
+ * DMA workaround.
+ */
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
+ tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
}
+ else {
+ struct pci_dev *bridge = NULL;
+
+ do {
+ bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
+ PCI_DEVICE_ID_SERVERWORKS_EPB,
+ bridge);
+ if (bridge && bridge->subordinate &&
+ (bridge->subordinate->number <=
+ tp->pdev->bus->number) &&
+ (bridge->subordinate->subordinate >=
+ tp->pdev->bus->number)) {
+ tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
+ pci_dev_put(bridge);
+ break;
+ }
+ } while (bridge);
+ }
/* Initialize misc host control in PCI block. */
tp->misc_host_ctrl |= (misc_ctrl_reg &
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
- if (ccval == 0x6 || ccval == 0x7)
+ /* If the 5704 is behind the EPB bridge, we can
+ * do the less restrictive ONE_DMA workaround for
+ * better performance.
+ */
+ if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
+ tp->dma_rwctrl |= 0x8000;
+ else if (ccval == 0x6 || ccval == 0x7)
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
/* Set bit 23 to enable PCIX hw bug fix */
goto err_out_iounmap;
}
- /* 5714, 5715 and 5780 cannot support DMA addresses > 40-bit.
+ /* The EPB bridge inside 5714, 5715, and 5780 and any
+ * device behind the EPB cannot support DMA addresses > 40-bit.
* On 64-bit systems with IOMMU, use 40-bit dma_mask.
* On 64-bit systems without IOMMU, use 64-bit dma_mask and
* do DMA address check in tg3_start_xmit().
*/
- if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
+ if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
+ persist_dma_mask = dma_mask = DMA_32BIT_MASK;
+ else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
persist_dma_mask = dma_mask = DMA_40BIT_MASK;
#ifdef CONFIG_HIGHMEM
dma_mask = DMA_64BIT_MASK;
#endif
- } else if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
- persist_dma_mask = dma_mask = DMA_32BIT_MASK;
- else
+ } else
persist_dma_mask = dma_mask = DMA_64BIT_MASK;
/* Configure DMA attributes. */
(tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
(tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
- printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
- dev->name, tp->dma_rwctrl);
+ printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
+ dev->name, tp->dma_rwctrl,
+ (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
+ (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
return 0;
#define TG3_FLAG_10_100_ONLY 0x01000000
#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
#define TG3_FLAG_IN_RESET_TASK 0x04000000
+#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
#define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
#define TG3_FLAG_SPLIT_MODE 0x40000000
filp->private_data = NULL;
}
- d_drop(filp->f_dentry);
return 0;
}
if (copy_from_user(&version, &arg->ca_version, sizeof(int)))
return -EFAULT;
- if (version != NFSCTL_VERSION) {
- printk(KERN_WARNING "nfsd: incompatible version in syscall.\n");
+ if (version != NFSCTL_VERSION)
return -EINVAL;
- }
if (cmd < 0 || cmd >= sizeof(map)/sizeof(map[0]) || !map[cmd].name)
return -EINVAL;
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
+#ifndef cpu_has_pindexed_dcache
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
struct cpuinfo_mips {
unsigned long udelay_val;
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) MIPS Technologies, Inc.
+ * written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H
#define irq_disable_hazard
_ehb
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
- defined(CONFIG_CPU_SB1)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
#else /* __ASSEMBLY__ */
__asm__(
- " .macro _ssnop \n\t"
- " sll $0, $0, 1 \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro _ehb \n\t"
- " sll $0, $0, 3 \n\t"
- " .endm \n\t");
+ " .macro _ssnop \n"
+ " sll $0, $0, 1 \n"
+ " .endm \n"
+ " \n"
+ " .macro _ehb \n"
+ " sll $0, $0, 3 \n"
+ " .endm \n");
#ifdef CONFIG_CPU_RM9000
#define mtc0_tlbw_hazard() \
__asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
+ " .set mips32 \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " .set mips0 \n")
#define tlbw_use_hazard() \
__asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
-
-#define back_to_back_c0_hazard() do { } while (0)
+ " .set mips32 \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " .set mips0 \n")
#else
*/
#define mtc0_tlbw_hazard() \
__asm__ __volatile__( \
- ".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
+ " .set noreorder \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " .set reorder \n")
#define tlbw_use_hazard() \
__asm__ __volatile__( \
- ".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
+ " .set noreorder \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " .set reorder \n")
#endif
#ifdef CONFIG_CPU_MIPSR2
-__asm__(
- " .macro\tirq_enable_hazard \n\t"
- " _ehb \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " _ehb \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tback_to_back_c0_hazard \n\t"
- " _ehb \n\t"
- " .endm");
-
-#define irq_enable_hazard() \
- __asm__ __volatile__( \
- "irq_enable_hazard")
+__asm__(" .macro irq_enable_hazard \n"
+ " _ehb \n"
+ " .endm \n"
+ " \n"
+ " .macro irq_disable_hazard \n"
+ " _ehb \n"
+ " .endm \n");
-#define irq_disable_hazard() \
- __asm__ __volatile__( \
- "irq_disable_hazard")
-
-#define back_to_back_c0_hazard() \
- __asm__ __volatile__( \
- "back_to_back_c0_hazard")
-
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
- defined(CONFIG_CPU_SB1)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
*/
__asm__(
- " .macro\tirq_enable_hazard \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " .endm");
-
-#define irq_enable_hazard() do { } while (0)
-#define irq_disable_hazard() do { } while (0)
-
-#define back_to_back_c0_hazard() do { } while (0)
+ " .macro irq_enable_hazard \n"
+ " .endm \n"
+ " \n"
+ " .macro irq_disable_hazard \n"
+ " .endm \n");
#else
*/
__asm__(
- " # \n\t"
- " # There is a hazard but we do not care \n\t"
- " # \n\t"
- " .macro\tirq_enable_hazard \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " _ssnop; _ssnop; _ssnop \n\t"
- " .endm");
+ " # \n"
+ " # There is a hazard but we do not care \n"
+ " # \n"
+ " .macro\tirq_enable_hazard \n"
+ " .endm \n"
+ " \n"
+ " .macro\tirq_disable_hazard \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " .endm \n");
-#define irq_enable_hazard() do { } while (0)
+#endif
+
+#define irq_enable_hazard() \
+ __asm__ __volatile__("irq_enable_hazard")
#define irq_disable_hazard() \
- __asm__ __volatile__( \
- "irq_disable_hazard")
+ __asm__ __volatile__("irq_disable_hazard")
-#define back_to_back_c0_hazard() \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " nop; nop; nop \n" \
- " .set reorder \n")
+
+/*
+ * Back-to-back hazards -
+ *
+ * What is needed to separate a move to cp0 from a subsequent read from the
+ * same cp0 register?
+ */
+#ifdef CONFIG_CPU_MIPSR2
+
+__asm__(" .macro back_to_back_c0_hazard \n"
+ " _ehb \n"
+ " .endm \n");
+
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+ defined(CONFIG_CPU_SB1)
+
+__asm__(" .macro back_to_back_c0_hazard \n"
+ " .endm \n");
+
+#else
+
+__asm__(" .macro back_to_back_c0_hazard \n"
+ " .set noreorder \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " .set reorder \n"
+ " .endm");
#endif
+#define back_to_back_c0_hazard() \
+ __asm__ __volatile__("back_to_back_c0_hazard")
+
+
+/*
+ * Instruction execution hazard
+ */
#ifdef CONFIG_CPU_MIPSR2
/*
* gcc has a tradition of misscompiling the previous construct using the
* for more details.
*
* Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Author: Maciej W. Rozycki <macro@mips.com>
*/
extern const unsigned long mips_io_port_base;
-#define set_io_port_base(base) \
- do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases. So we don't
+ * play quite by the book. We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue. Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer. Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+ * (unsigned long *) &mips_io_port_base = base;
+ barrier();
+}
/*
* Thanks to James van Artsdalen for a better timing-fix than
\
static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
{ \
- unsigned long start = page; \
+ unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
+ unsigned long start = INDEX_BASE + (page & indexmask); \
unsigned long end = start + PAGE_SIZE; \
unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
unsigned long ws_end = current_cpu_data.desc.ways << \
extern unsigned int periph_rev;
extern unsigned int zbbus_mhz;
+extern void sb1250_hpt_setup(void);
extern void sb1250_time_init(void);
-extern unsigned long sb1250_gettimeoffset(void);
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
extern void sb1250_smp_finish(void);
*/
#define V_SCD_TIMER_FREQ 1000000
+#define V_SCD_TIMER_WIDTH 23
#define S_SCD_TIMER_INIT 0
-#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
+#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
#define S_SCD_TIMER_CNT 0
-#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
+#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008
#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009
#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_EPB 0x0103
#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200
#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201
#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203
enum {
AX25_PROTO_STD_SIMPLEX,
AX25_PROTO_STD_DUPLEX,
+#ifdef CONFIG_AX25_DAMA_SLAVE
AX25_PROTO_DAMA_SLAVE,
- AX25_PROTO_DAMA_MASTER
+#ifdef CONFIG_AX25_DAMA_MASTER
+ AX25_PROTO_DAMA_MASTER,
+#define AX25_PROTO_MAX AX25_PROTO_DAMA_MASTER
+#endif
+#endif
+ __AX25_PROTO_MAX,
+ AX25_PROTO_MAX = __AX25_PROTO_MAX -1
};
enum {
rc = __condition; \
if (!rc) { \
*(__timeo) = schedule_timeout(*(__timeo)); \
- rc = __condition; \
} \
lock_sock(__sk); \
+ rc = __condition; \
rc; \
})
if ((unshare_flags & CLONE_VM) &&
(mm && atomic_read(&mm->mm_users) > 1)) {
- *new_mmp = dup_mm(current);
- if (!*new_mmp)
- return -ENOMEM;
+ return -EINVAL;
}
return 0;
if (new_sigh) {
sigh = current->sighand;
- current->sighand = new_sigh;
+ rcu_assign_pointer(current->sighand, new_sigh);
new_sigh = sigh;
}
hrtimer_forward(&timr->it.real.timer,
timr->it.real.interval);
ret = HRTIMER_RESTART;
+ ++timr->it_requeue_pending;
}
}
#ifdef CONFIG_TIME_INTERPOLATION
-struct time_interpolator *time_interpolator;
-static struct time_interpolator *time_interpolator_list;
+struct time_interpolator *time_interpolator __read_mostly;
+static struct time_interpolator *time_interpolator_list __read_mostly;
static DEFINE_SPINLOCK(time_interpolator_lock);
static inline u64 time_interpolator_get_cycles(unsigned int src)
(*zap_work)--;
continue;
}
+
+ (*zap_work) -= PAGE_SIZE;
+
if (pte_present(ptent)) {
struct page *page;
- (*zap_work) -= PAGE_SIZE;
-
page = vm_normal_page(vma, addr, ptent);
if (unlikely(details) && page) {
/*
int err;
struct vm_area_struct *first, *vma, *prev;
- /* Clear the LRU lists so pages can be isolated */
- if (flags & (MPOL_MF_MOVE | MPOL_MF_MOVE_ALL))
+ if (flags & (MPOL_MF_MOVE | MPOL_MF_MOVE_ALL)) {
+ /* Must have swap device for migration */
+ if (nr_swap_pages <= 0)
+ return ERR_PTR(-ENODEV);
+
+ /*
+ * Clear the LRU lists so pages can be isolated.
+ * Note that pages may be moved off the LRU after we have
+ * drained them. Those pages will fail to migrate like other
+ * pages that may be busy.
+ */
lru_add_drain_all();
+ }
first = find_vma(mm, start);
if (!first)
struct page *page = pvec->pages[i];
if (PagePrivate(page) && !TestSetPageLocked(page)) {
- try_to_release_page(page, 0);
+ if (PagePrivate(page))
+ try_to_release_page(page, 0);
unlock_page(page);
}
}
static int min_idle[1], max_idle[] = {65535 * HZ};
static int min_n2[] = {1}, max_n2[] = {31};
static int min_paclen[] = {1}, max_paclen[] = {512};
-static int min_proto[1], max_proto[] = {3};
+static int min_proto[1], max_proto[] = { AX25_PROTO_MAX };
static int min_ds_timeout[1], max_ds_timeout[] = {65535 * HZ};
static struct ctl_table_header *ax25_table_header;
a4_included = ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) ==
(IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS));
qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) &&
- (WLAN_FC_GET_STYPE(fc) & 0x08));
+ (WLAN_FC_GET_STYPE(fc) & IEEE80211_STYPE_QOS_DATA));
aad_len = 22;
if (a4_included)
aad_len += 6;
if (is_beacon(beacon->header.frame_ctl)) {
if (ieee->handle_beacon != NULL)
- ieee->handle_beacon(dev, beacon, &network);
+ ieee->handle_beacon(dev, beacon, target);
} else {
if (ieee->handle_probe_response != NULL)
- ieee->handle_probe_response(dev, beacon, &network);
+ ieee->handle_probe_response(dev, beacon, target);
}
}
va_start(ap, fmt);
len = vsnprintf(tmp, SZ, fmt, ap);
- if (buf->size - buf->pos < len + 1) {
- buf->size += 128;
- buf->p = realloc(buf->p, buf->size);
- }
- strncpy(buf->p + buf->pos, tmp, len + 1);
- buf->pos += len;
+ buf_write(buf, tmp, len);
va_end(ap);
}
buf_write(struct buffer *buf, const char *s, int len)
{
if (buf->size - buf->pos < len) {
- buf->size += len;
+ buf->size += len + SZ;
buf->p = realloc(buf->p, buf->size);
}
strncpy(buf->p + buf->pos, s, len);
projects / linux-beck.git / commitdiff