drm/i915: Fixup non-24bpp support for VGA screens on Haswell

The LPT PCH only supports 8bpc, so we need to force the pipe bpp
to the right value.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c063b9f0dd519e9a2ba167b585f8f78ba6c49544..991e53047e1dede413b8703de2b9d577e9d23e6a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -214,6 +214,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
        if (HAS_PCH_SPLIT(dev))
                pipe_config->has_pch_encoder = true;
 
+       /* LPT FDI RX only supports 8bpc. */
+       if (HAS_PCH_LPT(dev))
+               pipe_config->pipe_bpp = 24;
+
        return true;
 }