rockchip: make sure timer7 is enabled on rk3288 platforms

timer7 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.

While it should be the responsibility of the bootloader to do this,
and there exists a fix in a community u-boot, all u-boot based systems
that actually shipped have the mentioned issue.

Therefore to not require every developer to update their u-boot, add a
snippet for this, enabling the timer early in the kernel.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d360ec044b66e0b990c03f2569da3e07dbffc59d..b6cf3b449428960d28590f5cdad6e331d2239080 100644 (file)
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -30,11 +30,30 @@
 #include "pm.h"
 
 #define RK3288_GRF_SOC_CON0 0x244
+#define RK3288_TIMER6_7_PHYS 0xff810000
 
 static void __init rockchip_timer_init(void)
 {
        if (of_machine_is_compatible("rockchip,rk3288")) {
                struct regmap *grf;
+               void __iomem *reg_base;
+
+               /*
+                * Most/all uboot versions for rk3288 don't enable timer7
+                * which is needed for the architected timer to work.
+                * So make sure it is running during early boot.
+                */
+               reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
+               if (reg_base) {
+                       writel(0, reg_base + 0x30);
+                       writel(0xffffffff, reg_base + 0x20);
+                       writel(0xffffffff, reg_base + 0x24);
+                       writel(1, reg_base + 0x30);
+                       dsb();
+                       iounmap(reg_base);
+               } else {
+                       pr_err("rockchip: could not map timer7 registers\n");
+               }
 
                /*
                 * Disable auto jtag/sdmmc switching that causes issues