#include "linux/delay.h"
#include "pp_acpi.h"
#include "hwmgr.h"
-#include "ellesmere_hwmgr.h"
-#include "ellesmere_powertune.h"
-#include "ellesmere_dyn_defaults.h"
-#include "ellesmere_smumgr.h"
+#include "polaris10_hwmgr.h"
+#include "polaris10_powertune.h"
+#include "polaris10_dyn_defaults.h"
+#include "polaris10_smumgr.h"
#include "pp_debug.h"
#include "ppatomctrl.h"
#include "atombios.h"
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
-#include "ellesmere_thermal.h"
-#include "ellesmere_clockpowergating.h"
+#include "polaris10_thermal.h"
+#include "polaris10_clockpowergating.h"
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b
#define TCLK (PCIE_BUS_CLK / 10)
-uint16_t ellesmere_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
+uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
{600, 1050, 6, 1} };
/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
-uint32_t ellesmere_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
+uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
-uint8_t ellesmere_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
+uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
{0, 2, 4, 5, 6, 5} };
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
};
-const unsigned long PhwEllesmere_Magic = (unsigned long)(PHM_VIslands_Magic);
+const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
-struct ellesmere_power_state *cast_phw_ellesmere_power_state(
+struct polaris10_power_state *cast_phw_polaris10_power_state(
struct pp_hw_power_state *hw_ps)
{
- PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic),
+ PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
"Invalid Powerstate Type!",
return NULL);
- return (struct ellesmere_power_state *)hw_ps;
+ return (struct polaris10_power_state *)hw_ps;
}
-const struct ellesmere_power_state *cast_const_phw_ellesmere_power_state(
+const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
const struct pp_hw_power_state *hw_ps)
{
- PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic),
+ PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
"Invalid Powerstate Type!",
return NULL);
- return (const struct ellesmere_power_state *)hw_ps;
+ return (const struct polaris10_power_state *)hw_ps;
}
-static bool ellesmere_is_dpm_running(struct pp_hwmgr *hwmgr)
+static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
{
return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
* @param pHwMgr the address of the powerplay hardware manager.
* @return always PP_Result_OK
*/
-int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
+int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
{
PP_ASSERT_WITH_CODE(
(hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
*
* @param hwmgr the address of the powerplay hardware manager.
*/
-static bool ellesmere_voltage_control(const struct pp_hwmgr *hwmgr)
+static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
{
- const struct ellesmere_hwmgr *data =
- (const struct ellesmere_hwmgr *)(hwmgr->backend);
+ const struct polaris10_hwmgr *data =
+ (const struct polaris10_hwmgr *)(hwmgr->backend);
- return (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control);
+ return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
}
/**
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_enable_voltage_control(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
{
/* enable voltage control */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr)
+static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)hwmgr->pptable;
int result;
- if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
result = atomctrl_get_voltage_table_v3(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
&(data->mvdd_voltage_table));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve MVDD table.",
return result);
- } else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
+ } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
table_info->vdd_dep_on_mclk);
PP_ASSERT_WITH_CODE((0 == result),
return result;);
}
- if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
result = atomctrl_get_voltage_table_v3(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
&(data->vddci_voltage_table));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve VDDCI table.",
return result);
- } else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+ } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
table_info->vdd_dep_on_mclk);
PP_ASSERT_WITH_CODE((0 == result),
return result);
}
- if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
table_info->vddc_lookup_table);
PP_ASSERT_WITH_CODE((0 == result),
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_program_static_screen_threshold_parameters(
+static int polaris10_program_static_screen_threshold_parameters(
struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
/* Set static screen threshold unit */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_enable_display_gap(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
{
uint32_t display_gap =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_program_voting_clients(struct pp_hwmgr *hwmgr)
+static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
/* Clear reset for voting clients before enabling DPM */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr)
+static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(hwmgr->smumgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp;
int result;
bool error = false;
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, DpmTable),
&tmp, data->sram_end);
error |= (0 != result);
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, SoftRegisters),
&tmp, data->sram_end);
error |= (0 != result);
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, mcRegisterTable),
&tmp, data->sram_end);
if (!result)
data->mc_reg_table_start = tmp;
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, FanTable),
&tmp, data->sram_end);
error |= (0 != result);
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
&tmp, data->sram_end);
error |= (0 != result);
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, Version),
&tmp, data->sram_end);
/* Copy one arb setting to another and then switch the active set.
* arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
*/
-static int ellesmere_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
+static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
uint32_t arb_src, uint32_t arb_dest)
{
uint32_t mc_arb_dram_timing;
* @return always 0
* This function is to be called from the SetPowerState table.
*/
-static int ellesmere_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
+static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
{
- return ellesmere_copy_and_switch_arb_sets(hwmgr,
+ return polaris10_copy_and_switch_arb_sets(hwmgr,
MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
}
-static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
+static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
* on the power policy or external client requests,
* such as UVD request, etc.
*/
-int ellesmere_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
+int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
uint32_t i;
}
/* setup PCIE gen speed levels */
- ellesmere_setup_default_pcie_table(hwmgr);
+ polaris10_setup_default_pcie_table(hwmgr);
/* save a copy of the default DPM table */
memcpy(&(data->golden_dpm_table), &(data->dpm_table),
- sizeof(struct ellesmere_dpm_table));
+ sizeof(struct polaris10_dpm_table));
return 0;
}
* @param *table The SMC DPM table structure to be populated.
* @return 0
*/
-static int ellesmere_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
SMU74_Discrete_DpmTable *table)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t count, level;
- if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
count = data->mvdd_voltage_table.count;
if (count > SMU_MAX_SMIO_LEVELS)
count = SMU_MAX_SMIO_LEVELS;
return 0;
}
-static int ellesmere_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
uint32_t count, level;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
count = data->vddci_voltage_table.count;
- if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
if (count > SMU_MAX_SMIO_LEVELS)
count = SMU_MAX_SMIO_LEVELS;
for (level = 0; level < count; ++level) {
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
-static int ellesmere_populate_cac_table(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
uint32_t count;
uint8_t index;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_voltage_lookup_table *lookup_table =
* @return always 0
*/
-int ellesmere_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
+int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
- ellesmere_populate_smc_vddci_table(hwmgr, table);
- ellesmere_populate_smc_mvdd_table(hwmgr, table);
- ellesmere_populate_cac_table(hwmgr, table);
+ polaris10_populate_smc_vddci_table(hwmgr, table);
+ polaris10_populate_smc_mvdd_table(hwmgr, table);
+ polaris10_populate_cac_table(hwmgr, table);
return 0;
}
-static int ellesmere_populate_ulv_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_Ulv *state)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
return 0;
}
-static int ellesmere_populate_ulv_state(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
- return ellesmere_populate_ulv_level(hwmgr, &table->Ulv);
+ return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
}
-static int ellesmere_populate_smc_link_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_dpm_table *dpm_table = &data->dpm_table;
int i;
/* Index (dpm_table->pcie_speed_table.count)
return 0;
}
-static uint32_t ellesemere_get_xclk(struct pp_hwmgr *hwmgr)
+static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
{
uint32_t reference_clock, tmp;
struct cgs_display_info info = {0};
* @param clock the engine clock to use to populate the structure
* @param sclk the SMC SCLK structure to be populated
*/
-static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr,
+static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
uint32_t clock, SMU_SclkSetting *sclk_setting)
{
- const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
struct pp_atomctrl_clock_dividers_ai dividers;
return result;
}
- ref_clock = ellesemere_get_xclk(hwmgr);
+ ref_clock = polaris10_get_xclk(hwmgr);
for (i = 0; i < NUM_SCLK_RANGE; i++) {
if (clock > data->range_table[i].trans_lower_frequency
return 0;
}
-static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
+static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
{
uint32_t i;
uint16_t vddci;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
*voltage = *mvdd = 0;
if (dep_table->entries[i].clk >= clock) {
*voltage |= (dep_table->entries[i].vddc *
VOLTAGE_SCALE) << VDDC_SHIFT;
- if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
*voltage |= (data->vbios_boot_state.vddci_bootup_value *
VOLTAGE_SCALE) << VDDCI_SHIFT;
else if (dep_table->entries[i].vddci)
*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
}
- if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control)
+ if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
*mvdd = data->vbios_boot_state.mvdd_bootup_value *
VOLTAGE_SCALE;
else if (dep_table->entries[i].mvdd)
/* sclk is bigger than max sclk in the dependence table */
*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
- if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
*voltage |= (data->vbios_boot_state.vddci_bootup_value *
VOLTAGE_SCALE) << VDDCI_SHIFT;
else if (dep_table->entries[i-1].vddci) {
*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
}
- if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control)
+ if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
else if (dep_table->entries[i].mvdd)
*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
{VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
{VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
-static void ellesmere_get_sclk_range_table(struct pp_hwmgr *hwmgr)
+static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
{
uint32_t i, ref_clk;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
- ref_clk = ellesemere_get_xclk(hwmgr);
+ ref_clk = polaris10_get_xclk(hwmgr);
if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
for (i = 0; i < NUM_SCLK_RANGE; i++) {
* @param sclk the SMC SCLK structure to be populated
*/
-static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
uint32_t clock, uint16_t sclk_al_threshold,
struct SMU74_Discrete_GraphicsLevel *level)
{
int result, i, temp;
/* PP_Clocks minClocks; */
uint32_t mvdd;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
SMU_SclkSetting curr_sclk_setting = { 0 };
- result = ellesmere_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
+ result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
/* populate graphics levels */
- result = ellesmere_get_dependency_volt_by_clk(hwmgr,
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
table_info->vdd_dep_on_sclk, clock,
&level->MinVoltage, &mvdd);
level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
*/
PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
- for (i = ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
+ for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
temp = clock / (1UL << i);
if (temp >= 2500 || i == 0)
*
* @param hwmgr the address of the hardware manager
*/
-static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_dpm_table *dpm_table = &data->dpm_table;
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
mid_pcie_level_enabled = 0,
count = 0;
- ellesmere_get_sclk_range_table(hwmgr);
+ polaris10_get_sclk_range_table(hwmgr);
for (i = 0; i < dpm_table->sclk_table.count; i++) {
- result = ellesmere_populate_single_graphic_level(hwmgr,
+ result = polaris10_populate_single_graphic_level(hwmgr,
dpm_table->sclk_table.dpm_levels[i].value,
(uint16_t)data->activity_target[i],
&(data->smc_state_table.GraphicsLevel[i]));
levels[1].pcieDpmLevel = mid_pcie_level_enabled;
}
/* level count will send to smc once at init smc table and never change */
- result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
+ result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
(uint32_t)array_size, data->sram_end);
return result;
}
-static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
int result = 0;
cgs_get_active_displays_info(hwmgr->device, &info);
if (table_info->vdd_dep_on_mclk) {
- result = ellesmere_get_dependency_volt_by_clk(hwmgr,
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
table_info->vdd_dep_on_mclk, clock,
&mem_level->MinVoltage, &mem_level->MinMvdd);
PP_ASSERT_WITH_CODE((0 == result),
*
* @param hwmgr the address of the hardware manager
*/
-static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_dpm_table *dpm_table = &data->dpm_table;
int result;
/* populate MCLK dpm table to SMU7 */
uint32_t array = data->dpm_table_start +
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
"can not populate memory level as memory clock is zero",
return -EINVAL);
- result = ellesmere_populate_single_memory_level(hwmgr,
+ result = polaris10_populate_single_memory_level(hwmgr,
dpm_table->mclk_table.dpm_levels[i].value,
&levels[i]);
if (result)
PPSMC_DISPLAY_WATERMARK_HIGH;
/* level count will send to smc once at init smc table and never change */
- result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
+ result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
(uint32_t)array_size, data->sram_end);
return result;
* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
* @param voltage the SMC VOLTAGE structure to be populated
*/
-int ellesmere_populate_mvdd_value(struct pp_hwmgr *hwmgr,
+int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
uint32_t mclk, SMIO_Pattern *smio_pat)
{
- const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
uint32_t i = 0;
- if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
/* find mvdd value which clock is more than request */
for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
return 0;
}
-static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
SMU74_Discrete_DpmTable *table)
{
int result = 0;
uint32_t sclk_frequency;
- const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
SMIO_Pattern vol_level;
/* Get MinVoltage and Frequency from DPM0,
* already converted to SMC_UL */
sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
- result = ellesmere_get_dependency_volt_by_clk(hwmgr,
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
table_info->vdd_dep_on_sclk,
table->ACPILevel.SclkFrequency,
&table->ACPILevel.MinVoltage, &mvdd);
data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
}
- result = ellesmere_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
+ result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
table->ACPILevel.DeepSleepDivId = 0;
/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
table->MemoryACPILevel.MclkFrequency =
data->dpm_table.mclk_table.dpm_levels[0].value;
- result = ellesmere_get_dependency_volt_by_clk(hwmgr,
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
table_info->vdd_dep_on_mclk,
table->MemoryACPILevel.MclkFrequency,
&table->MemoryACPILevel.MinVoltage, &mvdd);
}
us_mvdd = 0;
- if ((ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
+ if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
(data->mclk_dpm_key_disabled))
us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
else {
- if (!ellesmere_populate_mvdd_value(hwmgr,
+ if (!polaris10_populate_mvdd_value(hwmgr,
data->dpm_table.mclk_table.dpm_levels[0].value,
&vol_level))
us_mvdd = vol_level.Voltage;
}
- if (0 == ellesmere_populate_mvdd_value(hwmgr, 0, &vol_level))
+ if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
else
table->MemoryACPILevel.MinMvdd = 0;
return result;
}
-static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
SMU74_Discrete_DpmTable *table)
{
int result = -EINVAL;
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
table_info->mm_dep_table;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
table->VceLevelCount = (uint8_t)(mm_table->count);
table->VceBootLevel = 0;
return result;
}
-static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
SMU74_Discrete_DpmTable *table)
{
int result = -EINVAL;
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
table_info->mm_dep_table;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
table->SamuBootLevel = 0;
table->SamuLevelCount = (uint8_t)(mm_table->count);
return result;
}
-static int ellesmere_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
int32_t eng_clock, int32_t mem_clock,
SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
{
return 0;
}
-static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
+static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
uint32_t i, j;
int result = 0;
for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
- result = ellesmere_populate_memory_timing_parameters(hwmgr,
+ result = polaris10_populate_memory_timing_parameters(hwmgr,
data->dpm_table.sclk_table.dpm_levels[i].value,
data->dpm_table.mclk_table.dpm_levels[j].value,
&arb_regs.entries[i][j]);
}
}
- result = ellesmere_copy_bytes_to_smc(
+ result = polaris10_copy_bytes_to_smc(
hwmgr->smumgr,
data->arb_table_start,
(uint8_t *)&arb_regs,
return result;
}
-static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
int result = -EINVAL;
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
table_info->mm_dep_table;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
table->UvdLevelCount = (uint8_t)(mm_table->count);
table->UvdBootLevel = 0;
return result;
}
-static int ellesmere_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
int result = 0;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
table->GraphicsBootLevel = 0;
table->MemoryBootLevel = 0;
}
-static int ellesmere_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
uint8_t count, level;
return 0;
}
-static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
{
uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
volt_with_cks, value;
uint16_t clock_freq_u16;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
volt_offset = 0;
struct phm_ppt_v1_information *table_info =
ixPWR_CKS_CNTL);
value &= 0xFFC2FF87;
data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
- ellesmere_clock_stretcher_lookup_table[stretch_amount2][0];
+ polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
- ellesmere_clock_stretcher_lookup_table[stretch_amount2][1];
+ polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
- if (ellesmere_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
- && ellesmere_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
+ if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
+ && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
- value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
+ value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
- value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
+ value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
- value |= (ellesmere_clock_stretch_amount_conversion
- [ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]]
+ value |= (polaris10_clock_stretch_amount_conversion
+ [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
[stretch_amount]) << 3;
}
CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
- ellesmere_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
+ polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
- (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
+ (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixPWR_CKS_CNTL, value);
* in the last row of Clock Stretcher Voltage Table.
*/
data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
- (uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][2];
+ (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
- (uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][3];
+ (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
/* Loop through each SCLK and check the frequency
* to see if it lies within the frequency for clock stretcher.
*/
* and it's in 10Khz unit,
* as opposed to Data table, which is in Mhz unit.
*/
- if (clock_freq >= (ellesmere_clock_stretcher_ddt_table[type][i][0]) * 100) {
+ if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
cks_setting |= 0x2;
- if (clock_freq < (ellesmere_clock_stretcher_ddt_table[type][i][1]) * 100)
+ if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
cks_setting |= 0x1;
}
data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
-static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr,
+static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint16_t config;
config = VR_MERGED_WITH_VDDC;
table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
/* Set Vddc Voltage Controller */
- if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
config = VR_SVI2_PLANE_1;
table->VRConfig |= config;
} else {
);
}
/* Set Vddci Voltage Controller */
- if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
config = VR_SVI2_PLANE_2; /* only in merged mode */
table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- } else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
config = VR_SMIO_PATTERN_1;
table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
} else {
table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
}
/* Set Mvdd Voltage Controller */
- if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
+ if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
config = VR_SVI2_PLANE_2;
table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
- } else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
config = VR_SMIO_PATTERN_2;
table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
} else {
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr)
+static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
{
int result;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
- const struct ellesmere_ulv_parm *ulv = &(data->ulv);
+ const struct polaris10_ulv_parm *ulv = &(data->ulv);
uint8_t i;
struct pp_atomctrl_gpio_pin_assignment gpio_pin;
pp_atomctrl_clock_dividers_vi dividers;
- result = ellesmere_setup_default_dpm_tables(hwmgr);
+ result = polaris10_setup_default_dpm_tables(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to setup default DPM tables!", return result);
- if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control)
- ellesmere_populate_smc_voltage_tables(hwmgr, table);
+ if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
+ polaris10_populate_smc_voltage_tables(hwmgr, table);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition))
table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
- result = ellesmere_populate_ulv_state(hwmgr, table);
+ result = polaris10_populate_ulv_state(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize ULV state!", return result);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_ULV_PARAMETER, PPELLESMERE_CGULVPARAMETER_DFLT);
+ ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
}
- result = ellesmere_populate_smc_link_level(hwmgr, table);
+ result = polaris10_populate_smc_link_level(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize Link Level!", return result);
- result = ellesmere_populate_all_graphic_levels(hwmgr);
+ result = polaris10_populate_all_graphic_levels(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize Graphics Level!", return result);
- result = ellesmere_populate_all_memory_levels(hwmgr);
+ result = polaris10_populate_all_memory_levels(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize Memory Level!", return result);
- result = ellesmere_populate_smc_acpi_level(hwmgr, table);
+ result = polaris10_populate_smc_acpi_level(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize ACPI Level!", return result);
- result = ellesmere_populate_smc_vce_level(hwmgr, table);
+ result = polaris10_populate_smc_vce_level(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize VCE Level!", return result);
- result = ellesmere_populate_smc_samu_level(hwmgr, table);
+ result = polaris10_populate_smc_samu_level(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize SAMU Level!", return result);
* (the other states are just copies of the boot state) we only
* need to populate the ARB settings for the initial state.
*/
- result = ellesmere_program_memory_timing_parameters(hwmgr);
+ result = polaris10_program_memory_timing_parameters(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to Write ARB settings for the initial state.", return result);
- result = ellesmere_populate_smc_uvd_level(hwmgr, table);
+ result = polaris10_populate_smc_uvd_level(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize UVD Level!", return result);
- result = ellesmere_populate_smc_boot_level(hwmgr, table);
+ result = polaris10_populate_smc_boot_level(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize Boot Level!", return result);
- result = ellesmere_populate_smc_initailial_state(hwmgr);
+ result = polaris10_populate_smc_initailial_state(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize Boot State!", return result);
- result = ellesmere_populate_bapm_parameters_in_dpm_table(hwmgr);
+ result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate BAPM Parameters!", return result);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ClockStretcher)) {
- result = ellesmere_populate_clock_stretcher_data_table(hwmgr);
+ result = polaris10_populate_clock_stretcher_data_table(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate Clock Stretcher Data Table!",
return result);
table->ThermalInterval = 1;
table->TemperatureLimitHigh =
table_info->cac_dtp_table->usTargetOperatingTemp *
- ELLESMERE_Q88_FORMAT_CONVERSION_UNIT;
+ POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
table->TemperatureLimitLow =
(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
- ELLESMERE_Q88_FORMAT_CONVERSION_UNIT;
+ POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
table->MemoryVoltageChangeEnable = 1;
table->MemoryInterval = 1;
table->VoltageResponseTime = 0;
table->PCIeBootLinkLevel = 0;
table->PCIeGenInterval = 1;
- result = ellesmere_populate_vr_config(hwmgr, table);
+ result = polaris10_populate_vr_config(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate VRConfig setting!", return result);
if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
} else {
- table->VRHotGpio = ELLESMERE_UNUSED_GPIO_PIN;
+ table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot);
}
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
} else {
- table->AcDcGpio = ELLESMERE_UNUSED_GPIO_PIN;
+ table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
}
CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
- result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr,
+ result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
data->dpm_table_start +
offsetof(SMU74_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags),
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr)
+static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
{
- const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t tmp;
int result;
* In reality this field should not be in that structure
* but in a soft register.
*/
- result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+ result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
data->arb_table_start, &tmp, data->sram_end);
if (result)
tmp &= 0x00FFFFFF;
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
- return ellesmere_write_smc_sram_dword(hwmgr->smumgr,
+ return polaris10_write_smc_sram_dword(hwmgr->smumgr,
data->arb_table_start, tmp, data->sram_end);
}
-static int ellesmere_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot))
return 0;
}
-static int ellesmere_enable_sclk_control(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
{
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
SCLK_PWRMGT_OFF, 0);
return 0;
}
-static int ellesmere_enable_ulv(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_ulv_parm *ulv = &(data->ulv);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_ulv_parm *ulv = &(data->ulv);
if (ulv->ulv_supported)
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
return 0;
}
-static int ellesmere_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
return 0;
}
-static int ellesmere_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
/* enable SCLK dpm */
if (!data->sclk_dpm_key_disabled)
return 0;
}
-static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr)
+static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
/*enable general power management */
return -1);
*/
- if (ellesmere_enable_sclk_mclk_dpm(hwmgr)) {
+ if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
return -1;
}
return 0;
}
-static void ellesmere_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
+static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
{
bool protection;
enum DPM_EVENT_SRC src;
THERMAL_PROTECTION_DIS, 1);
}
-static int ellesmere_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
+static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
PHM_AutoThrottleSource source)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (!(data->active_auto_throttle_sources & (1 << source))) {
data->active_auto_throttle_sources |= 1 << source;
- ellesmere_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
+ polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
}
return 0;
}
-static int ellesmere_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
{
- return ellesmere_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
+ return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
}
-int ellesmere_pcie_performance_request(struct pp_hwmgr *hwmgr)
+int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
data->pcie_performance_request = true;
return 0;
}
-int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
- tmp_result = (!ellesmere_is_dpm_running(hwmgr)) ? 0 : -1;
+ tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
PP_ASSERT_WITH_CODE(result == 0,
"DPM is already running right now, no need to enable DPM!",
return 0);
- if (ellesmere_voltage_control(hwmgr)) {
- tmp_result = ellesmere_enable_voltage_control(hwmgr);
+ if (polaris10_voltage_control(hwmgr)) {
+ tmp_result = polaris10_enable_voltage_control(hwmgr);
PP_ASSERT_WITH_CODE(tmp_result == 0,
"Failed to enable voltage control!",
result = tmp_result);
- tmp_result = ellesmere_construct_voltage_tables(hwmgr);
+ tmp_result = polaris10_construct_voltage_tables(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to contruct voltage tables!",
result = tmp_result);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
- tmp_result = ellesmere_program_static_screen_threshold_parameters(hwmgr);
+ tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to program static screen threshold parameters!",
result = tmp_result);
- tmp_result = ellesmere_enable_display_gap(hwmgr);
+ tmp_result = polaris10_enable_display_gap(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable display gap!", result = tmp_result);
- tmp_result = ellesmere_program_voting_clients(hwmgr);
+ tmp_result = polaris10_program_voting_clients(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to program voting clients!", result = tmp_result);
- tmp_result = ellesmere_process_firmware_header(hwmgr);
+ tmp_result = polaris10_process_firmware_header(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to process firmware header!", result = tmp_result);
- tmp_result = ellesmere_initial_switch_from_arbf0_to_f1(hwmgr);
+ tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to initialize switch from ArbF0 to F1!",
result = tmp_result);
- tmp_result = ellesmere_init_smc_table(hwmgr);
+ tmp_result = polaris10_init_smc_table(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to initialize SMC table!", result = tmp_result);
- tmp_result = ellesmere_init_arb_table_index(hwmgr);
+ tmp_result = polaris10_init_arb_table_index(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to initialize ARB table index!", result = tmp_result);
- tmp_result = ellesmere_populate_pm_fuses(hwmgr);
+ tmp_result = polaris10_populate_pm_fuses(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to populate PM fuses!", result = tmp_result);
- tmp_result = ellesmere_enable_vrhot_gpio_interrupt(hwmgr);
+ tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
- tmp_result = ellesmere_enable_sclk_control(hwmgr);
+ tmp_result = polaris10_enable_sclk_control(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable SCLK control!", result = tmp_result);
- tmp_result = ellesmere_enable_smc_voltage_controller(hwmgr);
+ tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable voltage control!", result = tmp_result);
- tmp_result = ellesmere_enable_ulv(hwmgr);
+ tmp_result = polaris10_enable_ulv(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable ULV!", result = tmp_result);
- tmp_result = ellesmere_enable_deep_sleep_master_switch(hwmgr);
+ tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable deep sleep master switch!", result = tmp_result);
- tmp_result = ellesmere_start_dpm(hwmgr);
+ tmp_result = polaris10_start_dpm(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to start DPM!", result = tmp_result);
- tmp_result = ellesmere_enable_smc_cac(hwmgr);
+ tmp_result = polaris10_enable_smc_cac(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable SMC CAC!", result = tmp_result);
- tmp_result = ellesmere_enable_power_containment(hwmgr);
+ tmp_result = polaris10_enable_power_containment(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable power containment!", result = tmp_result);
- tmp_result = ellesmere_power_control_set_level(hwmgr);
+ tmp_result = polaris10_power_control_set_level(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to power control set level!", result = tmp_result);
- tmp_result = ellesmere_enable_thermal_auto_throttle(hwmgr);
+ tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable thermal auto throttle!", result = tmp_result);
- tmp_result = ellesmere_pcie_performance_request(hwmgr);
+ tmp_result = polaris10_pcie_performance_request(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable thermal auto throttle!", result = tmp_result);
return result;
}
-int ellesmere_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
return 0;
}
-int ellesmere_reset_asic_tasks(struct pp_hwmgr *hwmgr)
+int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
{
return 0;
}
-int ellesmere_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
return phm_hwmgr_backend_fini(hwmgr);
}
-int ellesmere_set_features_platform_caps(struct pp_hwmgr *hwmgr)
+int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
- if (data->mvdd_control == ELLESMERE_VOLTAGE_CONTROL_NONE)
+ if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableMVDDControl);
- if (data->vddci_control == ELLESMERE_VOLTAGE_CONTROL_NONE)
+ if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDCI);
return 0;
}
-static void ellesmere_init_dpm_defaults(struct pp_hwmgr *hwmgr)
+static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- ellesmere_initialize_power_tune_defaults(hwmgr);
+ polaris10_initialize_power_tune_defaults(hwmgr);
data->pcie_gen_performance.max = PP_PCIEGen1;
data->pcie_gen_performance.min = PP_PCIEGen3;
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr)
+static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint16_t vv_id;
uint16_t vddc = 0;
uint16_t i, j;
table_info->vdd_dep_on_sclk;
int result;
- for (i = 0; i < ELLESMERE_MAX_LEAKAGE_COUNT; i++) {
+ for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
if (!phm_get_sclk_for_voltage_evv(hwmgr,
table_info->vddc_lookup_table, vv_id, &sclk)) {
* @param pointer to changing voltage
* @param pointer to leakage table
*/
-static void ellesmere_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
- uint16_t *voltage, struct ellesmere_leakage_voltage *leakage_table)
+static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
+ uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
{
uint32_t index;
* @param pointer to leakage table
* @return always 0
*/
-static int ellesmere_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
+static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *lookup_table,
- struct ellesmere_leakage_voltage *leakage_table)
+ struct polaris10_leakage_voltage *leakage_table)
{
uint32_t i;
for (i = 0; i < lookup_table->count; i++)
- ellesmere_patch_with_vdd_leakage(hwmgr,
+ polaris10_patch_with_vdd_leakage(hwmgr,
&lookup_table->entries[i].us_vdd, leakage_table);
return 0;
}
-static int ellesmere_patch_clock_voltage_limits_with_vddc_leakage(
- struct pp_hwmgr *hwmgr, struct ellesmere_leakage_voltage *leakage_table,
+static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
+ struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
uint16_t *vddc)
{
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
- ellesmere_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
+ polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
table_info->max_clock_voltage_on_dc.vddc;
return 0;
}
-static int ellesmere_patch_voltage_dependency_tables_with_lookup_table(
+static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
struct pp_hwmgr *hwmgr)
{
uint8_t entryId;
}
-static int ellesmere_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
+static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
{
/* Need to determine if we need calculated voltage. */
return 0;
}
-static int ellesmere_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
+static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
{
/* Need to determine if we need calculated voltage from mm table. */
return 0;
}
-static int ellesmere_sort_lookup_table(struct pp_hwmgr *hwmgr,
+static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
struct phm_ppt_v1_voltage_lookup_table *lookup_table)
{
uint32_t table_size, i, j;
return 0;
}
-static int ellesmere_complete_dependency_tables(struct pp_hwmgr *hwmgr)
+static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
{
int result = 0;
int tmp_result;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
- tmp_result = ellesmere_patch_lookup_table_with_leakage(hwmgr,
+ tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
table_info->vddc_lookup_table, &(data->vddc_leakage));
if (tmp_result)
result = tmp_result;
- tmp_result = ellesmere_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
+ tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
if (tmp_result)
result = tmp_result;
- tmp_result = ellesmere_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
+ tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
if (tmp_result)
result = tmp_result;
- tmp_result = ellesmere_calc_voltage_dependency_tables(hwmgr);
+ tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
if (tmp_result)
result = tmp_result;
- tmp_result = ellesmere_calc_mm_voltage_dependency_table(hwmgr);
+ tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
if (tmp_result)
result = tmp_result;
- tmp_result = ellesmere_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
+ tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
if (tmp_result)
result = tmp_result;
return result;
}
-static int ellesmere_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
+static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
{
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
return 0;
}
-int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
uint32_t temp_reg;
int result;
data->sram_end = SMC_RAM_END;
data->disable_dpm_mask = 0xFF;
- data->static_screen_threshold = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT;
- data->static_screen_threshold_unit = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT;
- data->activity_target[0] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[1] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[2] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[3] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[4] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[5] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[6] = PPELLESMERE_TARGETACTIVITY_DFLT;
- data->activity_target[7] = PPELLESMERE_TARGETACTIVITY_DFLT;
-
- data->voting_rights_clients0 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0;
- data->voting_rights_clients1 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1;
- data->voting_rights_clients2 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2;
- data->voting_rights_clients3 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3;
- data->voting_rights_clients4 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4;
- data->voting_rights_clients5 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5;
- data->voting_rights_clients6 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6;
- data->voting_rights_clients7 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7;
+ data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
+ data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
+ data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+ data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
+
+ data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
+ data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
+ data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
+ data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
+ data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
+ data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
+ data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
+ data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
- data->mclk_activity_target = PPELLESMERE_MCLK_TARGETACTIVITY_DFLT;
+ data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
/* need to set voltage control types before EVV patching */
- data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
- data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
- data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
+ data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
+ data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
+ data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
- data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
+ data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicPatchPowerState);
PHM_PlatformCaps_EnableMVDDControl)) {
if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
- data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO;
+ data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
- data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
+ data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
}
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDCI)) {
if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
- data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO;
+ data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
- data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
+ data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
}
- ellesmere_set_features_platform_caps(hwmgr);
+ polaris10_set_features_platform_caps(hwmgr);
- ellesmere_init_dpm_defaults(hwmgr);
+ polaris10_init_dpm_defaults(hwmgr);
/* Get leakage voltage based on leakage ID. */
- result = ellesmere_get_evv_voltages(hwmgr);
+ result = polaris10_get_evv_voltages(hwmgr);
if (result) {
printk("Get EVV Voltage Failed. Abort Driver loading!\n");
return -1;
}
- ellesmere_complete_dependency_tables(hwmgr);
- ellesmere_set_private_data_based_on_pptable(hwmgr);
+ polaris10_complete_dependency_tables(hwmgr);
+ polaris10_set_private_data_based_on_pptable(hwmgr);
/* Initalize Dynamic State Adjustment Rule Settings */
result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
data->is_tlu_enabled = 0;
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
- ELLESMERE_MAX_HARDWARE_POWERLEVELS;
+ POLARIS10_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
data->pcie_lane_cap = (uint32_t)sys_info.value;
} else {
/* Ignore return value in here, we are cleaning up a mess. */
- ellesmere_hwmgr_backend_fini(hwmgr);
+ polaris10_hwmgr_backend_fini(hwmgr);
}
return 0;
}
-static int ellesmere_force_dpm_highest(struct pp_hwmgr *hwmgr)
+static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t level, tmp;
if (!data->pcie_dpm_key_disabled) {
return 0;
}
-static int ellesmere_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
+static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
phm_apply_dal_min_voltage_request(hwmgr);
return 0;
}
-static int ellesmere_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
+static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- if (!ellesmere_is_dpm_running(hwmgr))
+ if (!polaris10_is_dpm_running(hwmgr))
return -EINVAL;
if (!data->pcie_dpm_key_disabled) {
PPSMC_MSG_PCIeDPM_UnForceLevel);
}
- return ellesmere_upload_dpm_level_enable_mask(hwmgr);
+ return polaris10_upload_dpm_level_enable_mask(hwmgr);
}
-static int ellesmere_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data =
- (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data =
+ (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t level;
if (!data->sclk_dpm_key_disabled)
return 0;
}
-static int ellesmere_force_dpm_level(struct pp_hwmgr *hwmgr,
+static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
int ret = 0;
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = ellesmere_force_dpm_highest(hwmgr);
+ ret = polaris10_force_dpm_highest(hwmgr);
if (ret)
return ret;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- ret = ellesmere_force_dpm_lowest(hwmgr);
+ ret = polaris10_force_dpm_lowest(hwmgr);
if (ret)
return ret;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
- ret = ellesmere_unforce_dpm_levels(hwmgr);
+ ret = polaris10_unforce_dpm_levels(hwmgr);
if (ret)
return ret;
break;
return ret;
}
-static int ellesmere_get_power_state_size(struct pp_hwmgr *hwmgr)
+static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
{
- return sizeof(struct ellesmere_power_state);
+ return sizeof(struct polaris10_power_state);
}
-static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *request_ps,
const struct pp_power_state *current_ps)
{
- struct ellesmere_power_state *ellesmere_ps =
- cast_phw_ellesmere_power_state(&request_ps->hardware);
+ struct polaris10_power_state *polaris10_ps =
+ cast_phw_polaris10_power_state(&request_ps->hardware);
uint32_t sclk;
uint32_t mclk;
struct PP_Clocks minimum_clocks = {0};
struct cgs_display_info info = {0};
const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
int32_t count;
data->battery_state = (PP_StateUILabel_Battery ==
request_ps->classification.ui_label);
- PP_ASSERT_WITH_CODE(ellesmere_ps->performance_level_count == 2,
+ PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
"VI should always have 2 performance levels",
);
/* Cap clock DPM tables at DC MAX if it is in DC. */
if (PP_PowerSource_DC == hwmgr->power_source) {
- for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
- if (ellesmere_ps->performance_levels[i].memory_clock > max_limits->mclk)
- ellesmere_ps->performance_levels[i].memory_clock = max_limits->mclk;
- if (ellesmere_ps->performance_levels[i].engine_clock > max_limits->sclk)
- ellesmere_ps->performance_levels[i].engine_clock = max_limits->sclk;
+ for (i = 0; i < polaris10_ps->performance_level_count; i++) {
+ if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
+ polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
+ if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
+ polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
}
}
- ellesmere_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
- ellesmere_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
+ polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
+ polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
cgs_get_active_displays_info(hwmgr->device, &info);
if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
- ellesmere_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
+ polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
hwmgr->platform_descriptor.overdriveLimit.engineClock);
if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
- ellesmere_ps->performance_levels[1].engine_clock =
+ polaris10_ps->performance_levels[1].engine_clock =
hwmgr->gfx_arbiter.sclk_over_drive;
}
hwmgr->platform_descriptor.overdriveLimit.memoryClock);
if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
- ellesmere_ps->performance_levels[1].memory_clock =
+ polaris10_ps->performance_levels[1].memory_clock =
hwmgr->gfx_arbiter.mclk_over_drive;
}
disable_mclk_switching = (1 < info.display_count) ||
disable_mclk_switching_for_frame_lock;
- sclk = ellesmere_ps->performance_levels[0].engine_clock;
- mclk = ellesmere_ps->performance_levels[0].memory_clock;
+ sclk = polaris10_ps->performance_levels[0].engine_clock;
+ mclk = polaris10_ps->performance_levels[0].memory_clock;
if (disable_mclk_switching)
- mclk = ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count - 1].memory_clock;
+ mclk = polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count - 1].memory_clock;
if (sclk < minimum_clocks.engineClock)
sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
max_limits->mclk : minimum_clocks.memoryClock;
- ellesmere_ps->performance_levels[0].engine_clock = sclk;
- ellesmere_ps->performance_levels[0].memory_clock = mclk;
+ polaris10_ps->performance_levels[0].engine_clock = sclk;
+ polaris10_ps->performance_levels[0].memory_clock = mclk;
- ellesmere_ps->performance_levels[1].engine_clock =
- (ellesmere_ps->performance_levels[1].engine_clock >=
- ellesmere_ps->performance_levels[0].engine_clock) ?
- ellesmere_ps->performance_levels[1].engine_clock :
- ellesmere_ps->performance_levels[0].engine_clock;
+ polaris10_ps->performance_levels[1].engine_clock =
+ (polaris10_ps->performance_levels[1].engine_clock >=
+ polaris10_ps->performance_levels[0].engine_clock) ?
+ polaris10_ps->performance_levels[1].engine_clock :
+ polaris10_ps->performance_levels[0].engine_clock;
if (disable_mclk_switching) {
- if (mclk < ellesmere_ps->performance_levels[1].memory_clock)
- mclk = ellesmere_ps->performance_levels[1].memory_clock;
+ if (mclk < polaris10_ps->performance_levels[1].memory_clock)
+ mclk = polaris10_ps->performance_levels[1].memory_clock;
- ellesmere_ps->performance_levels[0].memory_clock = mclk;
- ellesmere_ps->performance_levels[1].memory_clock = mclk;
+ polaris10_ps->performance_levels[0].memory_clock = mclk;
+ polaris10_ps->performance_levels[1].memory_clock = mclk;
} else {
- if (ellesmere_ps->performance_levels[1].memory_clock <
- ellesmere_ps->performance_levels[0].memory_clock)
- ellesmere_ps->performance_levels[1].memory_clock =
- ellesmere_ps->performance_levels[0].memory_clock;
+ if (polaris10_ps->performance_levels[1].memory_clock <
+ polaris10_ps->performance_levels[0].memory_clock)
+ polaris10_ps->performance_levels[1].memory_clock =
+ polaris10_ps->performance_levels[0].memory_clock;
}
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) {
- for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
- ellesmere_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
- ellesmere_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
- ellesmere_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
- ellesmere_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
+ for (i = 0; i < polaris10_ps->performance_level_count; i++) {
+ polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
+ polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
+ polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
+ polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
}
}
return 0;
}
-static int ellesmere_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
- struct ellesmere_power_state *ellesmere_ps;
+ struct polaris10_power_state *polaris10_ps;
if (hwmgr == NULL)
return -EINVAL;
if (ps == NULL)
return -EINVAL;
- ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware);
+ polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
if (low)
- return ellesmere_ps->performance_levels[0].memory_clock;
+ return polaris10_ps->performance_levels[0].memory_clock;
else
- return ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count-1].memory_clock;
+ return polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count-1].memory_clock;
}
-static int ellesmere_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
- struct ellesmere_power_state *ellesmere_ps;
+ struct polaris10_power_state *polaris10_ps;
if (hwmgr == NULL)
return -EINVAL;
if (ps == NULL)
return -EINVAL;
- ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware);
+ polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
if (low)
- return ellesmere_ps->performance_levels[0].engine_clock;
+ return polaris10_ps->performance_levels[0].engine_clock;
else
- return ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count-1].engine_clock;
+ return polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count-1].engine_clock;
}
-static int ellesmere_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
+static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_power_state *ps = (struct ellesmere_power_state *)hw_ps;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
ATOM_FIRMWARE_INFO_V2_2 *fw_info;
uint16_t size;
uint8_t frev, crev;
return 0;
}
-static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
+static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
void *state, struct pp_power_state *power_state,
void *pp_table, uint32_t classification_flag)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_power_state *ellesmere_power_state =
- (struct ellesmere_power_state *)(&(power_state->hardware));
- struct ellesmere_performance_level *performance_level;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_power_state *polaris10_power_state =
+ (struct polaris10_power_state *)(&(power_state->hardware));
+ struct polaris10_performance_level *performance_level;
ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
(ATOM_Tonga_POWERPLAYTABLE *)pp_table;
power_state->temperatures.min = 0;
power_state->temperatures.max = 0;
- performance_level = &(ellesmere_power_state->performance_levels
- [ellesmere_power_state->performance_level_count++]);
+ performance_level = &(polaris10_power_state->performance_levels
+ [polaris10_power_state->performance_level_count++]);
PP_ASSERT_WITH_CODE(
- (ellesmere_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
+ (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
"Performance levels exceeds SMC limit!",
return -1);
PP_ASSERT_WITH_CODE(
- (ellesmere_power_state->performance_level_count <=
+ (polaris10_power_state->performance_level_count <=
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
"Performance levels exceeds Driver limit!",
return -1);
performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
state_entry->ucPCIELaneHigh);
- performance_level = &(ellesmere_power_state->performance_levels
- [ellesmere_power_state->performance_level_count++]);
+ performance_level = &(polaris10_power_state->performance_levels
+ [polaris10_power_state->performance_level_count++]);
performance_level->memory_clock = mclk_dep_table->entries
[state_entry->ucMemoryClockIndexHigh].ulMclk;
performance_level->engine_clock = sclk_dep_table->entries
return 0;
}
-static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr,
+static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
unsigned long entry_index, struct pp_power_state *state)
{
int result;
- struct ellesmere_power_state *ps;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_power_state *ps;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
state->hardware.magic = PHM_VIslands_Magic;
- ps = (struct ellesmere_power_state *)(&state->hardware);
+ ps = (struct polaris10_power_state *)(&state->hardware);
result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
- ellesmere_get_pp_table_entry_callback_func);
+ polaris10_get_pp_table_entry_callback_func);
/* This is the earliest time we have all the dependency table and the VBIOS boot state
* as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
}
static void
-ellesmere_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
+polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
{
uint32_t sclk, mclk;
mclk / 100, sclk / 100);
}
-static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
+static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
{
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
- const struct ellesmere_power_state *ellesmere_ps =
- cast_const_phw_ellesmere_power_state(states->pnew_state);
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
- uint32_t sclk = ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count - 1].engine_clock;
- struct ellesmere_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
- uint32_t mclk = ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count - 1].memory_clock;
+ const struct polaris10_power_state *polaris10_ps =
+ cast_const_phw_polaris10_power_state(states->pnew_state);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
+ uint32_t sclk = polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count - 1].engine_clock;
+ struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
+ uint32_t mclk = polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count - 1].memory_clock;
struct PP_Clocks min_clocks = {0};
uint32_t i;
struct cgs_display_info info = {0};
/* TODO: Check SCLK in DAL's minimum clocks
* in case DeepSleep divider update is required.
*/
- if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
+ if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
+ (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
+ data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
}
return 0;
}
-static uint16_t ellesmere_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
- const struct ellesmere_power_state *ellesmere_ps)
+static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
+ const struct polaris10_power_state *polaris10_ps)
{
uint32_t i;
uint32_t sclk, max_sclk = 0;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_dpm_table *dpm_table = &data->dpm_table;
- for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
- sclk = ellesmere_ps->performance_levels[i].engine_clock;
+ for (i = 0; i < polaris10_ps->performance_level_count; i++) {
+ sclk = polaris10_ps->performance_levels[i].engine_clock;
if (max_sclk < sclk)
max_sclk = sclk;
}
return 0;
}
-static int ellesmere_request_link_speed_change_before_state_change(
+static int polaris10_request_link_speed_change_before_state_change(
struct pp_hwmgr *hwmgr, const void *input)
{
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- const struct ellesmere_power_state *ellesmere_nps =
- cast_const_phw_ellesmere_power_state(states->pnew_state);
- const struct ellesmere_power_state *ellesmere_cps =
- cast_const_phw_ellesmere_power_state(states->pcurrent_state);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ const struct polaris10_power_state *polaris10_nps =
+ cast_const_phw_polaris10_power_state(states->pnew_state);
+ const struct polaris10_power_state *polaris10_cps =
+ cast_const_phw_polaris10_power_state(states->pcurrent_state);
- uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_nps);
+ uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
uint16_t current_link_speed;
if (data->force_pcie_gen == PP_PCIEGenInvalid)
- current_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_cps);
+ current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
else
current_link_speed = data->force_pcie_gen;
return 0;
}
-static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
+static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (0 == data->need_update_smu7_dpm_table)
return 0;
if ((0 == data->sclk_dpm_key_disabled) &&
(data->need_update_smu7_dpm_table &
(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
- PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
+ PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
"Trying to freeze SCLK DPM when DPM is disabled",
);
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
if ((0 == data->mclk_dpm_key_disabled) &&
(data->need_update_smu7_dpm_table &
DPMTABLE_OD_UPDATE_MCLK)) {
- PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
+ PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
"Trying to freeze MCLK DPM when DPM is disabled",
);
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
return 0;
}
-static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels(
+static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
struct pp_hwmgr *hwmgr, const void *input)
{
int result = 0;
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
- const struct ellesmere_power_state *ellesmere_ps =
- cast_const_phw_ellesmere_power_state(states->pnew_state);
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- uint32_t sclk = ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count - 1].engine_clock;
- uint32_t mclk = ellesmere_ps->performance_levels
- [ellesmere_ps->performance_level_count - 1].memory_clock;
- struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
-
- struct ellesmere_dpm_table *golden_dpm_table = &data->golden_dpm_table;
+ const struct polaris10_power_state *polaris10_ps =
+ cast_const_phw_polaris10_power_state(states->pnew_state);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ uint32_t sclk = polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count - 1].engine_clock;
+ uint32_t mclk = polaris10_ps->performance_levels
+ [polaris10_ps->performance_level_count - 1].memory_clock;
+ struct polaris10_dpm_table *dpm_table = &data->dpm_table;
+
+ struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
uint32_t dpm_count, clock_percent;
uint32_t i;
if (data->need_update_smu7_dpm_table &
(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
- result = ellesmere_populate_all_graphic_levels(hwmgr);
+ result = polaris10_populate_all_graphic_levels(hwmgr);
PP_ASSERT_WITH_CODE((0 == result),
"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
return result);
if (data->need_update_smu7_dpm_table &
(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
/*populate MCLK dpm table to SMU7 */
- result = ellesmere_populate_all_memory_levels(hwmgr);
+ result = polaris10_populate_all_memory_levels(hwmgr);
PP_ASSERT_WITH_CODE((0 == result),
"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
return result);
return result;
}
-static int ellesmere_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
- struct ellesmere_single_dpm_table *dpm_table,
+static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
+ struct polaris10_single_dpm_table *dpm_table,
uint32_t low_limit, uint32_t high_limit)
{
uint32_t i;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
for (i = 0; i < dpm_table->count; i++) {
if ((dpm_table->dpm_levels[i].value < low_limit)
return 0;
}
-static int ellesmere_trim_dpm_states(struct pp_hwmgr *hwmgr,
- const struct ellesmere_power_state *ellesmere_ps)
+static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
+ const struct polaris10_power_state *polaris10_ps)
{
int result = 0;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t high_limit_count;
- PP_ASSERT_WITH_CODE((ellesmere_ps->performance_level_count >= 1),
+ PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
"power state did not have any performance level",
return -1);
- high_limit_count = (1 == ellesmere_ps->performance_level_count) ? 0 : 1;
+ high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
- ellesmere_trim_single_dpm_states(hwmgr,
+ polaris10_trim_single_dpm_states(hwmgr,
&(data->dpm_table.sclk_table),
- ellesmere_ps->performance_levels[0].engine_clock,
- ellesmere_ps->performance_levels[high_limit_count].engine_clock);
+ polaris10_ps->performance_levels[0].engine_clock,
+ polaris10_ps->performance_levels[high_limit_count].engine_clock);
- ellesmere_trim_single_dpm_states(hwmgr,
+ polaris10_trim_single_dpm_states(hwmgr,
&(data->dpm_table.mclk_table),
- ellesmere_ps->performance_levels[0].memory_clock,
- ellesmere_ps->performance_levels[high_limit_count].memory_clock);
+ polaris10_ps->performance_levels[0].memory_clock,
+ polaris10_ps->performance_levels[high_limit_count].memory_clock);
return result;
}
-static int ellesmere_generate_dpm_level_enable_mask(
+static int polaris10_generate_dpm_level_enable_mask(
struct pp_hwmgr *hwmgr, const void *input)
{
int result;
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- const struct ellesmere_power_state *ellesmere_ps =
- cast_const_phw_ellesmere_power_state(states->pnew_state);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ const struct polaris10_power_state *polaris10_ps =
+ cast_const_phw_polaris10_power_state(states->pnew_state);
- result = ellesmere_trim_dpm_states(hwmgr, ellesmere_ps);
+ result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
if (result)
return result;
return 0;
}
-int ellesmere_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
+int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
PPSMC_MSG_UVDDPM_Enable :
PPSMC_MSG_UVDDPM_Disable);
}
-int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
+int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable?
PPSMC_MSG_VCEDPM_Enable :
PPSMC_MSG_VCEDPM_Disable);
}
-int ellesmere_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
+int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable?
PPSMC_MSG_SAMUDPM_Enable :
PPSMC_MSG_SAMUDPM_Disable);
}
-int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
+int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t mm_boot_level_offset, mm_boot_level_value;
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
}
- return ellesmere_enable_disable_uvd_dpm(hwmgr, !bgate);
+ return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
}
-static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
+static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
{
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- const struct ellesmere_power_state *ellesmere_nps =
- cast_const_phw_ellesmere_power_state(states->pnew_state);
- const struct ellesmere_power_state *ellesmere_cps =
- cast_const_phw_ellesmere_power_state(states->pcurrent_state);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ const struct polaris10_power_state *polaris10_nps =
+ cast_const_phw_polaris10_power_state(states->pnew_state);
+ const struct polaris10_power_state *polaris10_cps =
+ cast_const_phw_polaris10_power_state(states->pcurrent_state);
uint32_t mm_boot_level_offset, mm_boot_level_value;
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
- if (ellesmere_nps->vce_clks.evclk > 0 &&
- (ellesmere_cps == NULL || ellesmere_cps->vce_clks.evclk == 0)) {
+ if (polaris10_nps->vce_clks.evclk > 0 &&
+ (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
data->smc_state_table.VceBootLevel =
(uint8_t) (table_info->mm_dep_table->count - 1);
PPSMC_MSG_VCEDPM_SetEnabledMask,
(uint32_t)1 << data->smc_state_table.VceBootLevel);
- ellesmere_enable_disable_vce_dpm(hwmgr, true);
- } else if (ellesmere_nps->vce_clks.evclk == 0 &&
- ellesmere_cps != NULL &&
- ellesmere_cps->vce_clks.evclk > 0)
- ellesmere_enable_disable_vce_dpm(hwmgr, false);
+ polaris10_enable_disable_vce_dpm(hwmgr, true);
+ } else if (polaris10_nps->vce_clks.evclk == 0 &&
+ polaris10_cps != NULL &&
+ polaris10_cps->vce_clks.evclk > 0)
+ polaris10_enable_disable_vce_dpm(hwmgr, false);
}
return 0;
}
-int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
+int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t mm_boot_level_offset, mm_boot_level_value;
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
(uint32_t)(1 << data->smc_state_table.SamuBootLevel));
}
- return ellesmere_enable_disable_samu_dpm(hwmgr, !bgate);
+ return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
}
-static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
int result = 0;
uint32_t low_sclk_interrupt_threshold = 0;
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
- result = ellesmere_copy_bytes_to_smc(
+ result = polaris10_copy_bytes_to_smc(
hwmgr->smumgr,
data->dpm_table_start +
offsetof(SMU74_Discrete_DpmTable,
return result;
}
-static int ellesmere_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (data->need_update_smu7_dpm_table &
(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
- return ellesmere_program_memory_timing_parameters(hwmgr);
+ return polaris10_program_memory_timing_parameters(hwmgr);
return 0;
}
-static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
+static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (0 == data->need_update_smu7_dpm_table)
return 0;
(data->need_update_smu7_dpm_table &
(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
- PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
+ PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
"Trying to Unfreeze SCLK DPM when DPM is disabled",
);
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
if ((0 == data->mclk_dpm_key_disabled) &&
(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
- PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
+ PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
"Trying to Unfreeze MCLK DPM when DPM is disabled",
);
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
return 0;
}
-static int ellesmere_notify_link_speed_change_after_state_change(
+static int polaris10_notify_link_speed_change_after_state_change(
struct pp_hwmgr *hwmgr, const void *input)
{
const struct phm_set_power_state_input *states =
(const struct phm_set_power_state_input *)input;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
- const struct ellesmere_power_state *ellesmere_ps =
- cast_const_phw_ellesmere_power_state(states->pnew_state);
- uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_ps);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ const struct polaris10_power_state *polaris10_ps =
+ cast_const_phw_polaris10_power_state(states->pnew_state);
+ uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
uint8_t request;
if (data->pspp_notify_required) {
return 0;
}
-static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
{
int tmp_result, result = 0;
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- tmp_result = ellesmere_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
+ tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to find DPM states clocks in DPM table!",
result = tmp_result);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PCIEPerformanceRequest)) {
tmp_result =
- ellesmere_request_link_speed_change_before_state_change(hwmgr, input);
+ polaris10_request_link_speed_change_before_state_change(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to request link speed change before state change!",
result = tmp_result);
}
- tmp_result = ellesmere_freeze_sclk_mclk_dpm(hwmgr);
+ tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to freeze SCLK MCLK DPM!", result = tmp_result);
- tmp_result = ellesmere_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
+ tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to populate and upload SCLK MCLK DPM levels!",
result = tmp_result);
- tmp_result = ellesmere_generate_dpm_level_enable_mask(hwmgr, input);
+ tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to generate DPM level enabled mask!",
result = tmp_result);
- tmp_result = ellesmere_update_vce_dpm(hwmgr, input);
+ tmp_result = polaris10_update_vce_dpm(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to update VCE DPM!",
result = tmp_result);
- tmp_result = ellesmere_update_sclk_threshold(hwmgr);
+ tmp_result = polaris10_update_sclk_threshold(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to update SCLK threshold!",
result = tmp_result);
- tmp_result = ellesmere_program_mem_timing_parameters(hwmgr);
+ tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to program memory timing parameters!",
result = tmp_result);
- tmp_result = ellesmere_unfreeze_sclk_mclk_dpm(hwmgr);
+ tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to unfreeze SCLK MCLK DPM!",
result = tmp_result);
- tmp_result = ellesmere_upload_dpm_level_enable_mask(hwmgr);
+ tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to upload DPM level enabled mask!",
result = tmp_result);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PCIEPerformanceRequest)) {
tmp_result =
- ellesmere_notify_link_speed_change_after_state_change(hwmgr, input);
+ polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to notify link speed change after state change!",
result = tmp_result);
return result;
}
-static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
+static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
{
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
}
-int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
+int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
{
PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
}
-int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
+int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
uint32_t num_active_displays = 0;
struct cgs_display_info info = {0};
num_active_displays = info.display_count;
if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
- ellesmere_notify_smc_display_change(hwmgr, false);
+ polaris10_notify_smc_display_change(hwmgr, false);
else
- ellesmere_notify_smc_display_change(hwmgr, true);
+ polaris10_notify_smc_display_change(hwmgr, true);
return 0;
}
* @param hwmgr the address of the powerplay hardware manager.
* @return always OK
*/
-int ellesmere_program_display_gap(struct pp_hwmgr *hwmgr)
+int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t num_active_displays = 0;
uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
uint32_t display_gap2;
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
- if (num_active_displays == 1)
- ellesmere_notify_smc_display_change(hwmgr, true);
+ polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
return 0;
}
-int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
+int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
{
- return ellesmere_program_display_gap(hwmgr);
+ return polaris10_program_display_gap(hwmgr);
}
/**
* @param usMaxFanRpm: max operating fan RPM value.
* @return The response that came from the SMC.
*/
-static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
+static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
{
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
}
-int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
+int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
const void *thermal_interrupt_info)
{
return 0;
}
-bool ellesmere_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
+bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
bool is_update_required = false;
struct cgs_display_info info = {0, 0, NULL};
/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
- if (min_clocks.engineClockInSR != data->display_timing.minClockInSR)
+ if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
+ (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
+ data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
is_update_required = true;
*/
return is_update_required;
}
-static inline bool ellesmere_are_power_levels_equal(const struct ellesmere_performance_level *pl1,
- const struct ellesmere_performance_level *pl2)
+static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
+ const struct polaris10_performance_level *pl2)
{
return ((pl1->memory_clock == pl2->memory_clock) &&
(pl1->engine_clock == pl2->engine_clock) &&
(pl1->pcie_lane == pl2->pcie_lane));
}
-int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
+int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
{
- const struct ellesmere_power_state *psa = cast_const_phw_ellesmere_power_state(pstate1);
- const struct ellesmere_power_state *psb = cast_const_phw_ellesmere_power_state(pstate2);
+ const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
+ const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
int i;
if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
}
for (i = 0; i < psa->performance_level_count; i++) {
- if (!ellesmere_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
+ if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
/* If we have found even one performance level pair that is different the states are different. */
*equal = false;
return 0;
return 0;
}
-int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr)
+int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t vbios_version;
* PPMCME_FirmwareDescriptorEntry *pfd = NULL;
pfd = &tonga_mcmeFirmware;
if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
- ellesmere_load_mc_microcode(hwmgr, pfd->dpmThreshold,
+ polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
*/
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_read_clock_registers(struct pp_hwmgr *hwmgr)
+static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_get_memory_type(struct pp_hwmgr *hwmgr)
+static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t temp;
temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
+static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
{
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
GENERAL_PWRMGT, STATIC_PM_EN, 1);
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-static int ellesmere_init_power_gate_state(struct pp_hwmgr *hwmgr)
+static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
data->uvd_power_gated = false;
data->vce_power_gated = false;
return 0;
}
-static int ellesmere_init_sclk_threshold(struct pp_hwmgr *hwmgr)
+static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
data->low_sclk_interrupt_threshold = 0;
return 0;
}
-int ellesmere_setup_asic_task(struct pp_hwmgr *hwmgr)
+int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
- ellesmere_upload_mc_firmware(hwmgr);
+ polaris10_upload_mc_firmware(hwmgr);
- tmp_result = ellesmere_read_clock_registers(hwmgr);
+ tmp_result = polaris10_read_clock_registers(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to read clock registers!", result = tmp_result);
- tmp_result = ellesmere_get_memory_type(hwmgr);
+ tmp_result = polaris10_get_memory_type(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to get memory type!", result = tmp_result);
- tmp_result = ellesmere_enable_acpi_power_management(hwmgr);
+ tmp_result = polaris10_enable_acpi_power_management(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable ACPI power management!", result = tmp_result);
- tmp_result = ellesmere_init_power_gate_state(hwmgr);
+ tmp_result = polaris10_init_power_gate_state(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to init power gate state!", result = tmp_result);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to get MC microcode version!", result = tmp_result);
- tmp_result = ellesmere_init_sclk_threshold(hwmgr);
+ tmp_result = polaris10_init_sclk_threshold(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to init sclk threshold!", result = tmp_result);
return result;
}
-static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
- .backend_init = &ellesmere_hwmgr_backend_init,
- .backend_fini = &ellesmere_hwmgr_backend_fini,
- .asic_setup = &ellesmere_setup_asic_task,
- .dynamic_state_management_enable = &ellesmere_enable_dpm_tasks,
- .apply_state_adjust_rules = ellesmere_apply_state_adjust_rules,
- .force_dpm_level = &ellesmere_force_dpm_level,
- .power_state_set = ellesmere_set_power_state_tasks,
- .get_power_state_size = ellesmere_get_power_state_size,
- .get_mclk = ellesmere_dpm_get_mclk,
- .get_sclk = ellesmere_dpm_get_sclk,
- .patch_boot_state = ellesmere_dpm_patch_boot_state,
- .get_pp_table_entry = ellesmere_get_pp_table_entry,
+static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
+{
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+
+ *table = (char *)&data->smc_state_table;
+
+ return sizeof(struct SMU74_Discrete_DpmTable);
+}
+
+static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
+{
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+
+ void *table = (void *)&data->smc_state_table;
+
+ memcpy(table, buf, size);
+
+ return 0;
+}
+
+static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
+ enum pp_clock_type type, int level)
+{
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+
+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+ return -EINVAL;
+
+ switch (type) {
+ case PP_SCLK:
+ if (!data->sclk_dpm_key_disabled)
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_SCLKDPM_SetEnabledMask,
+ (1 << level));
+ break;
+ case PP_MCLK:
+ if (!data->mclk_dpm_key_disabled)
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_MCLKDPM_SetEnabledMask,
+ (1 << level));
+ break;
+ case PP_PCIE:
+ if (!data->pcie_dpm_key_disabled)
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_PCIeDPM_ForceLevel,
+ (1 << level));
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
+{
+ uint32_t speedCntl = 0;
+
+ /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
+ speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
+ ixPCIE_LC_SPEED_CNTL);
+ return((uint16_t)PHM_GET_FIELD(speedCntl,
+ PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
+}
+
+static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
+ enum pp_clock_type type, char *buf)
+{
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+ struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
+ struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
+ struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
+ int i, now, size = 0;
+ uint32_t clock, pcie_speed;
+
+ switch (type) {
+ case PP_SCLK:
+ smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
+ clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+
+ for (i = 0; i < sclk_table->count; i++) {
+ if (clock > sclk_table->dpm_levels[i].value)
+ continue;
+ break;
+ }
+ now = i;
+
+ for (i = 0; i < sclk_table->count; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, sclk_table->dpm_levels[i].value / 100,
+ (i == now) ? "*" : "");
+ break;
+ case PP_MCLK:
+ smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
+ clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+
+ for (i = 0; i < mclk_table->count; i++) {
+ if (clock > mclk_table->dpm_levels[i].value)
+ continue;
+ break;
+ }
+ now = i;
+
+ for (i = 0; i < mclk_table->count; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, mclk_table->dpm_levels[i].value / 100,
+ (i == now) ? "*" : "");
+ break;
+ case PP_PCIE:
+ pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
+ for (i = 0; i < pcie_table->count; i++) {
+ if (pcie_speed != pcie_table->dpm_levels[i].value)
+ continue;
+ break;
+ }
+ now = i;
+
+ for (i = 0; i < pcie_table->count; i++)
+ size += sprintf(buf + size, "%d: %s %s\n", i,
+ (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
+ (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
+ (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
+ (i == now) ? "*" : "");
+ break;
+ default:
+ break;
+ }
+ return size;
+}
+
+static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
+ .backend_init = &polaris10_hwmgr_backend_init,
+ .backend_fini = &polaris10_hwmgr_backend_fini,
+ .asic_setup = &polaris10_setup_asic_task,
+ .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
+ .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
+ .force_dpm_level = &polaris10_force_dpm_level,
+ .power_state_set = polaris10_set_power_state_tasks,
+ .get_power_state_size = polaris10_get_power_state_size,
+ .get_mclk = polaris10_dpm_get_mclk,
+ .get_sclk = polaris10_dpm_get_sclk,
+ .patch_boot_state = polaris10_dpm_patch_boot_state,
+ .get_pp_table_entry = polaris10_get_pp_table_entry,
.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
- .print_current_perforce_level = ellesmere_print_current_perforce_level,
- .powerdown_uvd = ellesmere_phm_powerdown_uvd,
- .powergate_uvd = ellesmere_phm_powergate_uvd,
- .powergate_vce = ellesmere_phm_powergate_vce,
- .disable_clock_power_gating = ellesmere_phm_disable_clock_power_gating,
- .update_clock_gatings = ellesmere_phm_update_clock_gatings,
- .notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment,
- .display_config_changed = ellesmere_display_configuration_changed_task,
- .set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
- .set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output,
- .get_temperature = ellesmere_thermal_get_temperature,
- .stop_thermal_controller = ellesmere_thermal_stop_thermal_controller,
- .get_fan_speed_info = ellesmere_fan_ctrl_get_fan_speed_info,
- .get_fan_speed_percent = ellesmere_fan_ctrl_get_fan_speed_percent,
- .set_fan_speed_percent = ellesmere_fan_ctrl_set_fan_speed_percent,
- .reset_fan_speed_to_default = ellesmere_fan_ctrl_reset_fan_speed_to_default,
- .get_fan_speed_rpm = ellesmere_fan_ctrl_get_fan_speed_rpm,
- .set_fan_speed_rpm = ellesmere_fan_ctrl_set_fan_speed_rpm,
- .uninitialize_thermal_controller = ellesmere_thermal_ctrl_uninitialize_thermal_controller,
- .register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt,
- .check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration,
- .check_states_equal = ellesmere_check_states_equal,
- .get_pp_table = ellesmere_get_pp_table,
- .set_pp_table = ellesmere_set_pp_table,
- .force_clock_level = ellesmere_force_clock_level,
- .print_clock_levels = ellesmere_print_clock_levels,
- .enable_per_cu_power_gating = ellesmere_phm_enable_per_cu_power_gating,
+ .print_current_perforce_level = polaris10_print_current_perforce_level,
+ .powerdown_uvd = polaris10_phm_powerdown_uvd,
+ .powergate_uvd = polaris10_phm_powergate_uvd,
+ .powergate_vce = polaris10_phm_powergate_vce,
+ .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
+ .update_clock_gatings = polaris10_phm_update_clock_gatings,
+ .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
+ .display_config_changed = polaris10_display_configuration_changed_task,
+ .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
+ .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
+ .get_temperature = polaris10_thermal_get_temperature,
+ .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
+ .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
+ .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
+ .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
+ .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
+ .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
+ .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
+ .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
+ .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
+ .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
+ .check_states_equal = polaris10_check_states_equal,
+ .get_pp_table = polaris10_get_pp_table,
+ .set_pp_table = polaris10_set_pp_table,
+ .force_clock_level = polaris10_force_clock_level,
+ .print_clock_levels = polaris10_print_clock_levels,
+ .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
};
-int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
+int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
{
- struct ellesmere_hwmgr *data;
+ struct polaris10_hwmgr *data;
- data = kzalloc (sizeof(struct ellesmere_hwmgr), GFP_KERNEL);
+ data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
hwmgr->backend = data;
- hwmgr->hwmgr_func = &ellesmere_hwmgr_funcs;
+ hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
hwmgr->pptable_func = &tonga_pptable_funcs;
- pp_ellesmere_thermal_initialize(hwmgr);
+ pp_polaris10_thermal_initialize(hwmgr);
return 0;
}
#include "smumgr.h"
#include "smu74.h"
#include "smu_ucode_xfer_vi.h"
-#include "ellesmere_smumgr.h"
+#include "polaris10_smumgr.h"
#include "smu74_discrete.h"
#include "smu/smu_7_1_3_d.h"
#include "smu/smu_7_1_3_sh_mask.h"
#include "gca/gfx_8_0_d.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
-#include "ellesmere_pwrvirus.h"
+#include "polaris10_pwrvirus.h"
#include "ppatomctrl.h"
#include "pp_debug.h"
#include "cgs_common.h"
-#define ELLESMERE_SMC_SIZE 0x20000
+#define POLARIS10_SMC_SIZE 0x20000
#define VOLTAGE_SCALE 4
/* Microcode file is stored in this buffer */
#define SMC_RAM_END 0x40000
-SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = {
+SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
/* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
/* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
{ 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
{ 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
};
-SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
+SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
/**
* @param smumgr the address of the powerplay hardware manager.
* @param smcAddress the address in the SMC RAM to access.
*/
-static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
+static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
{
PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
* @param src the byte array to copy the bytes to.
* @param byte_count the number of bytes to copy.
*/
-int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
+int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
{
uint32_t data;
uint32_t addr;
addr = smc_start_address;
while (byte_count >= 4) {
- ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
+ polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
*dest = PP_SMC_TO_HOST_UL(data);
}
if (byte_count) {
- ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
+ polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
*pdata = PP_SMC_TO_HOST_UL(data);
/* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
dest_byte = (uint8_t *)dest;
* @param src the byte array to copy the bytes from.
* @param byte_count the number of bytes to copy.
*/
-int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
+int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit)
{
int result;
/* Bytes are written into the SMC addres space with the MSB first. */
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
- result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
+ result = polaris10_set_smc_sram_address(smumgr, addr, limit);
if (0 != result)
return result;
data = 0;
- result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
+ result = polaris10_set_smc_sram_address(smumgr, addr, limit);
if (0 != result)
return result;
data |= (original_data & ~((~0UL) << extra_shift));
- result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
+ result = polaris10_set_smc_sram_address(smumgr, addr, limit);
if (0 != result)
return result;
}
-static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr)
+static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
{
static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
- ellesmere_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
+ polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
return 0;
}
*
* @param smumgr the address of the powerplay hardware manager.
*/
-bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr)
+bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
{
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
* @param msg the message to send.
* @return The response that came from the SMC.
*/
-int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
{
- if (!ellesmere_is_smc_ram_running(smumgr))
+ if (!polaris10_is_smc_ram_running(smumgr))
return -1;
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
* @param msg the message to send.
* @return Always return 0.
*/
-int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
+int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
{
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
* @param parameter: the parameter to send
* @return The response that came from the SMC.
*/
-int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
+int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
{
- if (!ellesmere_is_smc_ram_running(smumgr)) {
+ if (!polaris10_is_smc_ram_running(smumgr)) {
return -1;
}
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
- return ellesmere_send_msg_to_smc(smumgr, msg);
+ return polaris10_send_msg_to_smc(smumgr, msg);
}
* @param parameter: the parameter to send
* @return The response that came from the SMC.
*/
-int ellesmere_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
+int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
{
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
- return ellesmere_send_msg_to_smc_without_waiting(smumgr, msg);
+ return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
}
-int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
+int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
{
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
* @param msg the message to send.
* @return The response that came from the SMC.
*/
-int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr)
+int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr)
{
/* If the SMC is not even on it qualifies as inactive. */
- if (!ellesmere_is_smc_ram_running(smumgr))
+ if (!polaris10_is_smc_ram_running(smumgr))
return -1;
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
* @param smumgr the address of the powerplay hardware manager.
* @param pFirmware the data structure containing the various sections of the firmware.
*/
-static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
+static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
{
uint32_t byte_count = length;
return 0;
}
-static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
+static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type)
{
enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
return result;
}
-static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr)
+static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr)
{
int result = 0;
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct cgs_firmware_info info = {0};
if (smu_data->security_hard_key == 1)
cgs_get_firmware_info(smumgr->device,
- ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
+ polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
else
cgs_get_firmware_info(smumgr->device,
- ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
+ polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
- result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE);
+ result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE);
return result;
}
* @param smcAddress the address in the SMC RAM to access.
* @param value and output parameter for the data read from the SMC SRAM.
*/
-int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
+int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
{
int result;
- result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
+ result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
if (result)
return result;
* @param smc_addr the address in the SMC RAM to access.
* @param value to write to the SMC SRAM.
*/
-int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
+int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
{
int result;
- result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
+ result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
if (result)
return result;
}
-int ellesmere_smu_fini(struct pp_smumgr *smumgr)
+int polaris10_smu_fini(struct pp_smumgr *smumgr)
{
if (smumgr->backend) {
kfree(smumgr->backend);
}
/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
-static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type)
+static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type)
{
uint32_t result = 0;
/* Populate one firmware image to the data structure */
-static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr,
+static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr,
uint32_t fw_type,
struct SMU_Entry *entry)
{
struct cgs_firmware_info info = {0};
result = cgs_get_firmware_info(smumgr->device,
- ellesmere_convert_fw_type_to_cgs(fw_type),
+ polaris10_convert_fw_type_to_cgs(fw_type),
&info);
if (!result) {
return 0;
}
-static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr)
+static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr)
{
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
uint32_t fw_to_load;
int result = 0;
smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
0x0);
- ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
- ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
+ polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
+ polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
toc = (struct SMU_DRAMData_TOC *)smu_data->header;
toc->num_entries = 0;
toc->structure_version = 1;
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
+ PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
- ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
- ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
+ polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
+ polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
fw_to_load = UCODE_ID_RLC_G_MASK
+ UCODE_ID_SDMA0_MASK
+ UCODE_ID_CP_PFP_MASK
+ UCODE_ID_CP_MEC_MASK;
- if (ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
+ if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
printk(KERN_ERR "Fail to Request SMU Load uCode");
return result;
}
/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
-static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
+static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
{
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
- uint32_t fw_mask = ellesmere_get_mask_for_firmware_type(fw_type);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
+ uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type);
uint32_t ret;
/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
return ret;
}
-static int ellesmere_reload_firmware(struct pp_smumgr *smumgr)
+static int polaris10_reload_firmware(struct pp_smumgr *smumgr)
{
return smumgr->smumgr_funcs->start_smu(smumgr);
}
-static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr)
+static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
{
int i;
int result = -1;
uint32_t reg, data;
PWR_Command_Table *pvirus = pwr_virus_table;
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
return result;
}
-static int ellesmere_perform_btc(struct pp_smumgr *smumgr)
+static int polaris10_perform_btc(struct pp_smumgr *smumgr)
{
int result = 0;
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
if (0 != smu_data->avfs.avfs_btc_param) {
- if (0 != ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
- printk("[AVFS][SmuEllesmere_PerformBtc] PerformBTC SMU msg failed");
+ if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
+ printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
result = -1;
}
}
}
-int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr)
+int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
{
uint32_t vr_config;
uint32_t dpm_table_start;
uint16_t u16_boot_mvdd;
uint32_t graphics_level_address, vr_config_address, graphics_level_size;
- graphics_level_size = sizeof(avfs_graphics_level_ellesmere);
+ graphics_level_size = sizeof(avfs_graphics_level_polaris10);
u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
- PP_ASSERT_WITH_CODE(0 == ellesmere_read_smc_sram_dword(smumgr,
+ PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
&dpm_table_start, 0x40000),
- "[AVFS][Ellesmere_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
+ "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
return -1);
/* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
- PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, vr_config_address,
+ PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address,
(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
- "[AVFS][Ellesmere_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
+ "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
return -1);
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
- PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
- (uint8_t *)(&avfs_graphics_level_ellesmere),
+ PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
+ (uint8_t *)(&avfs_graphics_level_polaris10),
graphics_level_size, 0x40000),
- "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
+ "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
return -1);
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
- PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
- (uint8_t *)(&avfs_memory_level_ellesmere), sizeof(avfs_memory_level_ellesmere), 0x40000),
- "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
+ PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
+ (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
+ "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
return -1);
/* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
- PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
+ PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
- "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of DPM table failed!",
+ "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1);
return 0;
}
-int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
+int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
{
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY:
case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
- PP_ASSERT_WITH_CODE(0 == ellesmere_setup_graphics_level_structure(smumgr),
- "[AVFS][Ellesmere_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
+ PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
+ "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
return -1);
if (smu_data->avfs.avfs_btc_param > 1) {
- printk("[AVFS][Ellesmere_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
+ printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
- PP_ASSERT_WITH_CODE(-1 == ellesmere_setup_pwr_virus(smumgr),
- "[AVFS][Ellesmere_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
+ PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
+ "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
return -1);
}
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
- PP_ASSERT_WITH_CODE(0 == ellesmere_perform_btc(smumgr),
- "[AVFS][Ellesmere_AVFSEventMgr] Failure at SmuEllesmere_PerformBTC. AVFS Disabled",
+ PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
+ "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
return -1);
break;
return 0;
}
-static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
+static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
{
int result = 0;
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- result = ellesmere_upload_smu_firmware_image(smumgr);
+ result = polaris10_upload_smu_firmware_image(smumgr);
if (result != 0)
return result;
/* Call Test SMU message with 0x20000 offset to trigger SMU start */
- ellesmere_send_msg_to_smc_offset(smumgr);
+ polaris10_send_msg_to_smc_offset(smumgr);
/* Wait done bit to be set */
/* Check pass/failed indicator */
return result;
}
-static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
+static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
{
int result = 0;
SMC_SYSCON_RESET_CNTL,
rst_reg, 1);
- result = ellesmere_upload_smu_firmware_image(smumgr);
+ result = polaris10_upload_smu_firmware_image(smumgr);
if (result != 0)
return result;
/* Set smc instruct start point at 0x0 */
- ellesmere_program_jump_on_start(smumgr);
+ polaris10_program_jump_on_start(smumgr);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
return result;
}
-static int ellesmere_start_smu(struct pp_smumgr *smumgr)
+static int polaris10_start_smu(struct pp_smumgr *smumgr)
{
int result = 0;
- struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
bool SMU_VFT_INTACT;
/* Only start SMC if SMC RAM is not running */
- if (!ellesmere_is_smc_ram_running(smumgr)) {
+ if (!polaris10_is_smc_ram_running(smumgr)) {
SMU_VFT_INTACT = false;
smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
/* Check if SMU is running in protected mode */
if (smu_data->protected_mode == 0) {
- result = ellesmere_start_smu_in_non_protection_mode(smumgr);
+ result = polaris10_start_smu_in_non_protection_mode(smumgr);
} else {
- result = ellesmere_start_smu_in_protection_mode(smumgr);
+ result = polaris10_start_smu_in_protection_mode(smumgr);
/* If failed, try with different security Key. */
if (result != 0) {
smu_data->security_hard_key ^= 1;
- result = ellesmere_start_smu_in_protection_mode(smumgr);
+ result = polaris10_start_smu_in_protection_mode(smumgr);
}
}
if (result != 0)
PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
- ellesmere_avfs_event_mgr(smumgr, true);
+ polaris10_avfs_event_mgr(smumgr, true);
} else
SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
smu_data->post_initial_boot = true;
- ellesmere_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
+ polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
- ellesmere_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
+ polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
&(smu_data->soft_regs_start), 0x40000);
- result = ellesmere_request_smu_load_fw(smumgr);
+ result = polaris10_request_smu_load_fw(smumgr);
return result;
}
-static int ellesmere_smu_init(struct pp_smumgr *smumgr)
+static int polaris10_smu_init(struct pp_smumgr *smumgr)
{
- struct ellesmere_smumgr *smu_data;
+ struct polaris10_smumgr *smu_data;
uint8_t *internal_buf;
uint64_t mc_addr = 0;
/* Allocate memory for backend private data */
- smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
+ smu_data = (struct polaris10_smumgr *)(smumgr->backend);
smu_data->header_buffer.data_size =
((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
smu_data->smu_buffer.data_size = 200*4096;
}
static const struct pp_smumgr_func ellsemere_smu_funcs = {
- .smu_init = ellesmere_smu_init,
- .smu_fini = ellesmere_smu_fini,
- .start_smu = ellesmere_start_smu,
- .check_fw_load_finish = ellesmere_check_fw_load_finish,
- .request_smu_load_fw = ellesmere_reload_firmware,
+ .smu_init = polaris10_smu_init,
+ .smu_fini = polaris10_smu_fini,
+ .start_smu = polaris10_start_smu,
+ .check_fw_load_finish = polaris10_check_fw_load_finish,
+ .request_smu_load_fw = polaris10_reload_firmware,
.request_smu_load_specific_fw = NULL,
- .send_msg_to_smc = ellesmere_send_msg_to_smc,
- .send_msg_to_smc_with_parameter = ellesmere_send_msg_to_smc_with_parameter,
+ .send_msg_to_smc = polaris10_send_msg_to_smc,
+ .send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
};
-int ellesmere_smum_init(struct pp_smumgr *smumgr)
+int polaris10_smum_init(struct pp_smumgr *smumgr)
{
- struct ellesmere_smumgr *ellesmere_smu = NULL;
+ struct polaris10_smumgr *polaris10_smu = NULL;
- ellesmere_smu = kzalloc(sizeof(struct ellesmere_smumgr), GFP_KERNEL);
+ polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
- if (ellesmere_smu == NULL)
+ if (polaris10_smu == NULL)
return -1;
- smumgr->backend = ellesmere_smu;
+ smumgr->backend = polaris10_smu;
smumgr->smumgr_funcs = &ellsemere_smu_funcs;
return 0;
projects / karo-tx-linux.git / commitdiff