clk: tegra: Read correct IDDQ register in PLL_SS registration

This fixes a bug in tegra_clk_register_pllss() which mistakenly assume
the IDDQ register is the PLL base address.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 9ca1120262f056a7a2e1321c762b81482cb0d8a7..a534bfab30b39ee53c81a89c3a5c5b1d2979144e 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1934,7 +1934,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
        struct clk *clk, *parent;
        struct tegra_clk_pll_freq_table cfg;
        unsigned long parent_rate;
-       u32 val;
+       u32 val, val_iddq;
        int i;
 
        if (!pll_params->div_nmp)
@@ -1981,14 +1981,17 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
        pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
 
        val = pll_readl_base(pll);
+       val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
        if (val & PLL_BASE_ENABLE) {
-               if (val & BIT(pll_params->iddq_bit_idx)) {
+               if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
                        WARN(1, "%s is on but IDDQ set\n", name);
                        kfree(pll);
                        return ERR_PTR(-EINVAL);
                }
-       } else
-               val |= BIT(pll_params->iddq_bit_idx);
+       } else {
+               val_iddq |= BIT(pll_params->iddq_bit_idx);
+               writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
+       }
 
        val &= ~PLLSS_LOCK_OVERRIDE;
        pll_writel_base(val, pll);