gic_unmask_irq(irq_get_irq_data(irq));
local_irq_restore(flags);
}
+void __cpuinit gic_disable_ppi(unsigned int irq)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ irq_set_status_flags(irq, IRQ_NOPROBE);
+ gic_mask_irq(irq_get_irq_data(irq));
+ local_irq_restore(flags);
+}
void save_gic_cpu_state(unsigned int gic_nr, struct gic_cpu_state *gcs)
{
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
void gic_enable_ppi(unsigned int);
+void gic_disable_ppi(unsigned int);
void save_gic_cpu_state(unsigned int gic_nr, struct gic_cpu_state *gcs);
void restore_gic_cpu_state(unsigned int gic_nr, struct gic_cpu_state *gcs);
void save_gic_dist_state(unsigned int gic_nr, struct gic_dist_state *gds);
ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
| TWD_TIMER_CONTROL_PERIODIC;
__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
+ gic_enable_ppi(clk->irq);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
+ gic_enable_ppi(clk->irq);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = 0;
+ gic_disable_ppi(clk->irq);
}
__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);