ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE

MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S
index dc4107dff7e81a31fd5b13880f5bf4711369b28c..e8936b6862c83cc543ea9722748f1c220dc09d6d 100644 (file)
--- a/arch/arm/mach-mx6/mx6sl_wfi.S
+++ b/arch/arm/mach-mx6/mx6sl_wfi.S
@@ -99,6 +99,31 @@
        str     r6, [r1, #0x320] /* DRAM_RESET */
        str     r7, [r1, #0x5c8] /* GPR_CTLDS */
 
+       /* Need to reset the FIFO to avoid MMDC lockup
+         * caused because of floating/changing the
+         * configuration of many DDR IO pads.
+         */
+       /* reset read FIFO, RST_RD_FIFO */
+       ldr     r7, =0x83c
+       ldr     r6, [r1, r7]
+       orr     r6, r6, #0x80000000
+       str     r6, [r1, r7]
+fifo_reset1_wait:
+       ldr     r6, [r1, r7]
+       and     r6, r6, #0x80000000
+       cmp     r6, #0
+       bne     fifo_reset1_wait
+
+       /* reset FIFO a second time */
+       ldr     r6, [r1, r7]
+       orr     r6, r6, #0x80000000
+       str     r6, [r1, r7]
+fifo_reset2_wait:
+       ldr     r6, [r1, r7]
+       and     r6, r6, #0x80000000
+       cmp     r6, #0
+       bne     fifo_reset2_wait
+
        .endm
 
        .macro  sl_ddr_io_set_lpm