]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
Merge branch 'spi-tegra' into spi-next
authorMark Brown <broonie@opensource.wolfsonmicro.com>
Tue, 30 Oct 2012 18:39:02 +0000 (18:39 +0000)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Tue, 30 Oct 2012 18:39:02 +0000 (18:39 +0000)
Documentation/devicetree/bindings/spi/omap-spi.txt
drivers/spi/spi-bcm63xx.c
drivers/spi/spi-omap2-mcspi.c
drivers/spi/spi-pl022.c
drivers/spi/spi-s3c64xx.c
include/linux/platform_data/spi-omap2-mcspi.h

index 81df374adbb97f53a8c7b8d56cb21e70e5d39cb3..2ef0a6b85653c4dc0ddbd18aac6c958c839f5004 100644 (file)
@@ -6,7 +6,9 @@ Required properties:
   - "ti,omap4-spi" for OMAP4+.
 - ti,spi-num-cs : Number of chipselect supported  by the instance.
 - ti,hwmods: Name of the hwmod associated to the McSPI
-
+- ti,pindir-d0-in-d1-out: Select the D0 pin as input and D1 as
+                         output. The default is D0 as output and
+                         D1 as input.
 
 Example:
 
index a9f4049c6769316c368a716b0b6707d7082abd25..6d97047d9242dbe495a2d209255f47fa98f24208 100644 (file)
@@ -36,7 +36,6 @@
 #include <bcm63xx_dev_spi.h>
 
 #define PFX            KBUILD_MODNAME
-#define DRV_VER                "0.1.2"
 
 struct bcm63xx_spi {
        struct completion       done;
@@ -170,13 +169,6 @@ static int bcm63xx_spi_setup(struct spi_device *spi)
                return -EINVAL;
        }
 
-       ret = bcm63xx_spi_check_transfer(spi, NULL);
-       if (ret < 0) {
-               dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
-                       spi->mode & ~MODEBITS);
-               return ret;
-       }
-
        dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
                __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 
@@ -441,8 +433,8 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
                goto out_clk_disable;
        }
 
-       dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
-                r->start, irq, bs->fifo_size, DRV_VER);
+       dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
+                r->start, irq, bs->fifo_size);
 
        return 0;
 
@@ -485,6 +477,8 @@ static int bcm63xx_spi_suspend(struct device *dev)
                        platform_get_drvdata(to_platform_device(dev));
        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 
+       spi_master_suspend(master);
+
        clk_disable(bs->clk);
 
        return 0;
@@ -498,6 +492,8 @@ static int bcm63xx_spi_resume(struct device *dev)
 
        clk_enable(bs->clk);
 
+       spi_master_resume(master);
+
        return 0;
 }
 
index 3542fdc664b11abcaecd579b8743b52346453354..51046332677cfe247a476ee4568392a7dbd4d175 100644 (file)
@@ -130,6 +130,7 @@ struct omap2_mcspi {
        struct omap2_mcspi_dma  *dma_channels;
        struct device           *dev;
        struct omap2_mcspi_regs ctx;
+       unsigned int            pin_dir:1;
 };
 
 struct omap2_mcspi_cs {
@@ -765,8 +766,15 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
        /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
         * REVISIT: this controller could support SPI_3WIRE mode.
         */
-       l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
-       l |= OMAP2_MCSPI_CHCONF_DPE0;
+       if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) {
+               l &= ~OMAP2_MCSPI_CHCONF_IS;
+               l &= ~OMAP2_MCSPI_CHCONF_DPE1;
+               l |= OMAP2_MCSPI_CHCONF_DPE0;
+       } else {
+               l |= OMAP2_MCSPI_CHCONF_IS;
+               l |= OMAP2_MCSPI_CHCONF_DPE1;
+               l &= ~OMAP2_MCSPI_CHCONF_DPE0;
+       }
 
        /* wordlength */
        l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
@@ -1167,6 +1175,11 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
        master->cleanup = omap2_mcspi_cleanup;
        master->dev.of_node = node;
 
+       dev_set_drvdata(&pdev->dev, master);
+
+       mcspi = spi_master_get_devdata(master);
+       mcspi->master = master;
+
        match = of_match_device(omap_mcspi_of_match, &pdev->dev);
        if (match) {
                u32 num_cs = 1; /* default number of chipselect */
@@ -1175,19 +1188,17 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
                of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
                master->num_chipselect = num_cs;
                master->bus_num = bus_num++;
+               if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL))
+                       mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
        } else {
                pdata = pdev->dev.platform_data;
                master->num_chipselect = pdata->num_cs;
                if (pdev->id != -1)
                        master->bus_num = pdev->id;
+               mcspi->pin_dir = pdata->pin_dir;
        }
        regs_offset = pdata->regs_offset;
 
-       dev_set_drvdata(&pdev->dev, master);
-
-       mcspi = spi_master_get_devdata(master);
-       mcspi->master = master;
-
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (r == NULL) {
                status = -ENODEV;
index a1db91a99b89a670cb7979c5fd758c90796aa2a9..1361868fced7d417c9a0a3768cc77bf0327920c6 100644 (file)
@@ -371,6 +371,7 @@ struct pl022 {
        /* Two optional pin states - default & sleep */
        struct pinctrl                  *pinctrl;
        struct pinctrl_state            *pins_default;
+       struct pinctrl_state            *pins_idle;
        struct pinctrl_state            *pins_sleep;
        struct spi_master               *master;
        struct pl022_ssp_controller     *master_info;
@@ -2116,6 +2117,11 @@ pl022_probe(struct amba_device *adev, const struct amba_id *id)
        } else
                dev_err(dev, "could not get default pinstate\n");
 
+       pl022->pins_idle = pinctrl_lookup_state(pl022->pinctrl,
+                                             PINCTRL_STATE_IDLE);
+       if (IS_ERR(pl022->pins_idle))
+               dev_dbg(dev, "could not get idle pinstate\n");
+
        pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl,
                                               PINCTRL_STATE_SLEEP);
        if (IS_ERR(pl022->pins_sleep))
@@ -2246,10 +2252,9 @@ pl022_probe(struct amba_device *adev, const struct amba_id *id)
                pm_runtime_set_autosuspend_delay(dev,
                        platform_info->autosuspend_delay);
                pm_runtime_use_autosuspend(dev);
-               pm_runtime_put_autosuspend(dev);
-       } else {
-               pm_runtime_put(dev);
        }
+       pm_runtime_put(dev);
+
        return 0;
 
  err_spi_register:
@@ -2303,35 +2308,47 @@ pl022_remove(struct amba_device *adev)
  * the runtime counterparts to handle external resources like
  * clocks, pins and regulators when going to sleep.
  */
-static void pl022_suspend_resources(struct pl022 *pl022)
+static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
 {
        int ret;
+       struct pinctrl_state *pins_state;
 
        clk_disable(pl022->clk);
 
+       pins_state = runtime ? pl022->pins_idle : pl022->pins_sleep;
        /* Optionally let pins go into sleep states */
-       if (!IS_ERR(pl022->pins_sleep)) {
-               ret = pinctrl_select_state(pl022->pinctrl,
-                                          pl022->pins_sleep);
+       if (!IS_ERR(pins_state)) {
+               ret = pinctrl_select_state(pl022->pinctrl, pins_state);
                if (ret)
-                       dev_err(&pl022->adev->dev,
-                               "could not set pins to sleep state\n");
+                       dev_err(&pl022->adev->dev, "could not set %s pins\n",
+                               runtime ? "idle" : "sleep");
        }
 }
 
-static void pl022_resume_resources(struct pl022 *pl022)
+static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
 {
        int ret;
 
        /* Optionaly enable pins to be muxed in and configured */
+       /* First go to the default state */
        if (!IS_ERR(pl022->pins_default)) {
-               ret = pinctrl_select_state(pl022->pinctrl,
-                                          pl022->pins_default);
+               ret = pinctrl_select_state(pl022->pinctrl, pl022->pins_default);
                if (ret)
                        dev_err(&pl022->adev->dev,
                                "could not set default pins\n");
        }
 
+       if (!runtime) {
+               /* Then let's idle the pins until the next transfer happens */
+               if (!IS_ERR(pl022->pins_idle)) {
+                       ret = pinctrl_select_state(pl022->pinctrl,
+                                       pl022->pins_idle);
+               if (ret)
+                       dev_err(&pl022->adev->dev,
+                               "could not set idle pins\n");
+               }
+       }
+
        clk_enable(pl022->clk);
 }
 #endif
@@ -2347,7 +2364,9 @@ static int pl022_suspend(struct device *dev)
                dev_warn(dev, "cannot suspend master\n");
                return ret;
        }
-       pl022_suspend_resources(pl022);
+
+       pm_runtime_get_sync(dev);
+       pl022_suspend_resources(pl022, false);
 
        dev_dbg(dev, "suspended\n");
        return 0;
@@ -2358,7 +2377,8 @@ static int pl022_resume(struct device *dev)
        struct pl022 *pl022 = dev_get_drvdata(dev);
        int ret;
 
-       pl022_resume_resources(pl022);
+       pl022_resume_resources(pl022, false);
+       pm_runtime_put(dev);
 
        /* Start the queue running */
        ret = spi_master_resume(pl022->master);
@@ -2376,7 +2396,7 @@ static int pl022_runtime_suspend(struct device *dev)
 {
        struct pl022 *pl022 = dev_get_drvdata(dev);
 
-       pl022_suspend_resources(pl022);
+       pl022_suspend_resources(pl022, true);
        return 0;
 }
 
@@ -2384,7 +2404,7 @@ static int pl022_runtime_resume(struct device *dev)
 {
        struct pl022 *pl022 = dev_get_drvdata(dev);
 
-       pl022_resume_resources(pl022);
+       pl022_resume_resources(pl022, true);
        return 0;
 }
 #endif
index 6e7a805d324d19d6bec848a8bca2f2a74a4303af..01b2f56a852e130038913857cb0ba5cf03f1ad70 100644 (file)
@@ -516,7 +516,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 
        /* Disable Clock */
        if (sdd->port_conf->clk_from_cmu) {
-               clk_disable(sdd->src_clk);
+               clk_disable_unprepare(sdd->src_clk);
        } else {
                val = readl(regs + S3C64XX_SPI_CLK_CFG);
                val &= ~S3C64XX_SPI_ENCLK_ENABLE;
@@ -564,7 +564,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
                /* There is half-multiplier before the SPI */
                clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
                /* Enable Clock */
-               clk_enable(sdd->src_clk);
+               clk_prepare_enable(sdd->src_clk);
        } else {
                /* Configure Clock */
                val = readl(regs + S3C64XX_SPI_CLK_CFG);
@@ -1302,7 +1302,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
                goto err3;
        }
 
-       if (clk_enable(sdd->clk)) {
+       if (clk_prepare_enable(sdd->clk)) {
                dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
                ret = -EBUSY;
                goto err4;
@@ -1317,7 +1317,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
                goto err5;
        }
 
-       if (clk_enable(sdd->src_clk)) {
+       if (clk_prepare_enable(sdd->src_clk)) {
                dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
                ret = -EBUSY;
                goto err6;
@@ -1361,11 +1361,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 err8:
        free_irq(irq, sdd);
 err7:
-       clk_disable(sdd->src_clk);
+       clk_disable_unprepare(sdd->src_clk);
 err6:
        clk_put(sdd->src_clk);
 err5:
-       clk_disable(sdd->clk);
+       clk_disable_unprepare(sdd->clk);
 err4:
        clk_put(sdd->clk);
 err3:
@@ -1393,10 +1393,10 @@ static int s3c64xx_spi_remove(struct platform_device *pdev)
 
        free_irq(platform_get_irq(pdev, 0), sdd);
 
-       clk_disable(sdd->src_clk);
+       clk_disable_unprepare(sdd->src_clk);
        clk_put(sdd->src_clk);
 
-       clk_disable(sdd->clk);
+       clk_disable_unprepare(sdd->clk);
        clk_put(sdd->clk);
 
        if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
@@ -1417,8 +1417,8 @@ static int s3c64xx_spi_suspend(struct device *dev)
        spi_master_suspend(master);
 
        /* Disable the clock */
-       clk_disable(sdd->src_clk);
-       clk_disable(sdd->clk);
+       clk_disable_unprepare(sdd->src_clk);
+       clk_disable_unprepare(sdd->clk);
 
        if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
                s3c64xx_spi_dt_gpio_free(sdd);
@@ -1440,8 +1440,8 @@ static int s3c64xx_spi_resume(struct device *dev)
                sci->cfg_gpio();
 
        /* Enable the clock */
-       clk_enable(sdd->src_clk);
-       clk_enable(sdd->clk);
+       clk_prepare_enable(sdd->src_clk);
+       clk_prepare_enable(sdd->clk);
 
        s3c64xx_spi_hwinit(sdd, sdd->port_id);
 
@@ -1457,8 +1457,8 @@ static int s3c64xx_spi_runtime_suspend(struct device *dev)
        struct spi_master *master = dev_get_drvdata(dev);
        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 
-       clk_disable(sdd->clk);
-       clk_disable(sdd->src_clk);
+       clk_disable_unprepare(sdd->clk);
+       clk_disable_unprepare(sdd->src_clk);
 
        return 0;
 }
@@ -1468,8 +1468,8 @@ static int s3c64xx_spi_runtime_resume(struct device *dev)
        struct spi_master *master = dev_get_drvdata(dev);
        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 
-       clk_enable(sdd->src_clk);
-       clk_enable(sdd->clk);
+       clk_prepare_enable(sdd->src_clk);
+       clk_prepare_enable(sdd->clk);
 
        return 0;
 }
index a357eb26bd258dfd6a969bf218da86d322f41ba1..ce70f7b5a8e1a0c77fb10b232c10fd405a5a48f1 100644 (file)
@@ -7,9 +7,13 @@
 
 #define OMAP4_MCSPI_REG_OFFSET 0x100
 
+#define MCSPI_PINDIR_D0_OUT_D1_IN      0
+#define MCSPI_PINDIR_D0_IN_D1_OUT      1
+
 struct omap2_mcspi_platform_config {
        unsigned short  num_cs;
        unsigned int regs_offset;
+       unsigned int pin_dir:1;
 };
 
 struct omap2_mcspi_dev_attr {