ASoC: tlv320aic32x4: Rearrange clock tree shutdown

Rearrange clock tree shutdown to disable them in the reversed order of
startup. First disable all dividers, then PLL followed by master clock.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>

diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c
index d69c61ffcda882d70b287912f3e87f50f8cb605d..c6bd7e75352d2c5298e28df490f1444dc027bc10 100644 (file)
--- a/sound/soc/codecs/tlv320aic32x4.c
+++ b/sound/soc/codecs/tlv320aic32x4.c
@@ -534,29 +534,29 @@ static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
        case SND_SOC_BIAS_PREPARE:
                break;
        case SND_SOC_BIAS_STANDBY:
-               /* Switch off PLL */
-               snd_soc_update_bits(codec, AIC32X4_PLLPR,
-                                   AIC32X4_PLLEN, 0);
-
-               /* Switch off NDAC Divider */
-               snd_soc_update_bits(codec, AIC32X4_NDAC,
-                                   AIC32X4_NDACEN, 0);
+               /* Switch off BCLK_N Divider */
+               snd_soc_update_bits(codec, AIC32X4_BCLKN,
+                                   AIC32X4_BCLKEN, 0);
 
-               /* Switch off MDAC Divider */
-               snd_soc_update_bits(codec, AIC32X4_MDAC,
-                                   AIC32X4_MDACEN, 0);
+               /* Switch off MADC Divider */
+               snd_soc_update_bits(codec, AIC32X4_MADC,
+                                   AIC32X4_MADCEN, 0);
 
                /* Switch off NADC Divider */
                snd_soc_update_bits(codec, AIC32X4_NADC,
                                    AIC32X4_NADCEN, 0);
 
-               /* Switch off MADC Divider */
-               snd_soc_update_bits(codec, AIC32X4_MADC,
-                                   AIC32X4_MADCEN, 0);
+               /* Switch off MDAC Divider */
+               snd_soc_update_bits(codec, AIC32X4_MDAC,
+                                   AIC32X4_MDACEN, 0);
 
-               /* Switch off BCLK_N Divider */
-               snd_soc_update_bits(codec, AIC32X4_BCLKN,
-                                   AIC32X4_BCLKEN, 0);
+               /* Switch off NDAC Divider */
+               snd_soc_update_bits(codec, AIC32X4_NDAC,
+                                   AIC32X4_NDACEN, 0);
+
+               /* Switch off PLL */
+               snd_soc_update_bits(codec, AIC32X4_PLLPR,
+                                   AIC32X4_PLLEN, 0);
 
                /* Switch off master clock */
                clk_disable_unprepare(aic32x4->mclk);