void *mx6_wait_in_iram_base;
-void (*mx6_wait_in_iram)(void *ccm_base);
+void (*mx6_wait_in_iram)();
extern void mx6_wait(void);
*/
ENTRY(mx6_wait)
- stmfd sp!, {r3,r4,r5,r6,r7} @ Save registers
+ dsb
wfi
- /*Wait for 170ns due to L2 cache errata (TKT065875) */
- /*System is more stable only if the wait is closer to ~380ns */
- /* Each IO read takes about 76ns. */
-
- ldr r6, [r0]
- ldr r6, [r0, #4]
- ldr r6, [r0, #8]
- ldr r6, [r0, #0xc]
- ldr r6, [r0, #0x10]
- ldr r6, [r0, #0x14]
- ldr r6, [r0, #0x18]
- ldr r6, [r0, #0x1c]
- ldr r6, [r0, #0x20]
- ldr r6, [r0, #0x24]
-
- /* Restore registers */
- ldmfd sp!, {r3,r4,r5,r6,r7}
- mov pc, lr
+ isb
+ isb
+
+ mov pc, lr
.type mx6_do_wait, #object
ENTRY(mx6_do_wait)
/* static DEFINE_SPINLOCK(wfi_lock); */
extern unsigned int gpc_wake_irq[4];
+extern int mx6q_revision(void);
/* static unsigned int cpu_idle_mask; */
static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
-extern void (*mx6_wait_in_iram)(void *ccm_base);
+extern void (*mx6_wait_in_iram)();
extern void mx6_wait(void);
extern void *mx6_wait_in_iram_base;
extern bool enable_wait_mode;
__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
}
-void arch_idle(void)
+ void arch_idle(void)
{
if (enable_wait_mode) {
if ((num_online_cpus() == num_present_cpus())
&& mx6_wait_in_iram != NULL) {
mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
- mx6_wait_in_iram(MXC_CCM_BASE);
+ if (smp_processor_id() == 0 &&
+ (mx6q_revision() <= IMX_CHIP_REVISION_1_0))
+ mx6_wait_in_iram();
+ else
+ cpu_do_idle();
}
} else
cpu_do_idle();