ARM: hw_breakpoint: only clear OS lock when implemented on v7

The OS save and restore register are optional in debug architecture v7,
so check the status register before attempting to clear the OS lock.

Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 281bf3301241fba2a1ce1baafeaf3020b7cd57ff..ec16adac9af798be173bd7aca59658529ec3538f 100644 (file)
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -929,6 +929,13 @@ static void reset_ctrl_regs(void *unused)
                asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
                if ((dbg_power & 0x1) == 0)
                        err = -EPERM;
+
+               /*
+                * Check whether we implement OS save and restore.
+                */
+               asm volatile("mrc p14, 0, %0, c1, c1, 4" : "=r" (dbg_power));
+               if ((dbg_power & 0x9) == 0)
+                       goto clear_vcr;
                break;
        case ARM_DEBUG_ARCH_V7_1:
                /*
@@ -947,7 +954,7 @@ static void reset_ctrl_regs(void *unused)
        }
 
        /*
-        * Unconditionally clear the lock by writing a value
+        * Unconditionally clear the OS lock by writing a value
         * other than 0xC5ACCE55 to the access register.
         */
        asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
@@ -957,6 +964,7 @@ static void reset_ctrl_regs(void *unused)
         * Clear any configured vector-catch events before
         * enabling monitor mode.
         */
+clear_vcr:
        asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
        isb();