ENGR00235086 I2C: update i2c clock divider for each transaction

Currently on Arik/Rigel, the I2C clk is from IPG_PERCLK which is
sourced from IPG_CLK. Under normal operation, ipg_perclk is at 22MHz
so that we can get 400KHz i2c speed. In low bus freq mode, IPG_CLK is
at 12MHz and IPG_PERCLK is down to 4MHz.
So the I2C driver must update the divider register for each transaction.

Signed-off-by: Fugang Duan  <B38611@freescale.com>

diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index df9fca34915da267cc60fb7cecff70460c76f6a9..3aedafd08f16e2437b9dfe5c5ebcc312489485c3 100644 (file)
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -181,13 +181,64 @@ static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
        return 0;
 }
 
+static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
+                                                       unsigned int rate)
+{
+       unsigned int i2c_clk_rate;
+       unsigned int div;
+       int i;
+
+       /* Divider value calculation */
+       i2c_clk_rate = clk_get_rate(i2c_imx->clk);
+       div = (i2c_clk_rate + rate - 1) / rate;
+       if (div < i2c_clk_div[0][0])
+               i = 0;
+       else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
+               i = ARRAY_SIZE(i2c_clk_div) - 1;
+       else
+               for (i = 0; i2c_clk_div[i][0] < div; i++)
+                       ;
+
+       /* Store divider value */
+       i2c_imx->ifdr = i2c_clk_div[i][1];
+
+       /*
+        * There dummy delay is calculated.
+        * It should be about one I2C clock period long.
+        * This delay is used in I2C bus disable function
+        * to fix chip hardware bug.
+        */
+       i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
+               + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
+
+       /* dev_dbg() can't be used, because adapter is not yet registered */
+#ifdef CONFIG_I2C_DEBUG_BUS
+       printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
+               __func__, i2c_clk_rate, div);
+       printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
+               __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
+#endif
+}
+
 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
 {
        unsigned int temp = 0;
+       struct imxi2c_platform_data *pdata;
        int result;
 
        dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 
+       /* Currently on Arik/Rigel, the I2C clk is from IPG_PERCLK which is
+        * sourced from IPG_CLK. In low bus freq mode, IPG_CLK is at 12MHz
+        * and IPG_PERCLK is down to 4MHz.
+        * Update I2C divider before set i2c clock.
+        */
+       pdata = i2c_imx->adapter.dev.parent->platform_data;
+       if (pdata && pdata->bitrate)
+               i2c_imx_set_clk(i2c_imx, pdata->bitrate);
+       else
+               i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
+
        clk_enable(i2c_imx->clk);
        writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
        /* Enable I2C controller */
@@ -240,44 +291,6 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
        clk_disable(i2c_imx->clk);
 }
 
-static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
-                                                       unsigned int rate)
-{
-       unsigned int i2c_clk_rate;
-       unsigned int div;
-       int i;
-
-       /* Divider value calculation */
-       i2c_clk_rate = clk_get_rate(i2c_imx->clk);
-       div = (i2c_clk_rate + rate - 1) / rate;
-       if (div < i2c_clk_div[0][0])
-               i = 0;
-       else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
-               i = ARRAY_SIZE(i2c_clk_div) - 1;
-       else
-               for (i = 0; i2c_clk_div[i][0] < div; i++);
-
-       /* Store divider value */
-       i2c_imx->ifdr = i2c_clk_div[i][1];
-
-       /*
-        * There dummy delay is calculated.
-        * It should be about one I2C clock period long.
-        * This delay is used in I2C bus disable function
-        * to fix chip hardware bug.
-        */
-       i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
-               + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
-
-       /* dev_dbg() can't be used, because adapter is not yet registered */
-#ifdef CONFIG_I2C_DEBUG_BUS
-       printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
-               __func__, i2c_clk_rate, div);
-       printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
-               __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
-#endif
-}
-
 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 {
        struct imx_i2c_struct *i2c_imx = dev_id;