ARM i.MX6q: set the LDB serial clock parent to the video PLL

On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2b230f83170bd728cec09da81e00b609033de052..43dbcd618be3f99b9e4c808bf5deaf7840927031 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -547,6 +547,11 @@ int __init mx6q_clocks_init(void)
        clk_register_clkdev(clk[cko1], "cko1", NULL);
        clk_register_clkdev(clk[arm], NULL, "cpu0");
 
+       if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
+               clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+               clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+       }
+
        /*
         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
         * We can not get the 100MHz from the pll2_pfd0_352m.