ENGR00229437 [MX6SL] Fix AHB clock not changed to 3MHz in IDLE mode

1. Fix AHB clock not changed to 3MHz in IDLE mode
2. Fix system hangs in IDLE mode due to changes made for LOCKDEP

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>

diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index 6e35418b92bd2a8687a4b9c13b7472cd22bfa3ad..6422052ed0b304055f6a1b51c3c94934ba5bd8d5 100644 (file)
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -168,8 +168,11 @@ void reduce_bus_freq(void)
                if (lp_audio_freq) {
                        /* PLL2 is on in this mode, as DDR is at 50MHz. */
                        /* Now change DDR freq while running from IRAM. */
+
+                       spin_lock_irqsave(&freq_lock, flags);
                        mx6sl_ddr_freq_change_iram(DDR_AUDIO_CLK,
                                                        low_bus_freq_mode);
+                       spin_unlock_irqrestore(&freq_lock, flags);
 
                        if (low_bus_freq_mode) {
                                /* Swtich ARM to run off PLL2_PFD2_400MHz
@@ -211,9 +214,11 @@ void reduce_bus_freq(void)
                                ;
                        clk_set_parent(pll1_sw_clk, pll1);
 
+                       spin_lock_irqsave(&freq_lock, flags);
                        /* Now change DDR freq while running from IRAM. */
                        mx6sl_ddr_freq_change_iram(LPAPM_CLK,
                                        low_bus_freq_mode);
+                       spin_unlock_irqrestore(&freq_lock, flags);
 
                        low_bus_freq_mode = 1;
                        audio_bus_freq_mode = 0;
@@ -319,8 +324,10 @@ int set_high_bus_freq(int high_bus_freq)
                u32 reg;
                unsigned long flags;
 
+               spin_lock_irqsave(&freq_lock, flags);
                /* Change DDR freq in IRAM. */
                mx6sl_ddr_freq_change_iram(ddr_normal_rate, low_bus_freq_mode);
+               spin_unlock_irqrestore(&freq_lock, flags);
 
                /* Set periph_clk to be sourced from pll2_pfd2_400M */
                /* First need to set the divider before changing the */

diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index b80a6b2599657dc0492b8f187010d0b6cd75d2c7..2308e332dc44363f68696e419821c09840a6d183 100644 (file)
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -371,7 +371,6 @@ static int mx6_suspend_enter(suspend_state_t state)
        } else {
                        cpu_do_idle();
        }
-       clk_set_parent(axi_clk, axi_org_parent);
 
        return 0;
 }

diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index fdbf58cec947918b4ffbcd9fcf5f4215875c90aa..0e4b534de6eb677b19ab16cd836ca1a911991f5b 100644 (file)
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -272,8 +272,8 @@ void arch_idle_single_core(void)
                ca9_do_idle();
        } else {
                if (low_bus_freq_mode || audio_bus_freq_mode) {
-                       u32 ddr_usecount;
-                       if ((mmdc_ch0_axi != NULL) && ddr_usecount)
+                       int ddr_usecount = 0;
+                       if ((mmdc_ch0_axi != NULL))
                                ddr_usecount = clk_get_usecount(mmdc_ch0_axi);
 
                        if (cpu_is_mx6sl() && low_bus_freq_mode