ARM: dts: r8a7794: Fix W=1 dtc warnings

Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property

Move the cache-controller node under the cpus node, and make its unit
name and reg property match the MPIDR value.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index ad1df8317575011dfc8d56563a8724135c72b763..685f986cf962752f364d1beb8751d09f596ec726 100644 (file)
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -55,13 +55,14 @@
                        power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
                        next-level-cache = <&L2_CA7>;
                };
-       };
 
-       L2_CA7: cache-controller@1 {
-               compatible = "cache";
-               power-domains = <&sysc R8A7794_PD_CA7_SCU>;
-               cache-unified;
-               cache-level = <2>;
+               L2_CA7: cache-controller@0 {
+                       compatible = "cache";
+                       reg = <0>;
+                       power-domains = <&sysc R8A7794_PD_CA7_SCU>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
        };
 
        gic: interrupt-controller@f1001000 {