extern void (*mach_beep) (unsigned int, unsigned int);
/* Hardware clock functions */
-extern void hw_timer_init(void);
+extern void hw_timer_init(irq_handler_t handler);
extern unsigned long hw_timer_offset(void);
-extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
extern void config_BSP(char *command, int len);
char __initdata command_line[COMMAND_LINE_SIZE];
/* machine dependent timer functions */
+void (*mach_sched_init)(irq_handler_t handler) __initdata = NULL;
int (*mach_set_clock_mmss)(unsigned long);
int (*mach_hwclk) (int, struct rtc_time*);
return -1;
}
-#ifndef CONFIG_GENERIC_CLOCKEVENTS
/*
* timer_interrupt() needs to keep up the real-time clock,
* as well as call the "xtime_update()" routine every clocktick
*/
-irqreturn_t arch_timer_interrupt(int irq, void *dummy)
+static irqreturn_t timer_interrupt(int irq, void *dummy)
{
if (current->pid)
return(IRQ_HANDLED);
}
-#endif
void read_persistent_clock(struct timespec *ts)
{
return set_rtc_mmss(now.tv_sec);
}
-void time_init(void)
+void __init time_init(void)
{
- hw_timer_init();
+ mach_sched_init(timer_interrupt);
}
#endif /* CONFIG_NETtel */
mach_reset = m5206_cpu_reset;
+ mach_sched_init = hw_timer_init;
m5206_timers_init();
m5206_uarts_init();
void __init config_BSP(char *commandp, int size)
{
mach_reset = m520x_cpu_reset;
+ mach_sched_init = hw_timer_init;
m520x_uarts_init();
m520x_fec_init();
#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
void __init config_BSP(char *commandp, int size)
{
mach_reset = m523x_cpu_reset;
+ mach_sched_init = hw_timer_init;
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_reset = m5249_cpu_reset;
+ mach_sched_init = hw_timer_init;
m5249_timers_init();
m5249_uarts_init();
#ifdef CONFIG_M5249C3
#endif
mach_reset = m5272_cpu_reset;
+ mach_sched_init = hw_timer_init;
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_reset = m527x_cpu_reset;
+ mach_sched_init = hw_timer_init;
m527x_uarts_init();
m527x_fec_init();
#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
static int __init init_BSP(void)
{
mach_reset = m528x_cpu_reset;
+ mach_sched_init = hw_timer_init;
m528x_uarts_init();
m528x_fec_init();
#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
#endif
mach_reset = m5307_cpu_reset;
+ mach_sched_init = hw_timer_init;
m5307_timers_init();
m5307_uarts_init();
}
#endif
+ mach_sched_init = hw_timer_init;
+
#ifdef CONFIG_BDM_DISABLE
/*
* Disable the BDM clocking. This also turns off most of the rest of
void __init config_BSP(char *commandp, int size)
{
mach_reset = m5407_cpu_reset;
+ mach_sched_init = hw_timer_init;
m5407_timers_init();
m5407_uarts_init();
mmu_context_init();
#endif
mach_reset = mcf54xx_reset;
+ mach_sched_init = hw_timer_init;
m54xx_uarts_init();
}
/***************************************************************************/
-void hw_timer_init(void)
+void hw_timer_init(irq_handler_t handler)
{
cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
static u32 mcfslt_cycles_per_jiffy;
static u32 mcfslt_cnt;
+static irq_handler_t timer_interrupt;
+
static irqreturn_t mcfslt_tick(int irq, void *dummy)
{
/* Reset Slice Timer 0 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
mcfslt_cnt += mcfslt_cycles_per_jiffy;
- return arch_timer_interrupt(irq, dummy);
+ return timer_interrupt(irq, dummy);
}
static struct irqaction mcfslt_timer_irq = {
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-void hw_timer_init(void)
+void hw_timer_init(irq_handler_t handler)
{
mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
/*
/* initialize mcfslt_cnt knowing that slice timers count down */
mcfslt_cnt = mcfslt_cycles_per_jiffy;
+ timer_interrupt = handler;
setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
static u32 mcftmr_cycles_per_jiffy;
static u32 mcftmr_cnt;
+static irq_handler_t timer_interrupt;
+
/***************************************************************************/
static irqreturn_t mcftmr_tick(int irq, void *dummy)
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
mcftmr_cnt += mcftmr_cycles_per_jiffy;
- return arch_timer_interrupt(irq, dummy);
+ return timer_interrupt(irq, dummy);
}
/***************************************************************************/
/***************************************************************************/
-void hw_timer_init(void)
+void hw_timer_init(irq_handler_t handler)
{
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
mcftmr_cycles_per_jiffy = FREQ / HZ;
clocksource_register_hz(&mcftmr_clk, FREQ);
+ timer_interrupt = handler;
setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
#ifdef CONFIG_HIGHPROFILE