ENGR00317981: ARM: dts: imx6qdl: add LDB and LCD for imx6qdl-sabresd

It's a device tree source porting from imx_3.10.y regarding to LDB and
LCD support on imx6qdl-sabresd board.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 1e45f2f9d0b6bce33210988fb17ff816a173c8b7..c206074752434d8f7d612fa2df38eff1bb1d8a1f 100644 (file)
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,3 +15,21 @@
        model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
        compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
 };
+
+&ldb {
+       lvds-channel@0 {
+               crtc = "ipu1-di0";
+       };
+
+       lvds-channel@1 {
+               crtc = "ipu1-di1";
+       };
+};
+
+&mxcfb1 {
+       status = "okay";
+};
+
+&mxcfb2 {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 9cbdfe7a0931ff4fa8c09db3c9ea0fa3bb397609..f4ae2c73c6ebb3e3b738bde94f13bf3c9cfe4b6c 100644 (file)
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -20,6 +20,32 @@
        compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
 };
 
+&ldb {
+       lvds-channel@0 {
+               crtc = "ipu2-di0";
+       };
+
+       lvds-channel@1 {
+               crtc = "ipu2-di1";
+       };
+};
+
+&mxcfb1 {
+       status = "okay";
+};
+
+&mxcfb2 {
+       status = "okay";
+};
+
+&mxcfb3 {
+       status = "okay";
+};
+
+&mxcfb4 {
+       status = "okay";
+};
+
 &sata {
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 6d3c8242fd872d0bba7146541af38738912475e5..5472a4cc790dd9e232957bbd6b51a77f1b1d94e7 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -13,6 +13,10 @@
 #include "imx6qdl.dtsi"
 
 / {
+       aliases {
+               ipu1 = &ipu2;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -148,34 +152,37 @@
                };
 
                ipu2: ipu@02800000 {
-                       #crtc-cells = <1>;
                        compatible = "fsl,imx6q-ipu";
                        reg = <0x02800000 0x400000>;
                        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
                                     <0 7 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clks IMX6QDL_CLK_IPU2>,
-                                <&clks IMX6QDL_CLK_IPU2_DI0>,
-                                <&clks IMX6QDL_CLK_IPU2_DI1>;
-                       clock-names = "bus", "di0", "di1";
+                                <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
+                                <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+                                <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
+                       clock-names = "bus",
+                                     "di0", "di1",
+                                     "di0_sel", "di1_sel",
+                                     "ldb_di0", "ldb_di1";
                        resets = <&src 4>;
+                       bypass_reset = <0>;
                };
        };
 };
 
 &ldb {
-       clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+       compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+
+       clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
                 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
                 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
-                <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
-       clock-names = "di0_pll", "di1_pll",
-                     "di0_sel", "di1_sel", "di2_sel", "di3_sel",
-                     "di0", "di1";
-
-       lvds-channel@0 {
-               crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-       };
-
-       lvds-channel@1 {
-               crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-       };
+                <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
+                <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
+                <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
+       clock-names = "ldb_di0", "ldb_di1",
+                     "di0_sel", "di1_sel",
+                     "di2_sel", "di3_sel",
+                     "ldb_di0_div_3_5", "ldb_di1_div_3_5",
+                     "ldb_di0_div_7", "ldb_di1_div_7",
+                     "ldb_di0_div_sel", "ldb_di1_div_sel";
 };

diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index bdc00f974f07cd323fbeb9ab55f48cf8b093ada4..4abb351143826e37952595513ec08689adf497c3 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -13,6 +13,13 @@
 #include <dt-bindings/input/input.h>
 
 / {
+       aliases {
+               mxcfb0 = &mxcfb1;
+               mxcfb1 = &mxcfb2;
+               mxcfb2 = &mxcfb3;
+               mxcfb3 = &mxcfb4;
+       };
+
        memory {
                reg = <0x10000000 0x40000000>;
        };
@@ -97,6 +104,58 @@
                mux-ext-port = <3>;
        };
 
+       mxcfb1: fb@0 {
+               compatible = "fsl,mxc_sdc_fb";
+               disp_dev = "ldb";
+               interface_pix_fmt = "RGB666";
+               default_bpp = <16>;
+               int_clk = <0>;
+               late_init = <0>;
+               status = "disabled";
+       };
+
+       mxcfb2: fb@1 {
+               compatible = "fsl,mxc_sdc_fb";
+               disp_dev = "hdmi";
+               interface_pix_fmt = "RGB24";
+               mode_str ="1920x1080M@60";
+               default_bpp = <24>;
+               int_clk = <0>;
+               late_init = <0>;
+               status = "disabled";
+       };
+
+       mxcfb3: fb@2 {
+               compatible = "fsl,mxc_sdc_fb";
+               disp_dev = "lcd";
+               interface_pix_fmt = "RGB565";
+               mode_str ="CLAA-WVGA";
+               default_bpp = <16>;
+               int_clk = <0>;
+               late_init = <0>;
+               status = "disabled";
+       };
+
+       mxcfb4: fb@3 {
+               compatible = "fsl,mxc_sdc_fb";
+               disp_dev = "ldb";
+               interface_pix_fmt = "RGB666";
+               default_bpp = <16>;
+               int_clk = <0>;
+               late_init = <0>;
+               status = "disabled";
+       };
+
+       lcd@0 {
+               compatible = "fsl,lcd";
+               ipu_id = <0>;
+               disp_id = <0>;
+               default_ifmt = "RGB565";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ipu1>;
+               status = "okay";
+       };
+
        backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm1 0 5000000>;
@@ -259,6 +318,40 @@
                        >;
                };
 
+               pinctrl_ipu1: ipu1grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+                               MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+                               MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+                               MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+                               MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
+                               MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+                               MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+                               MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+                               MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+                               MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+                               MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+                               MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+                               MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+                               MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+                               MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+                               MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+                               MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+                               MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+                               MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+                               MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+                               MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+                               MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+                               MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
+                               MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
+                               MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
+                               MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
+                               MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
+                               MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
+                               MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
+                       >;
+               };
+
                pinctrl_pwm1: pwm1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
@@ -313,7 +406,7 @@
 &ldb {
        status = "okay";
 
-       lvds-channel@1 {
+       lvds-channel@0 {
                fsl,data-mapping = "spwg";
                fsl,data-width = <18>;
                status = "okay";
@@ -333,6 +426,28 @@
                        };
                };
        };
+
+       lvds-channel@1 {
+               fsl,data-mapping = "spwg";
+               fsl,data-width = <18>;
+               primary;
+               status = "okay";
+
+               display-timings {
+                       native-mode = <&timing1>;
+                       timing1: hsd100pxn1 {
+                               clock-frequency = <65000000>;
+                               hactive = <1024>;
+                               vactive = <768>;
+                               hback-porch = <220>;
+                               hfront-porch = <40>;
+                               vback-porch = <21>;
+                               vfront-porch = <7>;
+                               hsync-len = <60>;
+                               vsync-len = <10>;
+                       };
+               };
+       };
 };
 
 &pwm1 {

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index cf32e1cd0e88dc94ba5c10dedfc45c43ed730424..9b93740862fcdbb65038b3f3704fc3b8c7958d06 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -26,6 +26,7 @@
                i2c0 = &i2c1;
                i2c1 = &i2c2;
                i2c2 = &i2c3;
+               ipu0 = &ipu1;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -657,7 +658,6 @@
                        ldb: ldb@020e0008 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
                                gpr = <&gpr>;
                                status = "disabled";
 
@@ -958,16 +958,20 @@
                };
 
                ipu1: ipu@02400000 {
-                       #crtc-cells = <1>;
                        compatible = "fsl,imx6q-ipu";
                        reg = <0x02400000 0x400000>;
                        interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
                                     <0 5 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clks IMX6QDL_CLK_IPU1>,
-                                <&clks IMX6QDL_CLK_IPU1_DI0>,
-                                <&clks IMX6QDL_CLK_IPU1_DI1>;
-                       clock-names = "bus", "di0", "di1";
+                                <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
+                                <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+                                <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI0>;
+                       clock-names = "bus",
+                                     "di0", "di1",
+                                     "di0_sel", "di1_sel",
+                                     "ldb_di0", "ldb_di1";
                        resets = <&src 2>;
+                       bypass_reset = <0>;
                };
        };
 };