bus_clk = clk_get(NULL, "bus");
if (IS_ERR(bus_clk))
- panic("unable to get bus clk\n");
+ panic("unable to get bus clk");
uart_port.type = PORT_AR7;
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
if (!io_base)
- panic("Can't remap IO base!\n");
+ panic("Can't remap IO base!");
set_io_port_base(io_base);
prom_meminit();
break;
default:
- panic("ath79: unknown SoC, id:0x%08x\n", id);
+ panic("ath79: unknown SoC, id:0x%08x", id);
}
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,
bcm47xx_get_invariants);
if (err)
- panic("Failed to initialize SSB bus (err %d)\n", err);
+ panic("Failed to initialize SSB bus (err %d)", err);
mcore = &bcm47xx_bus.ssb.mipscore;
if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
err = bcma_host_soc_register(&bcm47xx_bus.bcma);
if (err)
- panic("Failed to initialize BCMA bus (err %d)\n", err);
+ panic("Failed to initialize BCMA bus (err %d)", err);
}
#endif
: "=r" (insn) : : "$31", "memory");
if ((insn >> 26) != 0x33)
- panic("No PREF instruction at Core-14449 probe point.\n");
+ panic("No PREF instruction at Core-14449 probe point.");
if (((insn >> 16) & 0x1f) != 28)
panic("Core-14449 WAR not in place (%04x).\n"
- "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
+ "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
}
#ifdef CONFIG_CAVIUM_DECODE_RSL
cvmx_interrupt_rsl_enable();
/* Add an interrupt handler for general failures. */
if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
"RML/RSL", octeon_rlm_interrupt)) {
- panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
+ panic("Unable to request_irq(OCTEON_IRQ_RML)");
}
#endif
}
if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
mailbox_interrupt)) {
- panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
+ panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
}
}
board_gpio_setup();
if (qi_lb60_init_platform_devices())
- panic("Failed to initialize platform devices\n");
+ panic("Failed to initialize platform devices");
return 0;
}
pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
if (pipi == NULL)
- panic("kmalloc of IPI message buffers failed\n");
+ panic("kmalloc of IPI message buffers failed");
else
printk("IPI buffer pool of %d buffers\n", nipi);
for (i = 0; i < nipi; i++) {
if (pipi == NULL) {
bust_spinlocks(1);
mips_mt_regdump(dvpe());
- panic("IPI Msg. Buffers Depleted\n");
+ panic("IPI Msg. Buffers Depleted");
}
pipi->type = type;
pipi->arg = (void *)action;
panic("Fatal exception in interrupt");
if (panic_on_oops) {
- printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
+ printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
ssleep(5);
panic("Fatal exception");
}
asmlinkage void do_dsp(struct pt_regs *regs)
{
if (cpu_has_dsp)
- panic("Unexpected DSP exception\n");
+ panic("Unexpected DSP exception");
force_sig(SIGILL, current);
}
struct clk *clk;
if (insert_resource(&iomem_resource, <q_cgu_resource) < 0)
- panic("Failed to insert cgu memory\n");
+ panic("Failed to insert cgu memory");
if (request_mem_region(ltq_cgu_resource.start,
resource_size(<q_cgu_resource), "cgu") < 0)
- panic("Failed to request cgu memory\n");
+ panic("Failed to request cgu memory");
ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
resource_size(<q_cgu_resource));
int i;
if (insert_resource(&iomem_resource, <q_icu_resource) < 0)
- panic("Failed to insert icu memory\n");
+ panic("Failed to insert icu memory");
if (request_mem_region(ltq_icu_resource.start,
resource_size(<q_icu_resource), "icu") < 0)
- panic("Failed to request icu memory\n");
+ panic("Failed to request icu memory");
ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
resource_size(<q_icu_resource));
if (!ltq_icu_membase)
- panic("Failed to remap icu memory\n");
+ panic("Failed to remap icu memory");
if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
- panic("Failed to insert eiu memory\n");
+ panic("Failed to insert eiu memory");
if (request_mem_region(ltq_eiu_resource.start,
resource_size(<q_eiu_resource), "eiu") < 0)
- panic("Failed to request eiu memory\n");
+ panic("Failed to request eiu memory");
ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
resource_size(<q_eiu_resource));
if (!ltq_eiu_membase)
- panic("Failed to remap eiu memory\n");
+ panic("Failed to remap eiu memory");
/* make sure all irqs are turned off by default */
for (i = 0; i < 5; i++)
/* insert and request the memory region */
if (insert_resource(&iomem_resource, <q_dma_resource) < 0)
- panic("Failed to insert dma memory\n");
+ panic("Failed to insert dma memory");
if (request_mem_region(ltq_dma_resource.start,
resource_size(<q_dma_resource), "dma") < 0)
- panic("Failed to request dma memory\n");
+ panic("Failed to request dma memory");
/* remap dma register range */
ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
resource_size(<q_dma_resource));
if (!ltq_dma_membase)
- panic("Failed to remap dma memory\n");
+ panic("Failed to remap dma memory");
/* power up and reset the dma engine */
ltq_pmu_enable(PMU_DMA);
{
/* insert and request the memory region */
if (insert_resource(&iomem_resource, <q_ebu_resource) < 0)
- panic("Failed to insert ebu memory\n");
+ panic("Failed to insert ebu memory");
if (request_mem_region(ltq_ebu_resource.start,
resource_size(<q_ebu_resource), "ebu") < 0)
- panic("Failed to request ebu memory\n");
+ panic("Failed to request ebu memory");
/* remap ebu register range */
ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
resource_size(<q_ebu_resource));
if (!ltq_ebu_membase)
- panic("Failed to remap ebu memory\n");
+ panic("Failed to remap ebu memory");
/* make sure to unprotect the memory region where flash is located */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
if (!err)
- panic("activating PMU module failed!\n");
+ panic("activating PMU module failed!");
}
EXPORT_SYMBOL(ltq_pmu_enable);
int __init ltq_pmu_init(void)
{
if (insert_resource(&iomem_resource, <q_pmu_resource) < 0)
- panic("Failed to insert pmu memory\n");
+ panic("Failed to insert pmu memory");
if (request_mem_region(ltq_pmu_resource.start,
resource_size(<q_pmu_resource), "pmu") < 0)
- panic("Failed to request pmu memory\n");
+ panic("Failed to request pmu memory");
ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
resource_size(<q_pmu_resource));
if (!ltq_pmu_membase)
- panic("Failed to remap pmu memory\n");
+ panic("Failed to remap pmu memory");
return 0;
}
{
/* insert and request the memory region */
if (insert_resource(&iomem_resource, <q_rcu_resource) < 0)
- panic("Failed to insert rcu memory\n");
+ panic("Failed to insert rcu memory");
if (request_mem_region(ltq_rcu_resource.start,
resource_size(<q_rcu_resource), "rcu") < 0)
- panic("Failed to request rcu memory\n");
+ panic("Failed to request rcu memory");
/* remap rcu register range */
ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
resource_size(<q_rcu_resource));
if (!ltq_rcu_membase)
- panic("Failed to remap rcu memory\n");
+ panic("Failed to remap rcu memory");
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
break;
default:
- panic("Unsupported Cavium Networks CPU type\n");
+ panic("Unsupported Cavium Networks CPU type");
break;
}
msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
break;
default:
- panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
+ panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
}
msg.data = irq - OCTEON_IRQ_MSI_BIT0;
default:
/* we don't recognize the machine */
mips_machtype = MACH_UNKNOWN;
- panic("***Bogosity factor five***, exiting\n");
+ panic("***Bogosity factor five***, exiting");
break;
}
level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
if (level >= LEVELS_PER_SLICE)
- panic("Cpu %d flooded with devices\n", cpu);
+ panic("Cpu %d flooded with devices", cpu);
__set_bit(level, hub->irq_alloc_mask);
si->level_to_irq[level] = irq;
}
}
- panic("Could not identify cpu/level for irq %d\n", irq);
+ panic("Could not identify cpu/level for irq %d", irq);
}
/*