Merge branch 'topic/idma' into for-linus

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 6a388a7c6429607dce6ad4d7df4e281086af8687..e6cd1a32025a916cec7d219d4693c7c71e4c09a9 100644 (file)
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -229,7 +229,7 @@ config IMX_SDMA
          Support the i.MX SDMA engine. This engine is integrated into
          Freescale i.MX25/31/35/51/53/6 chips.
 
-config IDMA64
+config INTEL_IDMA64
        tristate "Intel integrated DMA 64-bit support"
        select DMA_ENGINE
        select DMA_VIRTUAL_CHANNELS

diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7711a718072622c024af8c22ef7161ce654b0003..ef9c099bd2b6c4e2d09c1a14dfb6563118745c17 100644 (file)
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
-obj-$(CONFIG_IDMA64) += idma64.o
+obj-$(CONFIG_INTEL_IDMA64) += idma64.o
 obj-$(CONFIG_INTEL_IOATDMA) += ioat/
 obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
 obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o

diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
index 18c14e1f1414e650969ff3c9e34431072b3abd83..39e6ab1d01fb429af8322e6bd50f7341360cf940 100644 (file)
--- a/drivers/dma/idma64.c
+++ b/drivers/dma/idma64.c
@@ -65,9 +65,6 @@ static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
        u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
        u32 cfglo = 0;
 
-       /* Enforce FIFO drain when channel is suspended */
-       cfglo |= IDMA64C_CFGL_CH_DRAIN;
-
        /* Set default burst alignment */
        cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
 
@@ -257,15 +254,15 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
                dar = config->dst_addr;
                ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
                         IDMA64C_CTLL_FC_M2P;
-               src_width = min_t(u32, 2, __fls(sar | hw->len));
-               dst_width = __fls(config->dst_addr_width);
+               src_width = __ffs(sar | hw->len | 4);
+               dst_width = __ffs(config->dst_addr_width);
        } else {        /* DMA_DEV_TO_MEM */
                sar = config->src_addr;
                dar = hw->phys;
                ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
                         IDMA64C_CTLL_FC_P2M;
-               src_width = __fls(config->src_addr_width);
-               dst_width = min_t(u32, 2, __fls(dar | hw->len));
+               src_width = __ffs(config->src_addr_width);
+               dst_width = __ffs(dar | hw->len | 4);
        }
 
        lli->sar = sar;
@@ -428,12 +425,17 @@ static int idma64_slave_config(struct dma_chan *chan,
        return 0;
 }
 
-static void idma64_chan_deactivate(struct idma64_chan *idma64c)
+static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
 {
        unsigned short count = 100;
        u32 cfglo;
 
        cfglo = channel_readl(idma64c, CFG_LO);
+       if (drain)
+               cfglo |= IDMA64C_CFGL_CH_DRAIN;
+       else
+               cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
+
        channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
        do {
                udelay(1);
@@ -456,7 +458,7 @@ static int idma64_pause(struct dma_chan *chan)
 
        spin_lock_irqsave(&idma64c->vchan.lock, flags);
        if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
-               idma64_chan_deactivate(idma64c);
+               idma64_chan_deactivate(idma64c, false);
                idma64c->desc->status = DMA_PAUSED;
        }
        spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
@@ -486,7 +488,7 @@ static int idma64_terminate_all(struct dma_chan *chan)
        LIST_HEAD(head);
 
        spin_lock_irqsave(&idma64c->vchan.lock, flags);
-       idma64_chan_deactivate(idma64c);
+       idma64_chan_deactivate(idma64c, true);
        idma64_stop_transfer(idma64c);
        if (idma64c->desc) {
                idma64_vdesc_free(&idma64c->desc->vdesc);

diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h
index a4d99685a7c4015c95baad86a8e07646489e4770..f6aeff0af8a52ea4a65a67d0eaada1b05ac88edd 100644 (file)
--- a/drivers/dma/idma64.h
+++ b/drivers/dma/idma64.h
@@ -16,6 +16,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include <asm-generic/io-64-nonatomic-lo-hi.h>
+
 #include "virt-dma.h"
 
 /* Channel registers */
@@ -166,19 +168,13 @@ static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
 
 static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
 {
-       u64 l, h;
-
-       l = idma64c_readl(idma64c, offset);
-       h = idma64c_readl(idma64c, offset + 4);
-
-       return l | (h << 32);
+       return lo_hi_readq(idma64c->regs + offset);
 }
 
 static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
                                  u64 value)
 {
-       idma64c_writel(idma64c, offset, value);
-       idma64c_writel(idma64c, offset + 4, value >> 32);
+       lo_hi_writeq(value, idma64c->regs + offset);
 }
 
 #define channel_readq(idma64c, reg)            \
@@ -217,7 +213,7 @@ static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
        idma64_writel(idma64, IDMA64_##reg, (value))
 
 /**
- * struct idma64_chip - representation of DesignWare DMA controller hardware
+ * struct idma64_chip - representation of iDMA 64-bit controller hardware
  * @dev:               struct device of the DMA controller
  * @irq:               irq line
  * @regs:              memory mapped I/O space