Correct the definitions of ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK and
ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK to 0x03000000 and 0x30000000 respectively
Signed-off-by: Peter Chan <B18700@freescale.com>
#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13)
#define ANADIG_ANA_MISC2_CONTROL3_MASK 0xC0000000
#define ANADIG_ANA_MISC2_CONTROL3_OFFSET 30
-#define ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK 0x30000000
-#define ANADIG_ANA_MISC2_REG1_STEP_TIME_MASK 0xC000000
-#define ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK 0x3000000
+#define ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK 0x03000000
+#define ANADIG_ANA_MISC2_REG1_STEP_TIME_MASK 0x0C000000
+#define ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK 0x30000000
#define MXC_CCM_BASE MX6_IO_ADDRESS(CCM_BASE_ADDR)
/* CCM Register Offsets. */