clk: tegra: pll: Don't unconditionally set LOCK flags

SoC specific drivers should define the appropriate flags for each
PLL rather than relying on the registration functions to automatically
set flags on their behalf. This will properly allow for changes between
SoC generations where flags might be different and allow sharing the
same logic functions.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 79f4dc230dee47482570e8fef75595f44335f176..54046266bdfbc98c5fe1e1cbe2950d5c11f65d9d 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1434,7 +1434,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
        struct clk *clk;
 
        pll_params->flags |= TEGRA_PLL_BYPASS;
-       pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+
        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
        if (IS_ERR(pll))
                return ERR_CAST(pll);
@@ -1464,8 +1464,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
        struct tegra_clk_pll *pll;
        struct clk *clk;
 
-       pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
-       pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+       pll_params->flags |= TEGRA_PLL_BYPASS;
 
        if (!pll_params->div_nmp)
                pll_params->div_nmp = &pll_e_nmp;
@@ -1569,7 +1568,6 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
                writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
        }
 
-       pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
        if (IS_ERR(pll))
                return ERR_CAST(pll);
@@ -1592,8 +1590,6 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
        struct tegra_clk_pll *pll;
        struct clk *clk;
 
-       pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
-
        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
 
        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
@@ -1653,7 +1649,6 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
 
        pll_params->flags |= TEGRA_PLL_BYPASS;
-       pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
        pll_params->flags |= TEGRA_PLLM;
        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
        if (IS_ERR(pll))
@@ -1751,7 +1746,6 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
        struct clk *clk;
        u32 val, val_aux;
 
-       pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
        if (IS_ERR(pll))
                return ERR_CAST(pll);
@@ -1813,7 +1807,6 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
                return ERR_PTR(-EINVAL);
        }
 
-       pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
        if (IS_ERR(pll))
                return ERR_CAST(pll);

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index a373d9f7397d36a3ee220333a08af53b32d09fc6..0b942e0cacc239a5dcaa2a241ede9b1c7bb27ead 100644 (file)
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -232,7 +232,7 @@ static struct tegra_clk_pll_params pll_c_params = {
        .pdiv_tohw = pllxc_p,
        .div_nmp = &pllxc_nmp,
        .freq_table = pll_c_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct div_nmp pllcx_nmp = {
@@ -351,7 +351,7 @@ static struct tegra_clk_pll_params pll_m_params = {
        .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
        .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
        .freq_table = pll_m_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct div_nmp pllp_nmp = {
@@ -386,7 +386,8 @@ static struct tegra_clk_pll_params pll_p_params = {
        .lock_delay = 300,
        .div_nmp = &pllp_nmp,
        .freq_table = pll_p_freq_table,
-       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
        .fixed_rate = 408000000,
 };
 
@@ -415,7 +416,8 @@ static struct tegra_clk_pll_params pll_a_params = {
        .lock_delay = 300,
        .div_nmp = &pllp_nmp,
        .freq_table = pll_a_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
@@ -451,7 +453,7 @@ static struct tegra_clk_pll_params pll_d_params = {
        .div_nmp = &pllp_nmp,
        .freq_table = pll_d_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_d2_params = {
@@ -469,7 +471,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
        .div_nmp = &pllp_nmp,
        .freq_table = pll_d_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static const struct pdiv_map pllu_p[] = {
@@ -512,7 +514,7 @@ static struct tegra_clk_pll_params pll_u_params = {
        .div_nmp = &pllu_nmp,
        .freq_table = pll_u_freq_table,
        .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
@@ -546,7 +548,7 @@ static struct tegra_clk_pll_params pll_x_params = {
        .pdiv_tohw = pllxc_p,
        .div_nmp = &pllxc_nmp,
        .freq_table = pll_x_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
@@ -581,7 +583,7 @@ static struct tegra_clk_pll_params pll_e_params = {
        .lock_delay = 300,
        .div_nmp = &plle_nmp,
        .freq_table = pll_e_freq_table,
-       .flags = TEGRA_PLL_FIXED,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
        .fixed_rate = 100000000,
 };
 
@@ -609,7 +611,8 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
        .iddq_reg = PLLRE_MISC,
        .iddq_bit_idx = PLLRE_IDDQ_BIT,
        .div_nmp = &pllre_nmp,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
+                TEGRA_PLL_LOCK_MISC,
 };
 
 /* possible OSC frequencies in Hz */

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 156a753e902df3293cbd86fa7a4fb5f37947b033..3c93dbf4b9bdd7f281ee5fe2bd9f7061db7ba9fe 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -218,7 +218,7 @@ static struct tegra_clk_pll_params pll_x_params = {
        .pdiv_tohw = pllxc_p,
        .div_nmp = &pllxc_nmp,
        .freq_table = pll_x_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
@@ -252,7 +252,7 @@ static struct tegra_clk_pll_params pll_c_params = {
        .pdiv_tohw = pllxc_p,
        .div_nmp = &pllxc_nmp,
        .freq_table = pll_c_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct div_nmp pllcx_nmp = {
@@ -386,6 +386,7 @@ static struct tegra_clk_pll_params pll_c4_params = {
        .ext_misc_reg[1] = 0x5b0,
        .ext_misc_reg[2] = 0x5b4,
        .freq_table = pll_c4_freq_table,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static const struct pdiv_map pllm_p[] = {
@@ -433,7 +434,7 @@ static struct tegra_clk_pll_params pll_m_params = {
        .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
        .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
        .freq_table = pll_m_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
@@ -469,7 +470,7 @@ static struct tegra_clk_pll_params pll_e_params = {
        .lock_delay = 300,
        .div_nmp = &plle_nmp,
        .freq_table = pll_e_freq_table,
-       .flags = TEGRA_PLL_FIXED,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
        .fixed_rate = 100000000,
 };
 
@@ -507,7 +508,8 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
        .iddq_reg = PLLRE_MISC,
        .iddq_bit_idx = PLLRE_IDDQ_BIT,
        .div_nmp = &pllre_nmp,
-       .flags = TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
+                TEGRA_PLL_LOCK_MISC,
 };
 
 static struct div_nmp pllp_nmp = {
@@ -543,7 +545,8 @@ static struct tegra_clk_pll_params pll_p_params = {
        .div_nmp = &pllp_nmp,
        .freq_table = pll_p_freq_table,
        .fixed_rate = 408000000,
-       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
@@ -570,7 +573,8 @@ static struct tegra_clk_pll_params pll_a_params = {
        .lock_delay = 300,
        .div_nmp = &pllp_nmp,
        .freq_table = pll_a_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct div_nmp plld_nmp = {
@@ -615,7 +619,7 @@ static struct tegra_clk_pll_params pll_d_params = {
        .div_nmp = &plld_nmp,
        .freq_table = pll_d_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
@@ -648,6 +652,7 @@ static struct tegra_clk_pll_params tegra124_pll_d2_params = {
        .ext_misc_reg[2] = 0x578,
        .max_p = 15,
        .freq_table = tegra124_pll_d2_freq_table,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
@@ -680,6 +685,7 @@ static struct tegra_clk_pll_params pll_dp_params = {
        .ext_misc_reg[2] = 0x5a0,
        .max_p = 5,
        .freq_table = pll_dp_freq_table,
+       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static const struct pdiv_map pllu_p[] = {
@@ -722,7 +728,7 @@ static struct tegra_clk_pll_params pll_u_params = {
        .div_nmp = &pllu_nmp,
        .freq_table = pll_u_freq_table,
        .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 struct utmi_clk_param {

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index d7da6fd8ca30f1682707f6fb94977bacd361518d..b49d94bc0b8f51f42b30b537d8eb6465af20d581 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -291,7 +291,7 @@ static struct tegra_clk_pll_params pll_c_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_c_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_m_params = {
@@ -307,7 +307,7 @@ static struct tegra_clk_pll_params pll_m_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_m_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_p_params = {
@@ -323,7 +323,8 @@ static struct tegra_clk_pll_params pll_p_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_p_freq_table,
-       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
        .fixed_rate =  216000000,
 };
 
@@ -340,7 +341,7 @@ static struct tegra_clk_pll_params pll_a_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_a_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_d_params = {
@@ -356,7 +357,7 @@ static struct tegra_clk_pll_params pll_d_params = {
        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
        .lock_delay = 1000,
        .freq_table = pll_d_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static const struct pdiv_map pllu_p[] = {
@@ -379,7 +380,7 @@ static struct tegra_clk_pll_params pll_u_params = {
        .lock_delay = 1000,
        .pdiv_tohw = pllu_p,
        .freq_table = pll_u_freq_table,
-       .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -395,7 +396,7 @@ static struct tegra_clk_pll_params pll_x_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_x_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_e_params = {
@@ -411,7 +412,8 @@ static struct tegra_clk_pll_params pll_e_params = {
        .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
        .lock_delay = 0,
        .freq_table = pll_e_freq_table,
-       .flags = TEGRA_PLL_FIXED,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
        .fixed_rate = 100000000,
 };
 

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 019a7fc5512d3dbd9fd4cc845714ea552935c851..a78f033c57e687b26156f44566c9f75c4705496c 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -420,7 +420,8 @@ static struct tegra_clk_pll_params pll_c_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_c_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct div_nmp pllm_nmp = {
@@ -452,7 +453,8 @@ static struct tegra_clk_pll_params pll_m_params = {
        .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
        .freq_table = pll_m_freq_table,
        .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
-                TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_p_params = {
@@ -468,7 +470,8 @@ static struct tegra_clk_pll_params pll_p_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_p_freq_table,
-       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
        .fixed_rate = 408000000,
 };
 
@@ -485,7 +488,8 @@ static struct tegra_clk_pll_params pll_a_params = {
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_a_freq_table,
-       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
+       .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_d_params = {
@@ -502,7 +506,7 @@ static struct tegra_clk_pll_params pll_d_params = {
        .lock_delay = 1000,
        .freq_table = pll_d_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_d2_params = {
@@ -519,7 +523,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
        .lock_delay = 1000,
        .freq_table = pll_d_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_u_params = {
@@ -536,7 +540,8 @@ static struct tegra_clk_pll_params pll_u_params = {
        .lock_delay = 1000,
        .pdiv_tohw = pllu_p,
        .freq_table = pll_u_freq_table,
-       .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
+       .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -553,7 +558,7 @@ static struct tegra_clk_pll_params pll_x_params = {
        .lock_delay = 300,
        .freq_table = pll_x_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
-                TEGRA_PLL_USE_LOCK,
+                TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 };
 
 static struct tegra_clk_pll_params pll_e_params = {
@@ -569,7 +574,8 @@ static struct tegra_clk_pll_params pll_e_params = {
        .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .freq_table = pll_e_freq_table,
-       .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
+       .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
+                TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
        .fixed_rate = 100000000,
 };