ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
endif
ifdef CONFIG_SND_IMX_SOC
static struct clk *clks[IMX6SL_CLK_CLK_END];
static struct clk_onecell_data clk_data;
+static u32 cur_arm_podf;
+
+/*
+ * On MX6SL, need to ensure that the ARM:IPG clock ratio is maintained
+ * within 12:5 when the clocks to ARM are gated when the SOC enters
+ * WAIT mode. This is necessary to avoid WAIT mode issue (an early
+ * interrupt waking up the ARM).
+ * This function will set the ARM clk to max value within the 12:5 limit.
+ */
+void imx6sl_set_wait_clk(bool enter)
+{
+ u32 parent_rate = clk_get_rate(clk_get_parent(clks[IMX6SL_CLK_ARM]));
+
+ if (enter) {
+ u32 ipg_rate = clk_get_rate(clks[IMX6SL_CLK_IPG]);
+ u32 max_arm_wait_clk = (12 * ipg_rate) / 5;
+ u32 wait_podf = (parent_rate + max_arm_wait_clk - 1) /
+ max_arm_wait_clk;
+
+ cur_arm_podf = parent_rate / clk_get_rate(clks[IMX6SL_CLK_ARM]);
+ clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / wait_podf);
+ } else
+ clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / cur_arm_podf);
+}
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
{
clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+ /* Ensure the AHB clk is at 132MHz. */
+ ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
+ if (ret)
+ pr_warn("%s: failed to set AHB clock rate %d\n", __func__, ret);
+
/*
* To prevent the bus clock from being disabled accidently when
* clk_disable() gets called on child clock, let's increment the use
extern void imx_anatop_pu_enable(bool enable);
extern int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6_set_cache_lpm_in_wait(bool enable);
+extern void imx6sl_set_wait_clk(bool enter);
extern void imx_cpu_die(unsigned int cpu);
extern int imx_cpu_kill(unsigned int cpu);
--- /dev/null
+/*
+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+
+#include "common.h"
+#include "cpuidle.h"
+
+static int imx6sl_enter_wait(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ imx6_set_lpm(WAIT_UNCLOCKED);
+ imx6sl_set_wait_clk(true);
+ cpu_do_idle();
+ imx6sl_set_wait_clk(false);
+ imx6_set_lpm(WAIT_CLOCKED);
+
+ return index;
+}
+
+static struct cpuidle_driver imx6sl_cpuidle_driver = {
+ .name = "imx6sl_cpuidle",
+ .owner = THIS_MODULE,
+ .states = {
+ /* WFI */
+ ARM_CPUIDLE_WFI_STATE,
+ /* WAIT */
+ {
+ .exit_latency = 50,
+ .target_residency = 75,
+ .flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_TIMER_STOP,
+ .enter = imx6sl_enter_wait,
+ .name = "WAIT",
+ .desc = "Clock off",
+ },
+ },
+ .state_count = 2,
+ .safe_state_index = 0,
+};
+
+int __init imx6sl_cpuidle_init(void)
+{
+ return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
+}
/*
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
* Copyright 2012 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
#ifdef CONFIG_CPU_IDLE
extern int imx5_cpuidle_init(void);
extern int imx6q_cpuidle_init(void);
+extern int imx6sl_cpuidle_init(void);
#else
static inline int imx5_cpuidle_init(void)
{
{
return 0;
}
+static inline int imx6sl_cpuidle_init(void)
+{
+ return 0;
+}
#endif
#include <asm/mach/map.h>
#include "common.h"
+#include "cpuidle.h"
#include "hardware.h"
static struct platform_device imx6sl_cpufreq_pdev = {
else
pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
+ /* Init CPUIDLE */
+ imx6sl_cpuidle_init();
+
if (IS_ENABLED(CONFIG_ARM_IMX6_CPUFREQ)) {
imx6sl_opp_init(&imx6sl_cpufreq_pdev.dev);
platform_device_register(&imx6sl_cpufreq_pdev);