void __init s3c6410_init_clocks(int xtal)
{
- printk(KERN_INFO "%s: initialising clocks\n", __func__);
+ printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks();
{
int uart, irq;
- printk(KERN_INFO "%s: initialising interrupts\n", __func__);
+ printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
{
unsigned long rate = clk_get_rate(clk->parent);
- printk(KERN_INFO "%s: parent is %ld\n", __func__, rate);
+ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
rate /= 2;
unsigned int ptr;
u32 clkdiv0;
- printk(KERN_INFO "%s: registering clocks\n", __func__);
+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
- printk(KERN_INFO "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
+ printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
- printk(KERN_INFO "%s: xtal is %ld\n", __func__, xtal);
+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
epll = s3c6400_get_epll(xtal);
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));