drm/radeon/kms: demystify r600 blit code

some 3d register bits look like magic in r600 blit functions
use predefined constants to make it more intuitive what they are

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 3940be619af7df05a80342a27bdb392c87fb64c2..d4e215f15062c98ed6551dc9cd99436dbc5f51fa 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -58,7 +58,9 @@ set_render_target(struct radeon_device *rdev, int format,
        if (h < 8)
                h = 8;
 
-       cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
+       cb_color_info = CB_FORMAT(format) |
+               CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
+               CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
        pitch = (w / 8) - 1;
        slice = ((w * h) / 64) - 1;
 
@@ -168,9 +170,10 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 {
        u32 sq_vtx_constant_word2;
 
-       sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
+       sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
+               SQ_VTXC_STRIDE(16);
 #ifdef __BIG_ENDIAN
-       sq_vtx_constant_word2 |= (2 << 30);
+       sq_vtx_constant_word2 |=  SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 #endif
 
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
@@ -206,18 +209,19 @@ set_tex_resource(struct radeon_device *rdev,
        if (h < 1)
                h = 1;
 
-       sq_tex_resource_word0 = (1 << 0) | (1 << 3);
-       sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
-                                 ((w - 1) << 19));
+       sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
+               S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+       sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
+               S_038000_TEX_WIDTH(w - 1);
 
-       sq_tex_resource_word1 = (format << 26);
-       sq_tex_resource_word1 |= ((h - 1) << 0);
+       sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
+       sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
 
-       sq_tex_resource_word4 = ((1 << 14) |
-                                (0 << 16) |
-                                (1 << 19) |
-                                (2 << 22) |
-                                (3 << 25));
+       sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
+               S_038010_DST_SEL_X(SQ_SEL_X) |
+               S_038010_DST_SEL_Y(SQ_SEL_Y) |
+               S_038010_DST_SEL_Z(SQ_SEL_Z) |
+               S_038010_DST_SEL_W(SQ_SEL_W);
 
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
        radeon_ring_write(rdev, 0);

diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 0245ae6c204ec60a739dd2200eff1d858e9a38da..bfe1b5d92afe86e093b8c61013a49ae053209be1 100644 (file)
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -79,6 +79,11 @@
 #define CB_COLOR0_SIZE                                  0x28060
 #define CB_COLOR0_VIEW                                  0x28080
 #define CB_COLOR0_INFO                                  0x280a0
+#      define CB_FORMAT(x)                             ((x) << 2)
+#       define CB_ARRAY_MODE(x)                         ((x) << 8)
+#      define CB_SOURCE_FORMAT(x)                      ((x) << 27)
+#      define CB_SF_EXPORT_FULL                        0
+#      define CB_SF_EXPORT_NORM                        1
 #define CB_COLOR0_TILE                                  0x280c0
 #define CB_COLOR0_FRAG                                  0x280e0
 #define CB_COLOR0_MASK                                  0x28100
@@ -417,6 +422,17 @@
 #define        SQ_PGM_START_VS                                 0x28858
 #define SQ_PGM_RESOURCES_VS                             0x28868
 #define SQ_PGM_CF_OFFSET_VS                             0x288d0
+
+#define SQ_VTX_CONSTANT_WORD0_0                                0x30000
+#define SQ_VTX_CONSTANT_WORD1_0                                0x30004
+#define SQ_VTX_CONSTANT_WORD2_0                                0x30008
+#      define SQ_VTXC_BASE_ADDR_HI(x)                  ((x) << 0)
+#      define SQ_VTXC_STRIDE(x)                        ((x) << 8)
+#      define SQ_VTXC_ENDIAN_SWAP(x)                   ((x) << 30)
+#      define SQ_ENDIAN_NONE                           0
+#      define SQ_ENDIAN_8IN16                          1
+#      define SQ_ENDIAN_8IN32                          2
+#define SQ_VTX_CONSTANT_WORD3_0                                0x3000c
 #define        SQ_VTX_CONSTANT_WORD6_0                         0x38018
 #define                S__SQ_VTX_CONSTANT_TYPE(x)                      (((x) & 3) << 30)
 #define                G__SQ_VTX_CONSTANT_TYPE(x)                      (((x) >> 30) & 3)
@@ -1352,6 +1368,12 @@
 #define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
 #define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
 #define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#      define SQ_SEL_X                                 0
+#      define SQ_SEL_Y                                 1
+#      define SQ_SEL_Z                                 2
+#      define SQ_SEL_W                                 3
+#      define SQ_SEL_0                                 4
+#      define SQ_SEL_1                                 5
 #define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
 #define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
 #define   C_038010_BASE_LEVEL                          0x0FFFFFFF