drm/i915: Add ILK support to intel_read_wm_latency

ILK has a slightly different way to read out the watermark
latency values. On ILK the LP0 latenciy values are in fact
not stored in any register, and instead we must use fixed
values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c4020631b36f957621ce2ff39b1b21d01c1cf28..e5e0fb2a3e9394371ffe3dcfeabf069f483501cf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2372,6 +2372,13 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
                wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
                wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
                wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
+       } else if (INTEL_INFO(dev)->gen >= 5) {
+               uint32_t mltr = I915_READ(MLTR_ILK);
+
+               /* ILK primary LP0 latency is 700 ns */
+               wm[0] = 7;
+               wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
+               wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
        }
 }