drm/i915: Store and use edram capabilities

Store the edram capabilities instead of only the size of
edram. This is preparatory patch to allow edram size calculation
based on edram capability bits for gen9+. With gen9 the
edram is behind llc and is a separate entity. With hsw/bdw
it was more of a victim cache for LLC so the name 'eLLC' might
be warranted. Regardless, rename all mentions of eLLC to EDRAM to
clear the confusion.

v2: return bytes for edram size (Chris)
    s/eLLC/eDRAM in output if we are gen > 8

v3: rebase, INTEL_GEN (Chris)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2d11b4948a74a4aba4c947c446776f7ee8731834..16afaee10b026e1d76911b9973ca0bbf69b7d3ef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2404,10 +2404,11 @@ static int i915_llc(struct seq_file *m, void *data)
        struct drm_info_node *node = m->private;
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
+       const bool edram = INTEL_GEN(dev_priv) > 8;
 
-       /* Size calculation for LLC is a bit of a pain. Ignore for now. */
        seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
-       seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
+       seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
+                  intel_uncore_edram_size(dev_priv)/1024/1024);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d1e6e580a92de32a00ebbe02337cfc5e361e2ed7..986281ebc2241a504c02d5965423ec153ac7788a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1873,7 +1873,7 @@ struct drm_i915_private {
        struct intel_l3_parity l3_parity;
 
        /* Cannot be determined by PCIID. You must always read a register. */
-       size_t ellc_size;
+       u32 edram_cap;
 
        /* gen6+ rps state */
        struct intel_gen6_power_mgmt rps;
@@ -2624,8 +2624,9 @@ struct drm_i915_cmd_table {
 #define HAS_VEBOX(dev)         (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
 #define HAS_LLC(dev)           (INTEL_INFO(dev)->has_llc)
 #define HAS_SNOOP(dev)         (INTEL_INFO(dev)->has_snoop)
+#define HAS_EDRAM(dev)         (__I915__(dev)->edram_cap & EDRAM_ENABLED)
 #define HAS_WT(dev)            ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
-                                __I915__(dev)->ellc_size)
+                                HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->gen >= 6)
@@ -2803,6 +2804,8 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
                                        enum forcewake_domains domains);
 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
                                        enum forcewake_domains domains);
+u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
+
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
 static inline bool intel_vgpu_active(struct drm_device *dev)
 {

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3e1222b57feeb78a5538bf6d6acaac557a1a36c3..2843813290d8bc625b5c625ffbe133a5a69f7e0c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4892,7 +4892,7 @@ i915_gem_init_hw(struct drm_device *dev)
        /* Double layer security blanket, see i915_gem_init() */
        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-       if (dev_priv->ellc_size && INTEL_GEN(dev_priv) < 9)
+       if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
                I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
        if (IS_HASWELL(dev))

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5cb04907525558ebf53c8ab3e7c2036c46e2411..9f165feb54ae59e361bdd60a37b82f7c16f39432 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3172,7 +3172,8 @@ int i915_ggtt_init_hw(struct drm_device *dev)
        } else if (INTEL_INFO(dev)->gen < 8) {
                ggtt->probe = gen6_gmch_probe;
                ggtt->base.cleanup = gen6_gmch_remove;
-               if (IS_HASWELL(dev) && dev_priv->ellc_size)
+
+               if (HAS_EDRAM(dev))
                        ggtt->base.pte_encode = iris_pte_encode;
                else if (IS_HASWELL(dev))
                        ggtt->base.pte_encode = hsw_pte_encode;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cea5a390d8c980cd71f1a102e3153ea77b208da2..bedce95aa0461c1ee693b992cf7d6b869379e3d4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6882,7 +6882,7 @@ enum skl_disp_power_wells {
 
 #define  HSW_IDICR                             _MMIO(0x9008)
 #define    IDIHASHMSK(x)                       (((x) & 0x3f) << 16)
-#define  HSW_EDRAM_PRESENT                     _MMIO(0x120010)
+#define  HSW_EDRAM_CAP                         _MMIO(0x120010)
 #define    EDRAM_ENABLED                       0x1
 
 #define GEN6_UCGCTL1                           _MMIO(0x9400)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 144700cd360bae5e321a48c886076e9203a2b265..89cda6342ce20c5bff31ceed451c230484b971fd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -315,21 +315,36 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
        spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void intel_uncore_ellc_detect(struct drm_device *dev)
+u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = dev->dev_private;
+       if (!HAS_EDRAM(dev_priv))
+               return 0;
+
+       /* The docs do not explain exactly how the calculation can be
+        * made. It is somewhat guessable, but for now, it's always
+        * 128MB.
+        */
+
+       return 128 * 1024 * 1024;
+}
+
+static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
+{
+       if (IS_HASWELL(dev_priv) ||
+           IS_BROADWELL(dev_priv) ||
+           INTEL_GEN(dev_priv) >= 9) {
+               dev_priv->edram_cap = __raw_i915_read32(dev_priv,
+                                                       HSW_EDRAM_CAP);
 
-       if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
-            INTEL_INFO(dev)->gen >= 9) &&
-           (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
-               /* The docs do not explain exactly how the calculation can be
-                * made. It is somewhat guessable, but for now, it's always
-                * 128MB.
-                * NB: We can't write IDICR yet because we do not have gt funcs
+               /* NB: We can't write IDICR yet because we do not have gt funcs
                 * set up */
-               dev_priv->ellc_size = 128;
-               DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
+       } else {
+               dev_priv->edram_cap = 0;
        }
+
+       if (HAS_EDRAM(dev_priv))
+               DRM_INFO("Found %lluMB of eDRAM\n",
+                        intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 }
 
 static bool
@@ -1301,7 +1316,7 @@ void intel_uncore_init(struct drm_device *dev)
 
        i915_check_vgpu(dev);
 
-       intel_uncore_ellc_detect(dev);
+       intel_uncore_edram_detect(dev_priv);
        intel_uncore_fw_domains_init(dev);
        __intel_uncore_early_sanitize(dev, false);