<0 0xf1002000 0 0x1000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
---- interrupts = <1 9 0xf04>;
++++ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
---- gpio0: gpio@ffc40000 {
++++ gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
---- reg = <0 0xffc40000 0 0x2c>;
++++ reg = <0 0xe6050000 0 0x50>;
interrupt-parent = <&gic>;
---- interrupts = <0 4 0x4>;
++++ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 32>;
interrupt-controller;
};
---- gpio1: gpio@ffc41000 {
++++ gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
---- reg = <0 0xffc41000 0 0x2c>;
++++ reg = <0 0xe6051000 0 0x50>;
interrupt-parent = <&gic>;
---- interrupts = <0 5 0x4>;
++++ interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 32>;
interrupt-controller;
};
---- gpio2: gpio@ffc42000 {
++++ gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
---- reg = <0 0xffc42000 0 0x2c>;
++++ reg = <0 0xe6052000 0 0x50>;
interrupt-parent = <&gic>;
---- interrupts = <0 6 0x4>;
++++ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 32>;
interrupt-controller;
};
---- gpio3: gpio@ffc43000 {
++++ gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
---- reg = <0 0xffc43000 0 0x2c>;
++++ reg = <0 0xe6053000 0 0x50>;
interrupt-parent = <&gic>;
---- interrupts = <0 7 0x4>;
++++ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 32>;
interrupt-controller;
};
---- gpio4: gpio@ffc44000 {
++++ gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
---- reg = <0 0xffc44000 0 0x2c>;
++++ reg = <0 0xe6054000 0 0x50>;
interrupt-parent = <&gic>;
---- interrupts = <0 8 0x4>;
++++ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
interrupt-controller;
};
---- gpio5: gpio@ffc45000 {
++++ gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
---- reg = <0 0xffc45000 0 0x2c>;
++++ reg = <0 0xe6055000 0 0x50>;
interrupt-parent = <&gic>;
---- interrupts = <0 9 0x4>;
++++ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 32>;
CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+++ CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
---- CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
++++ CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
---- CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
++++ CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
---- CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
++++ CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
---- CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
++++ CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
---- CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
++++ CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
---- CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
++++ CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+++ CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
+++ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
+++
+++ /* ICK */
+++ CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
+++ CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
+++ CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
+++ CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
+++ CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
+++ CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
+++ CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
+++ CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
+++ CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
+++ CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
+++ CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
+++ CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
+++ CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
+++ CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
+++ CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
+++ CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
+++
};
#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \