Merge tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudee...

Merge "SCPI support on ARM64 Juno Development Platform" from Sudeep Holla:

  1. SRAM, MHU mailbox and SCPI support
  2. CPU topology using cpu-map
  3. Clock support for all the cpus
  4. Support for SoC sensors

* tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: Add sensor node to Juno dt
  arm64: dts: add clock support for all the cpus
  arm64: dts: add CPU topology on Juno
  arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index e3ee96036eca17a04b513880f29d65c6fe71a532..dd5158eb5872396693bba678cda765a719e25e97 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -17,6 +17,18 @@
                };
        };
 
+       mailbox: mhu@2b1f0000 {
+               compatible = "arm,mhu", "arm,primecell";
+               reg = <0x0 0x2b1f0000 0x0 0x1000>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "mhu_lpri_rx",
+                                 "mhu_hpri_rx";
+               #mbox-cells = <1>;
+               clocks = <&soc_refclk100mhz>;
+               clock-names = "apb_pclk";
+       };
+
        gic: interrupt-controller@2c010000 {
                compatible = "arm,gic-400", "arm,cortex-a15-gic";
                reg = <0x0 0x2c010000 0 0x1000>,
@@ -44,6 +56,53 @@
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
+       sram: sram@2e000000 {
+               compatible = "arm,juno-sram-ns", "mmio-sram";
+               reg = <0x0 0x2e000000 0x0 0x8000>;
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x0 0x2e000000 0x8000>;
+
+               cpu_scp_lpri: scp-shmem@0 {
+                       compatible = "arm,juno-scp-shmem";
+                       reg = <0x0 0x200>;
+               };
+
+               cpu_scp_hpri: scp-shmem@200 {
+                       compatible = "arm,juno-scp-shmem";
+                       reg = <0x200 0x200>;
+               };
+       };
+
+       scpi {
+               compatible = "arm,scpi";
+               mboxes = <&mailbox 1>;
+               shmem = <&cpu_scp_hpri>;
+
+               clocks {
+                       compatible = "arm,scpi-clocks";
+
+                       scpi_dvfs: scpi_clocks@0 {
+                               compatible = "arm,scpi-dvfs-clocks";
+                               #clock-cells = <1>;
+                               clock-indices = <0>, <1>, <2>;
+                               clock-output-names = "atlclk", "aplclk","gpuclk";
+                       };
+                       scpi_clk: scpi_clocks@3 {
+                               compatible = "arm,scpi-variable-clocks";
+                               #clock-cells = <1>;
+                               clock-indices = <3>, <4>;
+                               clock-output-names = "pxlclk0", "pxlclk1";
+                       };
+               };
+
+               scpi_sensors0: sensors {
+                       compatible = "arm,scpi-sensors";
+                       #thermal-sensor-cells = <1>;
+               };
+       };
+
        /include/ "juno-clocks.dtsi"
 
        dma@7ff00000 {

diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index c62751153a4fc528202b4d645fc930f851aa2bc1..5eef4aa0c5320e5a3d4f1ae9427f57a0b5881063 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -34,12 +34,39 @@
                #address-cells = <2>;
                #size-cells = <0>;
 
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&A57_0>;
+                               };
+                               core1 {
+                                       cpu = <&A57_1>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&A53_0>;
+                               };
+                               core1 {
+                                       cpu = <&A53_1>;
+                               };
+                               core2 {
+                                       cpu = <&A53_2>;
+                               };
+                               core3 {
+                                       cpu = <&A53_3>;
+                               };
+                       };
+               };
+
                A57_0: cpu@0 {
                        compatible = "arm,cortex-a57","arm,armv8";
                        reg = <0x0 0x0>;
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A57_L2>;
+                       clocks = <&scpi_dvfs 0>;
                };
 
                A57_1: cpu@1 {
@@ -48,6 +75,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A57_L2>;
+                       clocks = <&scpi_dvfs 0>;
                };
 
                A53_0: cpu@100 {
@@ -56,6 +84,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A53_1: cpu@101 {
@@ -64,6 +93,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A53_2: cpu@102 {
@@ -72,6 +102,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A53_3: cpu@103 {
@@ -80,6 +111,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A57_L2: l2-cache0 {

diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d7cbdd482a61d231cbbfcff772dcf48e51e92bb2..c02f880584e886bb2e67231d17b8c5ac6ccd63ef 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -34,12 +34,39 @@
                #address-cells = <2>;
                #size-cells = <0>;
 
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&A57_0>;
+                               };
+                               core1 {
+                                       cpu = <&A57_1>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&A53_0>;
+                               };
+                               core1 {
+                                       cpu = <&A53_1>;
+                               };
+                               core2 {
+                                       cpu = <&A53_2>;
+                               };
+                               core3 {
+                                       cpu = <&A53_3>;
+                               };
+                       };
+               };
+
                A57_0: cpu@0 {
                        compatible = "arm,cortex-a57","arm,armv8";
                        reg = <0x0 0x0>;
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A57_L2>;
+                       clocks = <&scpi_dvfs 0>;
                };
 
                A57_1: cpu@1 {
@@ -48,6 +75,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A57_L2>;
+                       clocks = <&scpi_dvfs 0>;
                };
 
                A53_0: cpu@100 {
@@ -56,6 +84,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A53_1: cpu@101 {
@@ -64,6 +93,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A53_2: cpu@102 {
@@ -72,6 +102,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A53_3: cpu@103 {
@@ -80,6 +111,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
+                       clocks = <&scpi_dvfs 1>;
                };
 
                A57_L2: l2-cache0 {