]> git.karo-electronics.de Git - linux-beck.git/commitdiff
ath9k_hw: INI changes for WoW for AR9002 chipsets
authorMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Tue, 10 Jul 2012 09:25:54 +0000 (14:55 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Thu, 12 Jul 2012 19:27:16 +0000 (15:27 -0400)
for AR9002 family of chipsets and for WoW sleep, we reprogram
the SerDes so that the PLL and CHK REQ are both enabled. this
uses more power but in certain cases this is required as otherwise
WoW sleep is unstable and chip may disappear.

Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Cc: vadivel@qca.qualcomm.com
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9002_hw.c
drivers/net/wireless/ath/ath9k/ar9002_initvals.h
drivers/net/wireless/ath/ath9k/hw.h

index edf21ea4fe930ee19fe508d7c01d58dc153c3892..0e6ee60aed005791af9bf01748b2fcd8a9621cae 100644 (file)
@@ -43,6 +43,11 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
                INIT_INI_ARRAY(&ah->iniPcieSerdes,
                           ar9280PciePhy_clkreq_always_on_L1_9280,
                           ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
+#ifdef CONFIG_PM_SLEEP
+               INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
+                              ar9280PciePhy_awow,
+                              ARRAY_SIZE(ar9280PciePhy_awow), 2);
+#endif
 
        if (AR_SREV_9287_11_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
index 4d18c66a6790362483be6a3ab4be86332826686a..beb6162cf97cbc36e39b3611c9d2cb063f04a3d3 100644 (file)
@@ -925,6 +925,20 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
        {0x00004044, 0x00000000},
 };
 
+static const u32 ar9280PciePhy_awow[][2] = {
+       /* Addr      allmodes  */
+       {0x00004040, 0x9248fd00},
+       {0x00004040, 0x24924924},
+       {0x00004040, 0xa8000019},
+       {0x00004040, 0x13160820},
+       {0x00004040, 0xe5980560},
+       {0x00004040, 0xc01dcffd},
+       {0x00004040, 0x1aaabe41},
+       {0x00004040, 0xbe105554},
+       {0x00004040, 0x00043007},
+       {0x00004044, 0x00000000},
+};
+
 static const u32 ar9285Modes_9285_1_2[][5] = {
        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
        {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
index 09f6c07601702aa85fcd1b25648be0ccafd98011..51589fd8a3ed6df0cebcef73f98b8aea7a6fade8 100644 (file)
@@ -860,6 +860,9 @@ struct ath_hw {
        struct ar5416IniArray iniBank7;
        struct ar5416IniArray iniAddac;
        struct ar5416IniArray iniPcieSerdes;
+#ifdef CONFIG_PM_SLEEP
+       struct ar5416IniArray iniPcieSerdesWow;
+#endif
        struct ar5416IniArray iniPcieSerdesLowPower;
        struct ar5416IniArray iniModesFastClock;
        struct ar5416IniArray iniAdditional;