ENGR00329844-01 ARM: dts: imx6sx: add uart5 dte pad set for imx6sx-sdb board

Add imx6sx-sdb baord uart5 DTE pad set. To avoid a flood of dts files,
there only comment out DTE pinctrl set. If user want to test DTE mode,
it needs to rebuild the DTB file.

(cherry picked from commit 4bd6e1654495e190e61a70c9b2c44fda931e2727)

Signed-off-by: Fugang Duan <B38611@freescale.com>

diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h
index 3e0b816dac08ff368ef6259d2d67e72df7011bf9..21c014092acfd2b9e83ef578c686ae2558735884 100755 (executable)
--- a/arch/arm/boot/dts/imx6sx-pinfunc.h
+++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -380,6 +380,7 @@
 #define MX6SX_PAD_KEY_COL2__KPP_COL_2                             0x00AC 0x03F4 0x0000 0x0 0x0
 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B                           0x00AC 0x03F4 0x0874 0x1 0x1
 #define MX6SX_PAD_KEY_COL2__UART5_RTS_B                           0x00AC 0x03F4 0x084C 0x2 0x2
+#define MX6SX_PAD_KEY_COL2__UART5_CTS_B                           0x00AC 0x03F4 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_COL2__CAN1_TX                               0x00AC 0x03F4 0x0000 0x3 0x0
 #define MX6SX_PAD_KEY_COL2__CANFD_TX1                             0x00AC 0x03F4 0x0000 0x4 0x0
 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12                           0x00AC 0x03F4 0x0000 0x5 0x0
@@ -424,6 +425,7 @@
 #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2                             0x00C0 0x0408 0x0000 0x0 0x0
 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP                             0x00C0 0x0408 0x0878 0x1 0x1
 #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B                           0x00C0 0x0408 0x084C 0x2 0x3
+#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B                           0x00C0 0x0408 0x084C 0x2 0x3
 #define MX6SX_PAD_KEY_ROW2__CAN1_RX                               0x00C0 0x0408 0x068C 0x3 0x1
 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1                             0x00C0 0x0408 0x0694 0x4 0x1
 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17                           0x00C0 0x0408 0x0000 0x5 0x0

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 99f28e220c5ca089691cd4b31a64bc5aca82e97a..1affbbc7a0a2efe35225f8236f9164f7a281663d 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -237,6 +237,9 @@
        pinctrl-0 = <&pinctrl_uart5>;
        fsl,uart-has-rtscts;
        status = "okay";
+       /* for DTE mode, add below change */
+       /* fsl,dte-mode;*/
+       /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
 };
 
 &usdhc2 {
@@ -389,6 +392,15 @@
                        >;
                };
 
+               pinctrl_uart5dte_1: uart5dtegrp-1 {
+                       fsl,pins = <
+                               MX6SX_PAD_KEY_ROW3__UART5_TX            0x1b0b1
+                               MX6SX_PAD_KEY_COL3__UART5_RX            0x1b0b1
+                               MX6SX_PAD_KEY_ROW2__UART5_RTS_B         0x1b0b1
+                               MX6SX_PAD_KEY_COL2__UART5_CTS_B         0x1b0b1
+                       >;
+               };
+
                pinctrl_usdhc2: usdhc2grp {
                        fsl,pins = <
                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059