ENGR00153785 ipuv3: use ipu internal divider for external di clock

on imx6q, pll5 can only provide rate >=650M, and ipu_di_clk only has max
divider 8, so need use ipu internal clock divider for some low resolution
case. For example 640x480p60 need 25.2MHz pixel clock.

Signed-off-by: Jason Chen <b02280@freescale.com>

diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index fc28b3700a7f07346e91f3774c2cccce639a35f2..e956529dd2cd310f101c208d406593ed4e478ecb 100644 (file)
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -1087,8 +1087,13 @@ int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
                                rounded_pixel_clk = pixel_clk * 2;
                                rounded_parent_clk = clk_round_rate(di_parent,
                                                        rounded_pixel_clk);
-                               while (rounded_pixel_clk < rounded_parent_clk)
-                                       rounded_pixel_clk += pixel_clk * 2;
+                               while (rounded_pixel_clk < rounded_parent_clk) {
+                                       /* the max divider from parent to di is 8 */
+                                       if (rounded_parent_clk / pixel_clk < 8)
+                                               rounded_pixel_clk += pixel_clk * 2;
+                                       else
+                                               rounded_pixel_clk *= 2;
+                               }
                                clk_set_rate(di_parent, rounded_pixel_clk);
                                rounded_pixel_clk =
                                        clk_round_rate(ipu->di_clk[disp], pixel_clk);