ARM: 8665/1: nommu: access ID_PFR1 only if CPUID scheme

Greg upon trying to boot no-MMU Kernel on ARM926EJ reported boot
failure. He root caused it to ID_PFR1 access introduced by the
commit mentioned in the fixes tag below.

All CP15 processors need not have processor feature registers, only
for architectures defined by CPUID scheme would have it. Hence check
for it before accessing processor feature register, ID_PFR1.

Fixes: f8300a0b5de0 ("ARM: 8647/2: nommu: dynamic exception base address setting")
Reported-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Tested-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 3b5c7aaf9c76c522f8c6cbd7890c5105b3a3e1d4..33a45bd9686012c2547b218133f59a0169fea33d 100644 (file)
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -303,7 +303,10 @@ static inline void set_vbar(unsigned long val)
  */
 static inline bool security_extensions_enabled(void)
 {
-       return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4);
+       /* Check CPUID Identification Scheme before ID_PFR1 read */
+       if ((read_cpuid_id() & 0x000f0000) == 0x000f0000)
+               return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4);
+       return 0;
 }
 
 static unsigned long __init setup_vectors_base(void)