drm/i915: Preserve the FDI line reversal override bit on CPT

commit 3e68320ef84528604d971afc3cadfbe208bef001 upstream.

The FDI link has supported link reversal to make the PCB layout
engineer's life easier for quite a while and we have always presered
this bit as we programmed FDI_RX_CTL with a read/modify/write sequence.

We're trying to take a bit more control over what the BIOS leaves in
various register and with the introduction of DDI, started to program
FDI_RX_CTL fully.

There's a fused bit to indicate DMI link reversal and FDI defaults to
mirroring that configuration. We have a bit to override that behaviour
that we need to preserve from the BIOS.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12ab3bdea54dca227e8bd5f3f62cf00a31ce85ba..7339a4b89d5fcdfa53923892e66093d3dbeadb7e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -919,7 +919,7 @@ typedef struct drm_i915_private {
        bool hw_contexts_disabled;
        uint32_t hw_context_size;
 
-       bool fdi_rx_polarity_reversed;
+       u32 fdi_rx_config;
 
        struct i915_suspend_saved_registers regfile;
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76e0b381ea24089c82ef85757c68f7fdc1c1b0d8..37da050e939d6ab8e73415f7f7f2b85d8eacfc82 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3927,7 +3927,7 @@
 #define  FDI_10BPC                      (1<<16)
 #define  FDI_6BPC                       (2<<16)
 #define  FDI_12BPC                      (3<<16)
-#define  FDI_LINK_REVERSE_OVERWRITE     (1<<15)
+#define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
 #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
 #define  FDI_RX_PLL_ENABLE              (1<<13)
 #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9293878ec7eb53165e259e1607a57e23519dbaa7..06b17865ed9412831bd868b2d945b8465214cb56 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -800,10 +800,14 @@ void intel_crt_init(struct drm_device *dev)
        dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
 
        /*
-        * TODO: find a proper way to discover whether we need to set the
-        * polarity reversal bit or not, instead of relying on the BIOS.
+        * TODO: find a proper way to discover whether we need to set the the
+        * polarity and link reversal bits or not, instead of relying on the
+        * BIOS.
         */
-       if (HAS_PCH_LPT(dev))
-               dev_priv->fdi_rx_polarity_reversed =
-                    !!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT);
+       if (HAS_PCH_LPT(dev)) {
+               u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
+                                FDI_RX_LINK_REVERSAL_OVERRIDE;
+
+               dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
+       }
 }

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b17e5eae8583cc8a5b2359e8abf695ee1eb97dc0..59b778de0c0dcc0c36cb9ea698915499316d2284 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -178,10 +178,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
                                  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 
        /* Enable the PCH Receiver FDI PLL */
-       rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
-                    ((intel_crtc->fdi_lanes - 1) << 19);
-       if (dev_priv->fdi_rx_polarity_reversed)
-               rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT;
+       rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+                    FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
        I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
        POSTING_READ(_FDI_RXA_CTL);
        udelay(220);