Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xx

diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index 796ae22a6915a95d97e3de374d0d47a7f0ea1722..36d7e1ed487b0a1865d96e61bcd2330be1e1fa81 100644 (file)
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -542,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd)
 #endif
 
 #ifdef CONFIG_PCIE1
-       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
        if (p != NULL) {
                p[0] = 0;
                p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;

diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 900c3680c71dbb55bdda8a73acf66274123f17ee..68ccba746ba9a08c7c9ec2b6e3dbe341289698dd 100644 (file)
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -237,6 +237,6 @@ law_entry:
 
        /* contains both PCIE3 MEM & IO space */
        .long   (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
+       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
        entry_end

diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 80822bec73715169e20cf1a3d7ca9570fb04caa8..76d909191f9605a088beabbdae79a49862b79507 100644 (file)
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
 #include <spd.h>
 #include <miiphy.h>
 
@@ -222,6 +223,11 @@ pci_init_board(void)
                printf ("    PCIE3 on bus %02x - %02x\n",
                        hose->first_busno,hose->last_busno);
 
+               /*
+                * Activate ULI1575 legacy chip by performing a fake
+                * memory access.  Needed to make ULI RTC work.
+                */
+               in_be32(CFG_PCIE3_MEM_BASE);
        } else {
                printf ("    PCIE3: disabled\n");
        }
@@ -516,8 +522,16 @@ ft_board_setup(void *blob, bd_t *bd)
                *p++ = cpu_to_be32(bd->bi_memstart);
                *p = cpu_to_be32(bd->bi_memsize);
        }
+#ifdef CONFIG_PCI1
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+               debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
 #ifdef CONFIG_PCIE1
-       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
        if (p != NULL) {
                p[0] = 0;
                p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
@@ -525,7 +539,7 @@ ft_board_setup(void *blob, bd_t *bd)
        }
 #endif
 #ifdef CONFIG_PCIE2
-       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
        if (p != NULL) {
                p[0] = 0;
                p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
@@ -533,7 +547,7 @@ ft_board_setup(void *blob, bd_t *bd)
        }
 #endif
 #ifdef CONFIG_PCIE3
-       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
        if (p != NULL) {
                p[0] = 0;
                p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index ffd11cb5f1384e2a6e428cc7f393ccc4b795fdf5..931be9f375e946f5db416db438ece824f8bd6bbc 100644 (file)
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -338,6 +338,22 @@ ft_board_setup(void *blob, bd_t *bd)
                *p++ = cpu_to_be32(bd->bi_memstart);
                *p = cpu_to_be32(bd->bi_memsize);
        }
+#ifdef CONFIG_PCI1
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+               debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
+#ifdef CONFIG_PCI2
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+               debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
 }
 #endif
 

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 9743f031e0b495648dc8ea58c31d9164bae147f0..f580ccadee5ea515ff5b911c348da1529834eca6 100644 (file)
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -310,6 +310,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCIE3_IO_BASE      0x00000000
 #define CFG_PCIE3_IO_PHYS      0xb0100000      /* reuse mem LAW */
 #define CFG_PCIE3_IO_SIZE      0x00100000      /* 1M */
+#define CFG_PCIE3_MEM_BASE2    0xb0200000
+#define CFG_PCIE3_MEM_PHYS2    CFG_PCIE3_MEM_BASE2
+#define CFG_PCIE3_MEM_SIZE2    0x00200000      /* 1M */
 
 #if defined(CONFIG_PCI)