ARM: dts: ventana: add UHS-I support for Ventana boards

UHS-I support is available on Ventana boards with micro-SD sockets depending
on the board revision. To support this pinctl states for 100Mhz and 200MHz
must be added as well as pinmux of the VSELECT signal. In order to support
UHS-I the I/O rail of the 4-bit data bus must be switchable between 1.8V
and 3.3V.

By adding the no-1-8-v property, which disables UHS-I support, we allow the
bootloader to be in charge of selecting which boards have this capability
by removing that property if the board model/revision implement the support.

Additionally we will remove NANDF_CS1 here from the nand pinmux group as the
second chip-select is not used on any ventana boards and this is the pad
that is used for SD3_VELECT.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index f2867c4b34a858c3b07fda639a123d9688708249..7b31fdb79ced5cbac2eecff792fa8d56b1a9a010 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -248,7 +248,6 @@
                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index b5756c21ea1d55b791b10e6728b573a918ad78e7..b8e35513aed28eaa504ff1ff77ef2b552f37ce27 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -316,10 +316,13 @@
 };
 
 &usdhc3 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
        cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
        vmmc-supply = <&reg_3p3v>;
+       no-1-8-v; /* firmware will remove if board revision supports */
        status = "okay";
 };
 
@@ -380,7 +383,6 @@
                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
@@ -469,7 +471,34 @@
                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
-                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
+                       >;
+               };
+
+               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
+                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
+                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
+                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
+                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
+                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
+                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
+                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
+                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
+                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
+                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
                        >;
                };
        };

diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 86f03c1b147c630c43166aa9d4782da28f333519..765c3a758ae02d632bb5a49aa5bd952429af3366 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -322,10 +322,13 @@
 };
 
 &usdhc3 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
        cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
        vmmc-supply = <&reg_3p3v>;
+       no-1-8-v; /* firmware will remove if board revision supports */
        status = "okay";
 };
 
@@ -385,7 +388,6 @@
                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
@@ -476,7 +478,34 @@
                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
-                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0 /* CD */
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
+                       >;
+               };
+
+               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
+                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
+                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
+                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
+                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
+                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
+                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
+                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
+                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
+                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
+                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
                        >;
                };
        };

diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 4a8d97f477592316c3d9ff86cee4bc1b5c9e887f..1100aab4be54ab8d54384165869466a12464ed88 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -415,10 +415,13 @@
 };
 
 &usdhc3 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
        cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
        vmmc-supply = <&reg_3p3v>;
+       no-1-8-v; /* firmware will remove if board revision supports */
        status = "okay";
 };
 
@@ -478,7 +481,6 @@
                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
@@ -568,6 +570,34 @@
                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
+                       >;
+               };
+
+               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
+                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
+                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
+                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
+                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
+                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
+                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
+                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
+                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
+                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
+                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
+                               MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
                        >;
                };
        };

diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index d1866a0a2f1330c7b583cfb78475b2f8a20d0eed..741f3d529e3e23bcf3cb17160620fb30ae2c79dc 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -250,7 +250,6 @@
                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 5c6587f6c4201baf95ea3a114acb368ab3d78951..d1e5048b00b51c493b7843c7eba5d9e824269e86 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -202,7 +202,6 @@
                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                               MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1