#include "r8180_93cx6.h"
-static void eprom_cs(struct net_device *dev, short bit)
+static void eprom_cs(struct r8192_priv *priv, short bit)
{
if (bit)
- write_nic_byte(dev, EPROM_CMD,
+ write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CS_SHIFT) |
- read_nic_byte(dev, EPROM_CMD)); //enable EPROM
+ read_nic_byte(priv, EPROM_CMD)); //enable EPROM
else
- write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD)
+ write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_CS_SHIFT)); //disable EPROM
udelay(EPROM_DELAY);
}
-static void eprom_ck_cycle(struct net_device *dev)
+static void eprom_ck_cycle(struct r8192_priv *priv)
{
- write_nic_byte(dev, EPROM_CMD,
- (1<<EPROM_CK_SHIFT) | read_nic_byte(dev, EPROM_CMD));
+ write_nic_byte(priv, EPROM_CMD,
+ (1<<EPROM_CK_SHIFT) | read_nic_byte(priv, EPROM_CMD));
udelay(EPROM_DELAY);
- write_nic_byte(dev, EPROM_CMD,
- read_nic_byte(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
+ write_nic_byte(priv, EPROM_CMD,
+ read_nic_byte(priv, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
udelay(EPROM_DELAY);
}
-static void eprom_w(struct net_device *dev, short bit)
+static void eprom_w(struct r8192_priv *priv, short bit)
{
if (bit)
- write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) |
- read_nic_byte(dev, EPROM_CMD));
+ write_nic_byte(priv, EPROM_CMD, (1<<EPROM_W_SHIFT) |
+ read_nic_byte(priv, EPROM_CMD));
else
- write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD)
+ write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_W_SHIFT));
udelay(EPROM_DELAY);
}
-static short eprom_r(struct net_device *dev)
+static short eprom_r(struct r8192_priv *priv)
{
short bit;
- bit = (read_nic_byte(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT));
+ bit = (read_nic_byte(priv, EPROM_CMD) & (1<<EPROM_R_SHIFT));
udelay(EPROM_DELAY);
if (bit)
}
-static void eprom_send_bits_string(struct net_device *dev, short b[], int len)
+static void eprom_send_bits_string(struct r8192_priv *priv, short b[], int len)
{
int i;
for (i = 0; i < len; i++) {
- eprom_w(dev, b[i]);
- eprom_ck_cycle(dev);
+ eprom_w(priv, b[i]);
+ eprom_ck_cycle(priv);
}
}
ret = 0;
//enable EPROM programming
- write_nic_byte(dev, EPROM_CMD,
+ write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
udelay(EPROM_DELAY);
addr_str[0] = addr & (1<<5);
addr_len = 6;
}
- eprom_cs(dev, 1);
- eprom_ck_cycle(dev);
- eprom_send_bits_string(dev, read_cmd, 3);
- eprom_send_bits_string(dev, addr_str, addr_len);
+ eprom_cs(priv, 1);
+ eprom_ck_cycle(priv);
+ eprom_send_bits_string(priv, read_cmd, 3);
+ eprom_send_bits_string(priv, addr_str, addr_len);
//keep chip pin D to low state while reading.
//I'm unsure if it is necessary, but anyway shouldn't hurt
- eprom_w(dev, 0);
+ eprom_w(priv, 0);
for (i = 0; i < 16; i++) {
//eeprom needs a clk cycle between writing opcode&adr
//and reading data. (eeprom outs a dummy 0)
- eprom_ck_cycle(dev);
- ret |= (eprom_r(dev)<<(15-i));
+ eprom_ck_cycle(priv);
+ ret |= (eprom_r(priv)<<(15-i));
}
- eprom_cs(dev, 0);
- eprom_ck_cycle(dev);
+ eprom_cs(priv, 0);
+ eprom_ck_cycle(priv);
//disable EPROM programming
- write_nic_byte(dev, EPROM_CMD,
+ write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
return ret;
}
}
}
TxAGC = (byte1<<8) |byte0;
- write_nic_dword(dev, CCK_TXAGC, TxAGC);
+ write_nic_dword(priv, CCK_TXAGC, TxAGC);
#else
#ifdef RTL8192E
//DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp);
//DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2);
- write_nic_dword(dev, MCS_TXAGC, TxAGC1);
- write_nic_dword(dev, MCS_TXAGC+4, TxAGC2);
+ write_nic_dword(priv, MCS_TXAGC, TxAGC1);
+ write_nic_dword(priv, MCS_TXAGC+4, TxAGC2);
#else
#ifdef RTL8192E
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} else {
- write_nic_byte(dev, ANAPAR, 0x37);//160MHz
- //write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403
+ write_nic_byte(priv, ANAPAR, 0x37);//160MHz
+ //write_nic_byte(priv, MacBlkCtrl, 0x17); // 0x403
mdelay(1);
//enable clock 80/88 MHz
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
// Baseband reset 2008.09.30 add
- //write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0));
+ //write_nic_byte(priv, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0));
//2 AFE
// 2008.09.30 add
// PlatformZeroMemory( pMgntInfo->Bssid, 6 );
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55;
priv->OpMode = RT_OP_MODE_NO_LINK;
- write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
- write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
+ write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
+ write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
{
RT_OP_MODE OpMode = priv->OpMode;
//LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
- u8 btMsr = read_nic_byte(dev, MSR);
+ u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
break;
}
- write_nic_byte(dev, MSR, btMsr);
+ write_nic_byte(priv, MSR, btMsr);
// LED control
//Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
{
u32 RegRCR, Type;
Type = bFilterOutNonAssociatedBSSID;
- RegRCR = read_nic_dword(dev,RCR);
+ RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
RegRCR |= (RCR_CBSSID);
RegRCR &= (~RCR_CBSSID);
{
- write_nic_dword(dev, RCR,RegRCR);
+ write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR;
}
{
RT_OP_MODE OpMode = priv->OpMode;
//LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
- u8 btMsr = read_nic_byte(dev, MSR);
+ u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
break;
}
- write_nic_byte(dev, MSR, btMsr);
+ write_nic_byte(priv, MSR, btMsr);
// LED control
//Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
}
ieee80211_disassociate(priv->ieee80211);
- write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
- write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
+ write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
+ write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
}
Type = bFilterOutNonAssociatedBSSID;
//Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RCR, (pu1Byte)(&RegRCR));
- RegRCR = read_nic_dword(dev,RCR);
+ RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
- write_nic_dword(dev, RCR,RegRCR);
+ write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR;
bool init_firmware(struct net_device *dev);
short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
-u32 read_cam(struct net_device *dev, u8 addr);
-void write_cam(struct net_device *dev, u8 addr, u32 data);
-u8 read_nic_byte(struct net_device *dev, int x);
+u32 read_cam(struct r8192_priv *priv, u8 addr);
+void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
+u8 read_nic_byte(struct r8192_priv *priv, int x);
u8 read_nic_byte_E(struct net_device *dev, int x);
-u32 read_nic_dword(struct net_device *dev, int x);
-u16 read_nic_word(struct net_device *dev, int x) ;
-void write_nic_byte(struct net_device *dev, int x,u8 y);
-void write_nic_byte_E(struct net_device *dev, int x,u8 y);
-void write_nic_word(struct net_device *dev, int x,u16 y);
-void write_nic_dword(struct net_device *dev, int x,u32 y);
+u32 read_nic_dword(struct r8192_priv *priv, int x);
+u16 read_nic_word(struct r8192_priv *priv, int x) ;
+void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
+void write_nic_byte_E(struct net_device *priv, int x,u8 y);
+void write_nic_word(struct r8192_priv *priv, int x,u16 y);
+void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
void rtl8192_halt_adapter(struct net_device *dev, bool reset);
void rtl8192_rx_enable(struct net_device *);
void CamResetAllEntry(struct net_device *dev)
{
- write_nic_dword(dev, RWCAM, BIT31|BIT30);
+ struct r8192_priv* priv = ieee80211_priv(dev);
+ write_nic_dword(priv, RWCAM, BIT31|BIT30);
}
-
-void write_cam(struct net_device *dev, u8 addr, u32 data)
+void write_cam(struct r8192_priv *priv, u8 addr, u32 data)
{
- write_nic_dword(dev, WCAMI, data);
- write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) );
+ write_nic_dword(priv, WCAMI, data);
+ write_nic_dword(priv, RWCAM, BIT31|BIT16|(addr&0xff) );
}
-u32 read_cam(struct net_device *dev, u8 addr)
+
+u32 read_cam(struct r8192_priv *priv, u8 addr)
{
- write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) );
- return read_nic_dword(dev, 0xa8);
+ write_nic_dword(priv, RWCAM, 0x80000000|(addr&0xff) );
+ return read_nic_dword(priv, 0xa8);
}
#ifdef CONFIG_RTL8180_IO_MAP
-u8 read_nic_byte(struct net_device *dev, int x)
+u8 read_nic_byte(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return 0xff&inb(dev->base_addr +x);
}
-u32 read_nic_dword(struct net_device *dev, int x)
+u32 read_nic_dword(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return inl(dev->base_addr +x);
}
-u16 read_nic_word(struct net_device *dev, int x)
+u16 read_nic_word(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return inw(dev->base_addr +x);
}
-void write_nic_byte(struct net_device *dev, int x,u8 y)
+void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
outb(y&0xff,dev->base_addr +x);
}
-void write_nic_word(struct net_device *dev, int x,u16 y)
+void write_nic_word(struct r8192_priv *priv, int x,u16 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
outw(y,dev->base_addr +x);
}
-void write_nic_dword(struct net_device *dev, int x,u32 y)
+void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
outl(y,dev->base_addr +x);
}
#else /* RTL_IO_MAP */
-u8 read_nic_byte(struct net_device *dev, int x)
+u8 read_nic_byte(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return 0xff&readb((u8*)dev->mem_start +x);
}
-u32 read_nic_dword(struct net_device *dev, int x)
+u32 read_nic_dword(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return readl((u8*)dev->mem_start +x);
}
-u16 read_nic_word(struct net_device *dev, int x)
+u16 read_nic_word(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return readw((u8*)dev->mem_start +x);
}
-void write_nic_byte(struct net_device *dev, int x,u8 y)
+void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
writeb(y,(u8*)dev->mem_start +x);
udelay(20);
}
-void write_nic_dword(struct net_device *dev, int x,u32 y)
+void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
writel(y,(u8*)dev->mem_start +x);
udelay(20);
}
-void write_nic_word(struct net_device *dev, int x,u16 y)
+void write_nic_word(struct r8192_priv *priv, int x,u16 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
writew(y,(u8*)dev->mem_start +x);
udelay(20);
}
{
case HW_VAR_BSSID:
- write_nic_dword(dev, BSSIDR, ((u32*)(val))[0]);
- write_nic_word(dev, BSSIDR+2, ((u16*)(val+2))[0]);
+ write_nic_dword(priv, BSSIDR, ((u32*)(val))[0]);
+ write_nic_word(priv, BSSIDR+2, ((u16*)(val+2))[0]);
break;
case HW_VAR_MEDIA_STATUS:
{
RT_OP_MODE OpMode = *((RT_OP_MODE *)(val));
- u8 btMsr = read_nic_byte(dev, MSR);
+ u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
break;
}
- write_nic_byte(dev, MSR, btMsr);
+ write_nic_byte(priv, MSR, btMsr);
}
break;
u32 RegRCR, Type;
Type = ((u8*)(val))[0];
- RegRCR = read_nic_dword(dev,RCR);
+ RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
- write_nic_dword(dev, RCR,RegRCR);
+ write_nic_dword(priv, RCR,RegRCR);
priv->ReceiveConfig = RegRCR;
}
case HW_VAR_SLOT_TIME:
{
priv->slot_time = val[0];
- write_nic_byte(dev, SLOT_TIME, val[0]);
+ write_nic_byte(priv, SLOT_TIME, val[0]);
}
break;
regTmp = priv->basic_rate;
if (priv->short_preamble)
regTmp |= BRSR_AckShortPmb;
- write_nic_dword(dev, RRSR, regTmp);
+ write_nic_dword(priv, RRSR, regTmp);
}
break;
case HW_VAR_CPU_RST:
- write_nic_dword(dev, CPU_GEN, ((u32*)(val))[0]);
+ write_nic_dword(priv, CPU_GEN, ((u32*)(val))[0]);
break;
default:
int *eof, void *data)
{
struct net_device *dev = data;
+ struct r8192_priv *priv = ieee80211_priv(dev);
int len = 0;
int i,n;
int max=0xff;
for(i=0;i<16 && n<=max;i++,n++)
len += snprintf(page + len, count - len,
- "%2x ",read_nic_byte(dev,n));
+ "%2x ",read_nic_byte(priv,n));
}
len += snprintf(page + len, count - len,"\n");
len += snprintf(page + len, count - len,
for(i=0;i<16 && n<=max;i++,n++)
len += snprintf(page + len, count - len,
- "%2x ",read_nic_byte(dev,0x100|n));
+ "%2x ",read_nic_byte(priv,0x100|n));
}
len += snprintf(page + len, count - len,
for(i=0;i<16 && n<=max;i++,n++)
len += snprintf(page + len, count - len,
- "%2x ",read_nic_byte(dev,0x300|n));
+ "%2x ",read_nic_byte(priv,0x300|n));
}
*eof = 1;
{
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
priv->irq_enabled = 1;
- write_nic_dword(dev,INTA_MASK, priv->irq_mask);
+ write_nic_dword(priv, INTA_MASK, priv->irq_mask);
}
void rtl8192_irq_disable(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
- write_nic_dword(dev,INTA_MASK,0);
+ write_nic_dword(priv, INTA_MASK, 0);
priv->irq_enabled = 0;
}
struct r8192_priv *priv = ieee80211_priv(dev);
u8 msr;
- msr = read_nic_byte(dev, MSR);
+ msr = read_nic_byte(priv, MSR);
msr &= ~ MSR_LINK_MASK;
/* do not change in link_state != WLAN_LINK_ASSOCIATED.
}else
msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
- write_nic_byte(dev, MSR, msr);
+ write_nic_byte(priv, MSR, msr);
}
void rtl8192_set_chan(struct net_device *dev,short ch)
{
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
- write_nic_dword(dev, RDQDA,priv->rx_ring_dma);
+ write_nic_dword(priv, RDQDA,priv->rx_ring_dma);
}
/* the TX_DESC_BASE setting is according to the following queue index
u32 i;
for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
- write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
+ write_nic_dword(priv, TX_DESC_BASE[i], priv->tx_ring[i].dma);
ieee80211_reset_queue(priv->ieee80211);
}
void PHY_SetRtl8192eRfOff(struct net_device* dev)
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
+
//disable RF-Chip A/B
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
//analog to digital off, for power save
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
// Analog parameter!!Change bias and Lbus control.
- write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
+ write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07);
}
* disable tx/rx. In 8185 we write 0x10 (Reset bit),
* but here we make reference to WMAC and wirte 0x0
*/
- write_nic_byte(dev, CMDR, 0);
+ write_nic_byte(priv, CMDR, 0);
}
mdelay(20);
*/
if (!priv->ieee80211->bSupportRemoteWakeUp) {
PHY_SetRtl8192eRfOff(dev);
- ulRegRead = read_nic_dword(dev,CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
ulRegRead |= CPU_GEN_SYSTEM_RESET;
- write_nic_dword(dev,CPU_GEN, ulRegRead);
+ write_nic_dword(priv,CPU_GEN, ulRegRead);
} else {
/* for WOL */
- write_nic_dword(dev, WFCRC0, 0xffffffff);
- write_nic_dword(dev, WFCRC1, 0xffffffff);
- write_nic_dword(dev, WFCRC2, 0xffffffff);
+ write_nic_dword(priv, WFCRC0, 0xffffffff);
+ write_nic_dword(priv, WFCRC1, 0xffffffff);
+ write_nic_dword(priv, WFCRC2, 0xffffffff);
/* Write PMR register */
- write_nic_byte(dev, PMR, 0x5);
+ write_nic_byte(priv, PMR, 0x5);
/* Disable tx, enanble rx */
- write_nic_byte(dev, MacBlkCtrl, 0xa);
+ write_nic_byte(priv, MacBlkCtrl, 0xa);
}
}
tmp = priv->basic_rate;
if (priv->short_preamble)
tmp |= BRSR_AckShortPmb;
- write_nic_dword(dev, RRSR, tmp);
+ write_nic_dword(priv, RRSR, tmp);
if (net->mode & (IEEE_G|IEEE_N_24G))
{
else //long slot time
slot_time = NON_SHORT_SLOT_TIME;
priv->slot_time = slot_time;
- write_nic_byte(dev, SLOT_TIME, slot_time);
+ write_nic_byte(priv, SLOT_TIME, slot_time);
}
}
priv->basic_rate = rate_config &= 0x15f;
/* BSSID */
- write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
- write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
+ write_nic_dword(priv, BSSIDR, ((u32 *)net->bssid)[0]);
+ write_nic_word(priv, BSSIDR+4, ((u16 *)net->bssid)[2]);
if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
{
- write_nic_word(dev, ATIMWND, 2);
- write_nic_word(dev, BCN_DMATIME, 256);
- write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
+ write_nic_word(priv, ATIMWND, 2);
+ write_nic_word(priv, BCN_DMATIME, 256);
+ write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
/*
* BIT15 of BCN_DRV_EARLY_INT will indicate
* whether software beacon or hw beacon is applied.
*/
- write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
- write_nic_byte(dev, BCN_ERR_THRESH, 100);
+ write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
+ write_nic_byte(priv, BCN_ERR_THRESH, 100);
BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
/* TODO: BcnIFS may required to be changed on ASIC */
BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
- write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
+ write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
}
}
__skb_queue_tail(&ring->queue, skb);
spin_unlock_irqrestore(&priv->irq_th_lock,flags);
- write_nic_byte(dev, TPPoll, TPPoll_CQ);
+ write_nic_byte(priv, TPPoll, TPPoll_CQ);
return;
}
pdesc->OWN = 1;
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
dev->trans_start = jiffies;
- write_nic_word(dev, TPPoll, 0x01<<tcb_desc->queue_index);
+ write_nic_word(priv, TPPoll, 0x01<<tcb_desc->queue_index);
return 0;
}
{
struct r8192_priv *priv = ieee80211_priv(dev);
struct ieee80211_device* ieee = priv->ieee80211;
- //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval);
+ //write_nic_word(priv, BCN_INTR_ITV, net->beacon_interval);
if (ieee->state == IEEE80211_LINKED)
{
rtl8192_net_update(dev);
}
else
{
- write_nic_byte(dev, 0x173, 0);
+ write_nic_byte(priv, 0x173, 0);
}
/*update timing params*/
//rtl8192_set_chan(dev, priv->chan);
if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
{
u32 reg = 0;
- reg = read_nic_dword(dev, RCR);
+ reg = read_nic_dword(priv, RCR);
if (priv->ieee80211->state == IEEE80211_LINKED)
priv->ReceiveConfig = reg |= RCR_CBSSID;
else
priv->ReceiveConfig = reg &= ~RCR_CBSSID;
- write_nic_dword(dev, RCR, reg);
+ write_nic_dword(priv, RCR, reg);
}
}
static void rtl8192_qos_activate(struct work_struct * work)
{
struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
- struct net_device *dev = priv->ieee80211->dev;
struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
u8 mode = priv->ieee80211->current_network.mode;
u8 u1bAIFS;
(((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
(((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
- write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
- //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
+ write_nic_dword(priv, WDCAPARA_ADD[i], u4bAcParam);
+ //write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
}
success:
}else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
ratr_value |= 0x80000000;
}
- write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
- write_nic_byte(dev, UFWP, 1);
+ write_nic_dword(priv, RATR0+rate_index*4, ratr_value);
+ write_nic_byte(priv, UFWP, 1);
}
static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev)
u16 curCR = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
RT_TRACE(COMP_INIT, "===========>%s()\n", __FUNCTION__);
- curCR = read_nic_dword(dev, EPROM_CMD);
+ curCR = read_nic_dword(priv, EPROM_CMD);
RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, curCR);
//whether need I consider BIT5?
priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EPROM_93c56 : EPROM_93c46;
* Adapter->EEPROMAddressSize should be set before this function call.
* EEPROM address size can be got through GetEEPROMSize8185()
*/
-static void rtl8192_read_eeprom_info(struct net_device* dev)
+static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
{
- struct r8192_priv *priv = ieee80211_priv(dev);
-
+ struct net_device *dev = priv->ieee80211->dev;
u8 tempval;
#ifdef RTL8192E
u8 ICVer8192, ICVer8256;
rtl8192_init_priv_lock(priv);
rtl8192_init_priv_task(dev);
rtl8192_get_eeprom_size(dev);
- rtl8192_read_eeprom_info(dev);
+ rtl8192_read_eeprom_info(priv);
rtl8192_get_channel_map(dev);
init_hal_dm(dev);
init_timer(&priv->watch_dog_timer);
break;
}
- write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ write_nic_byte(priv, BW_OPMODE, regBwOpMode);
{
u32 ratr_value = 0;
ratr_value = regRATR;
{
ratr_value &= ~(RATE_ALL_OFDM_2SS);
}
- write_nic_dword(dev, RATR0, ratr_value);
- write_nic_byte(dev, UFWP, 1);
+ write_nic_dword(priv, RATR0, ratr_value);
+ write_nic_byte(priv, UFWP, 1);
}
- regTmp = read_nic_byte(dev, 0x313);
+ regTmp = read_nic_byte(priv, 0x313);
regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
- write_nic_dword(dev, RRSR, regRRSR);
+ write_nic_dword(priv, RRSR, regRRSR);
//
// Set Retry Limit here
//
- write_nic_word(dev, RETRY_LIMIT,
+ write_nic_word(priv, RETRY_LIMIT,
priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
// Set Contention Window here
//dPLL on
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
- write_nic_byte(dev, ANAPAR, 0x37);
+ write_nic_byte(priv, ANAPAR, 0x37);
// Accordign to designer's explain, LBUS active will never > 10ms. We delay 10ms
// Joseph increae the time to prevent firmware download fail
mdelay(500);
//3 //Config CPUReset Register
//3//
//3 Firmware Reset Or Not
- ulRegRead = read_nic_dword(dev, CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
if(priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
{ //called from MPInitialized. do nothing
ulRegRead |= CPU_GEN_SYSTEM_RESET;
ulRegRead &= (~(CPU_GEN_GPIO_UART));
#endif
- write_nic_dword(dev, CPU_GEN, ulRegRead);
+ write_nic_dword(priv, CPU_GEN, ulRegRead);
//mdelay(100);
#ifdef RTL8192E
//3 //Fix the issue of E-cut high temperature issue
//3//
// TODO: E cut only
- ICVersion = read_nic_byte(dev, IC_VERRSION);
+ ICVersion = read_nic_byte(priv, IC_VERRSION);
if(ICVersion >= 0x4) //E-cut only
{
// HW SD suggest that we should not wirte this register too often, so driver
// should readback this register. This register will be modified only when
// power on reset
- SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
+ SwitchingRegulatorOutput = read_nic_byte(priv, SWREGULATOR);
if(SwitchingRegulatorOutput != 0xb8)
{
- write_nic_byte(dev, SWREGULATOR, 0xa8);
+ write_nic_byte(priv, SWREGULATOR, 0xa8);
mdelay(1);
- write_nic_byte(dev, SWREGULATOR, 0xb8);
+ write_nic_byte(priv, SWREGULATOR, 0xb8);
}
}
#endif
//priv->LoopbackMode = RTL819X_MAC_LOOPBACK;
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
- ulRegRead = read_nic_dword(dev, CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
if(priv->LoopbackMode == RTL819X_NO_LOOPBACK)
{
ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
//2008.06.03, for WOL
//ulRegRead &= (~(CPU_GEN_GPIO_UART));
- write_nic_dword(dev, CPU_GEN, ulRegRead);
+ write_nic_dword(priv, CPU_GEN, ulRegRead);
// 2006.11.29. After reset cpu, we sholud wait for a second, otherwise, it may fail to write registers. Emily
udelay(500);
//2=======================================================
// If there is changes, please make sure it applies to all of the FPGA version
//3 Turn on Tx/Rx
- write_nic_byte(dev, CMDR, CR_RE|CR_TE);
+ write_nic_byte(priv, CMDR, CR_RE|CR_TE);
//2Set Tx dma burst
#ifdef RTL8190P
- write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
+ write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
(MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) |
(1<<MULRW_SHIFT)));
#else
#ifdef RTL8192E
- write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
+ write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
(MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) ));
#endif
#endif
//set IDR0 here
- write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
- write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
+ write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]);
+ write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
//set RCR
- write_nic_dword(dev, RCR, priv->ReceiveConfig);
+ write_nic_dword(priv, RCR, priv->ReceiveConfig);
//3 Initialize Number of Reserved Pages in Firmware Queue
#ifdef TO_DO_LIST
else
#endif
{
- write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |
+ write_nic_dword(priv, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |
NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT |
NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT |
NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
- write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
- write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW|
+ write_nic_dword(priv, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
+ write_nic_dword(priv, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW|
NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
}
//3Set Response Rate Setting Register
// CCK rate is supported by default.
// CCK rate will be filtered out only when associated AP does not support it.
- ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK;
- write_nic_dword(dev, RRSR, ulRegRead);
- write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
+ ulRegRead = (0xFFF00000 & read_nic_dword(priv, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK;
+ write_nic_dword(priv, RRSR, ulRegRead);
+ write_nic_dword(priv, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
//2Set AckTimeout
// TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
- write_nic_byte(dev, ACK_TIMEOUT, 0x30);
+ write_nic_byte(priv, ACK_TIMEOUT, 0x30);
//rtl8192_actset_wirelessmode(dev,priv->RegWirelessMode);
if(priv->ResetProgress == RESET_TYPE_NORESET)
SECR_value |= SCR_TxEncEnable;
SECR_value |= SCR_RxDecEnable;
SECR_value |= SCR_NoSKMC;
- write_nic_byte(dev, SECR, SECR_value);
+ write_nic_byte(priv, SECR, SECR_value);
}
//3Beacon related
- write_nic_word(dev, ATIMWND, 2);
- write_nic_word(dev, BCN_INTERVAL, 100);
+ write_nic_word(priv, ATIMWND, 2);
+ write_nic_word(priv, BCN_INTERVAL, 100);
for (i=0; i<QOS_QUEUE_NUM; i++)
- write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
+ write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
//
// Switching regulator controller: This is set temporarily.
// It's not sure if this can be removed in the future.
// PJ advised to leave it by default.
//
- write_nic_byte(dev, 0xbe, 0xc0);
+ write_nic_byte(priv, 0xbe, 0xc0);
//2=======================================================
// Set PHY related configuration defined in MAC register bank
}
//if D or C cut
- tmpvalue = read_nic_byte(dev, IC_VERRSION);
+ tmpvalue = read_nic_byte(priv, IC_VERRSION);
priv->IC_Cut = tmpvalue;
RT_TRACE(COMP_INIT, "priv->IC_Cut = 0x%x\n", priv->IC_Cut);
if(priv->IC_Cut >= IC_VersionCut_D)
#ifdef RTL8192E
//Enable Led
- write_nic_byte(dev, 0x87, 0x0);
+ write_nic_byte(priv, 0x87, 0x0);
#endif
#ifdef RTL8190P
//2008.06.03, for WOL
- ucRegRead = read_nic_byte(dev, GPE);
+ ucRegRead = read_nic_byte(priv, GPE);
ucRegRead |= BIT0;
- write_nic_byte(dev, GPE, ucRegRead);
+ write_nic_byte(priv, GPE, ucRegRead);
- ucRegRead = read_nic_byte(dev, GPO);
+ ucRegRead = read_nic_byte(priv, GPO);
ucRegRead &= ~BIT0;
- write_nic_byte(dev, GPO, ucRegRead);
+ write_nic_byte(priv, GPO, ucRegRead);
#endif
//2=======================================================
//rtl8192_beacon_tx_enable(dev);
/* ATIM window */
- write_nic_word(dev, ATIMWND, 2);
+ write_nic_word(priv, ATIMWND, 2);
/* Beacon interval (in unit of TU) */
- write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
+ write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
/*
* DrvErlyInt (in unit of TU).
* (Time to send interrupt to notify driver to c
* hange beacon content)
* */
- write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
+ write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
/*
* BcnDMATIM(in unit of us).
* Indicates the time before TBTT to perform beacon queue DMA
* */
- write_nic_word(dev, BCN_DMATIME, 256);
+ write_nic_word(priv, BCN_DMATIME, 256);
/*
* Force beacon frame transmission even after receiving
* beacon frame from other ad hoc STA
* */
- write_nic_byte(dev, BCN_ERR_THRESH, 100);
+ write_nic_byte(priv, BCN_ERR_THRESH, 100);
/* Set CW and IFS */
BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
- write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
+ write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
/* enable the interrupt for ad-hoc process */
static bool HalTxCheckStuck8190Pci(struct net_device *dev)
{
- u16 RegTxCounter = read_nic_word(dev, 0x128);
struct r8192_priv *priv = ieee80211_priv(dev);
+ u16 RegTxCounter = read_nic_word(priv, 0x128);
bool bStuck = FALSE;
RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
if(priv->TxCounter==RegTxCounter)
static bool HalRxCheckStuck8190Pci(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
- u16 RegRxCounter = read_nic_word(dev, 0x130);
+ u16 RegRxCounter = read_nic_word(priv, 0x130);
bool bStuck = FALSE;
RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
priv->bResetInProgress = false;
// For test --> force write UFWP.
- write_nic_byte(dev, UFWP, 1);
+ write_nic_byte(priv, UFWP, 1);
RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
}
}
setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
}
if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){
- write_nic_byte(dev, 0x173, 1); //fix aes bug
+ write_nic_byte(priv, 0x173, 1); //fix aes bug
}
}
stats.bFirstMPDU = (pDrvInfo->PartAggr==1) && (pDrvInfo->FirstAGGR==1);
stats.TimeStampLow = pDrvInfo->TSFL;
- stats.TimeStampHigh = read_nic_dword(dev, TSFR+4);
+ stats.TimeStampHigh = read_nic_dword(priv, TSFR+4);
UpdateRxPktTimeStamp8190(dev, &stats);
{
rtl8192_rx(priv->ieee80211->dev);
/* unmask RDU */
- write_nic_dword(priv->ieee80211->dev, INTA_MASK,read_nic_dword(priv->ieee80211->dev, INTA_MASK) | IMR_RDU);
+ write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) | IMR_RDU);
}
static const struct net_device_ops rtl8192_netdev_ops = {
/* ISR: 4bytes */
- inta = read_nic_dword(dev, ISR); /* & priv->IntrMask; */
- write_nic_dword(dev, ISR, inta); /* reset int situation */
+ inta = read_nic_dword(priv, ISR); /* & priv->IntrMask; */
+ write_nic_dword(priv, ISR, inta); /* reset int situation */
if (!inta) {
/*
RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n");
priv->stats.rxrdu++;
/* reset int situation */
- write_nic_dword(dev, INTA_MASK, read_nic_dword(dev, INTA_MASK) & ~IMR_RDU);
+ write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) & ~IMR_RDU);
tasklet_schedule(&priv->irq_rx_tasklet);
}
RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__,
ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
{
- write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
+ write_nic_byte(priv, SECR, SECR_value);//SECR_value | SCR_UseDK );
}
}
(u32)(*(MacAddr+1)) << 24|
(u32)usConfig;
- write_nic_dword(dev, WCAMI, TargetContent);
- write_nic_dword(dev, RWCAM, TargetCommand);
+ write_nic_dword(priv, WCAMI, TargetContent);
+ write_nic_dword(priv, RWCAM, TargetCommand);
}
else if(i==1){//MAC
TargetContent = (u32)(*(MacAddr+2)) |
(u32)(*(MacAddr+3)) << 8|
(u32)(*(MacAddr+4)) << 16|
(u32)(*(MacAddr+5)) << 24;
- write_nic_dword(dev, WCAMI, TargetContent);
- write_nic_dword(dev, RWCAM, TargetCommand);
+ write_nic_dword(priv, WCAMI, TargetContent);
+ write_nic_dword(priv, RWCAM, TargetCommand);
}
else { //Key Material
if(KeyContent != NULL)
{
- write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) );
- write_nic_dword(dev, RWCAM, TargetCommand);
+ write_nic_dword(priv, WCAMI, (u32)(*(KeyContent+i-2)) );
+ write_nic_dword(priv, RWCAM, TargetCommand);
}
}
}
if(curTxOkCnt > 4*curRxOkCnt) {
if (priv->bCurrentRxAggrEnable) {
- write_nic_dword(dev, 0x1a8, 0);
+ write_nic_dword(priv, 0x1a8, 0);
priv->bCurrentRxAggrEnable = false;
}
}else{
* when anyone of three threshold conditions above is reached,
* firmware will send aggregated packet to driver.
*/
- write_nic_dword(dev, 0x1a8, ulValue);
+ write_nic_dword(priv, 0x1a8, ulValue);
priv->bCurrentRxAggrEnable = true;
}
}
//
// Check whether updating of RATR0 is required
//
- currentRATR = read_nic_dword(dev, RATR0);
+ currentRATR = read_nic_dword(priv, RATR0);
if( targetRATR != currentRATR )
{
u32 ratr_value;
{
ratr_value &= ~(RATE_ALL_OFDM_2SS);
}
- write_nic_dword(dev, RATR0, ratr_value);
- write_nic_byte(dev, UFWP, 1);
+ write_nic_dword(priv, RATR0, ratr_value);
+ write_nic_byte(priv, UFWP, 1);
pra->last_ratr = targetRATR;
}
// bool rtStatus = true;
u32 delta=0;
RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
-// write_nic_byte(dev, 0x1ba, 0);
- write_nic_byte(dev, Pw_Track_Flag, 0);
- write_nic_byte(dev, FW_Busy_Flag, 0);
+// write_nic_byte(priv, 0x1ba, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
+ write_nic_byte(priv, FW_Busy_Flag, 0);
priv->ieee80211->bdynamic_txpower_enable = false;
bHighpowerstate = priv->bDynamicTxHighPower;
for(i = 0;i <= 30; i++)
{
- Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag);
+ Pwr_Flag = read_nic_byte(priv, Pw_Track_Flag);
if (Pwr_Flag == 0)
{
continue;
}
- Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value);
+ Avg_TSSI_Meas = read_nic_word(priv, Tssi_Mea_Value);
if(Avg_TSSI_Meas == 0)
{
- write_nic_byte(dev, Pw_Track_Flag, 0);
- write_nic_byte(dev, FW_Busy_Flag, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
+ write_nic_byte(priv, FW_Busy_Flag, 0);
return;
}
for(k = 0;k < 5; k++)
{
if(k !=4)
- tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k);
+ tmp_report[k] = read_nic_byte(priv, Tssi_Report_Value1+k);
else
- tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2);
+ tmp_report[k] = read_nic_byte(priv, Tssi_Report_Value2);
RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
}
}
if(viviflag ==TRUE)
{
- write_nic_byte(dev, Pw_Track_Flag, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
viviflag = FALSE;
RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
for(k = 0;k < 5; k++)
if(delta <= E_FOR_TX_POWER_TRACK)
{
priv->ieee80211->bdynamic_txpower_enable = TRUE;
- write_nic_byte(dev, Pw_Track_Flag, 0);
- write_nic_byte(dev, FW_Busy_Flag, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
+ write_nic_byte(priv, FW_Busy_Flag, 0);
RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
{
priv->ieee80211->bdynamic_txpower_enable = TRUE;
- write_nic_byte(dev, Pw_Track_Flag, 0);
- write_nic_byte(dev, FW_Busy_Flag, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
+ write_nic_byte(priv, FW_Busy_Flag, 0);
RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
return;
}
}
- write_nic_byte(dev, Pw_Track_Flag, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
Avg_TSSI_Meas_from_driver = 0;
for(k = 0;k < 5; k++)
tmp_report[k] = 0;
break;
}
- write_nic_byte(dev, FW_Busy_Flag, 0);
+ write_nic_byte(priv, FW_Busy_Flag, 0);
}
priv->ieee80211->bdynamic_txpower_enable = TRUE;
- write_nic_byte(dev, Pw_Track_Flag, 0);
+ write_nic_byte(priv, Pw_Track_Flag, 0);
}
#ifndef RTL8190P
static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
struct r8192_priv *priv = ieee80211_priv(dev);
static u32 tx_power_track_counter = 0;
RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
- if(read_nic_byte(dev, 0x11e) ==1)
+ if(read_nic_byte(priv, 0x11e) ==1)
return;
if(!priv->btxpower_tracking)
return;
{
ratr_value &=~ (RATE_ALL_OFDM_2SS);
}
- write_nic_dword(dev, RATR0, ratr_value);
- write_nic_byte(dev, UFWP, 1);
+ write_nic_dword(priv, RATR0, ratr_value);
+ write_nic_byte(priv, UFWP, 1);
}
//Resore TX Power Tracking Index
if(priv->btxpower_trackingInit && priv->btxpower_tracking){
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
// 1.2 Set initial gain.
- write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
- write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
- write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
- write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
+ write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x17);
+ write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x17);
+ write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x17);
+ write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x17);
// 1.3 Lower PD_TH for OFDM.
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
//PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
// 1.4 Lower CS ratio for CCK.
- write_nic_byte(dev, 0xa0a, 0x08);
+ write_nic_byte(priv, 0xa0a, 0x08);
// 1.5 Higher EDCCA.
//PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
// 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
if (reset_flag == 1)
{
- write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
- write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
- write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
- write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
+ write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x2c);
+ write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x2c);
+ write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x2c);
+ write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x2c);
}
else
{
- write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
- write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
- write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
- write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
+ write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x20);
+ write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x20);
+ write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x20);
+ write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x20);
}
// 2.2 Higher PD_TH for OFDM.
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
#endif
/*
else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
//PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
// 2.3 Higher CS ratio for CCK.
- write_nic_byte(dev, 0xa0a, 0xcd);
+ write_nic_byte(priv, 0xa0a, 0xcd);
// 2.4 Lower EDCCA.
/* 2008/01/11 MH 90/92 series are the same. */
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
*/
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
}
else
{
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
*/
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
}
}
reset_cnt = priv->reset_count;
}
- if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
+ if(dm_digtable.pre_ig_value != read_nic_byte(priv, rOFDM0_XAAGCCore1))
force_write = 1;
{
{
initial_gain = (u8)dm_digtable.cur_ig_value;
// Set initial gain.
- write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
initialized = 1;
force_write = 0;
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
*/
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
}
else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
{
/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
*/
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
}
else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
{
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
{
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
#else
- write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
+ write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
#endif
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
*/
}
else
- write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
+ write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
}
dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
if(initialized <= 3)
if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
{
// Lower CS ratio for CCK.
- write_nic_byte(dev, 0xa0a, 0x08);
+ write_nic_byte(priv, 0xa0a, 0x08);
}
else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
{
// Higher CS ratio for CCK.
- write_nic_byte(dev, 0xa0a, 0xcd);
+ write_nic_byte(priv, 0xa0a, 0xcd);
}
dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
initialized = 1;
{
if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
{
- write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
+ write_nic_dword(priv, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
priv->bis_cur_rdlstate = true;
}
}
{
if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
{
- write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
+ write_nic_dword(priv, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
priv->bis_cur_rdlstate = false;
}
((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
printk("===>u4bAcParam:%x, ", u4bAcParam);
//write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
- write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
+ write_nic_dword(priv, EDCAPARA_BE, u4bAcParam);
// Check ACM bit.
// If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
// TODO: Modified this part and try to set acm control in only 1 IO processing!!
PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
- u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
+ u8 AcmCtrl = read_nic_byte(priv, AcmHwCtrl );
if( pAciAifsn->f.ACM )
{ // ACM bit is 1.
AcmCtrl |= AcmHw_BeqEn;
}
RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
- write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
+ write_nic_byte(priv, AcmHwCtrl, AcmCtrl );
}
}
priv->bcurrent_turbo_EDCA = false;
u8 tmp1byte;
- tmp1byte = read_nic_byte(dev,GPI);
+ tmp1byte = read_nic_byte(priv, GPI);
if(tmp1byte == 0xff)
return;
} else {
// 0x108 GPIO input register is read only
//set 0x108 B1= 1: RF-ON; 0: RF-OFF.
- tmp1byte = read_nic_byte(dev,GPI);
+ tmp1byte = read_nic_byte(priv, GPI);
eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
/* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
always be the same. We only read 0xc04 now. */
- rfpath = read_nic_byte(dev, 0xc04);
+ rfpath = read_nic_byte(priv, 0xc04);
// Check Bit 0-3, it means if RF A-D is enabled.
for (i = 0; i < RF90_PATH_MAX; i++)
if(!cck_Rx_Path_initialized)
{
- DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
+ DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(priv, 0xa07)&0xf);
cck_Rx_Path_initialized = 1;
}
DM_RxPathSelTable.disabledRF = 0xf;
- DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
+ DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(priv, 0xc04));
if(priv->ieee80211->mode == WIRELESS_MODE_B)
{
void dm_fsync_timer_callback(unsigned long data)
{
- struct net_device *dev = (struct net_device *)data;
struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
u32 rate_index, rate_count = 0, rate_count_diff=0;
bool bSwitchFromCountDiff = false;
if(priv->bswitch_fsync)
{
#ifdef RTL8190P
- write_nic_byte(dev,0xC36, 0x00);
+ write_nic_byte(priv,0xC36, 0x00);
#else
- write_nic_byte(dev,0xC36, 0x1c);
+ write_nic_byte(priv,0xC36, 0x1c);
#endif
- write_nic_byte(dev, 0xC3e, 0x90);
+ write_nic_byte(priv, 0xC3e, 0x90);
}
else
{
#ifdef RTL8190P
- write_nic_byte(dev, 0xC36, 0x40);
+ write_nic_byte(priv, 0xC36, 0x40);
#else
- write_nic_byte(dev, 0xC36, 0x5c);
+ write_nic_byte(priv, 0xC36, 0x5c);
#endif
- write_nic_byte(dev, 0xC3e, 0x96);
+ write_nic_byte(priv, 0xC3e, 0x96);
}
}
else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
{
priv->bswitch_fsync = false;
#ifdef RTL8190P
- write_nic_byte(dev, 0xC36, 0x40);
+ write_nic_byte(priv, 0xC36, 0x40);
#else
- write_nic_byte(dev, 0xC36, 0x5c);
+ write_nic_byte(priv, 0xC36, 0x5c);
#endif
- write_nic_byte(dev, 0xC3e, 0x96);
+ write_nic_byte(priv, 0xC3e, 0x96);
}
}
if(bDoubleTimeInterval){
{
priv->bswitch_fsync = false;
#ifdef RTL8190P
- write_nic_byte(dev, 0xC36, 0x40);
+ write_nic_byte(priv, 0xC36, 0x40);
#else
- write_nic_byte(dev, 0xC36, 0x5c);
+ write_nic_byte(priv, 0xC36, 0x5c);
#endif
- write_nic_byte(dev, 0xC3e, 0x96);
+ write_nic_byte(priv, 0xC3e, 0x96);
}
priv->ContiuneDiffCount = 0;
#ifdef RTL8190P
- write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x164052cd);
#else
- write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
#endif
}
RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
static void dm_StartHWFsync(struct net_device *dev)
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
+
RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
- write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
- write_nic_byte(dev, 0xc3b, 0x41);
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cf);
+ write_nic_byte(priv, 0xc3b, 0x41);
}
static void dm_EndSWFsync(struct net_device *dev)
priv->bswitch_fsync = false;
#ifdef RTL8190P
- write_nic_byte(dev, 0xC36, 0x40);
+ write_nic_byte(priv, 0xC36, 0x40);
#else
- write_nic_byte(dev, 0xC36, 0x5c);
+ write_nic_byte(priv, 0xC36, 0x5c);
#endif
- write_nic_byte(dev, 0xC3e, 0x96);
+ write_nic_byte(priv, 0xC3e, 0x96);
}
priv->ContiuneDiffCount = 0;
#ifndef RTL8190P
- write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
#endif
}
add_timer(&priv->fsync_timer);
#ifndef RTL8190P
- write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cd);
#endif
}
static void dm_EndHWFsync(struct net_device *dev)
{
- RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
- write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
- write_nic_byte(dev, 0xc3b, 0x49);
+ struct r8192_priv *priv = ieee80211_priv(dev);
+ RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
+ write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
+ write_nic_byte(priv, 0xc3b, 0x49);
}
void dm_check_fsync(struct net_device *dev)
if(reg_c38_State != RegC38_Fsync_AP_BCM)
{ //For broadcom AP we write different default value
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
+ write_nic_byte(priv, rOFDM0_RxDetector3, 0x15);
#else
- write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
+ write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);
#endif
reg_c38_State = RegC38_Fsync_AP_BCM;
if(reg_c38_State != RegC38_NonFsync_Other_AP)
{
#ifdef RTL8190P
- write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
+ write_nic_byte(priv, rOFDM0_RxDetector3, 0x10);
#else
- write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
+ write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);
#endif
reg_c38_State = RegC38_NonFsync_Other_AP;
{
if(reg_c38_State)
{
- write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
+ write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
}
}
{
if(reg_c38_State)
{
- write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
+ write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
}
}
{
if(priv->reset_count != reset_cnt)
{ //After silent reset, the reg_c38_State will be returned to default value
- write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
+ write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
reset_cnt = priv->reset_count;
}
{
if(reg_c38_State)
{
- write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
+ write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
reg_c38_State = RegC38_Default;
}
}
struct r8192_priv *priv = ieee80211_priv(dev);
struct ieee80211_device* ieee = priv->ieee80211;
//for initial tx rate
- ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
+ ieee->softmac_stats.last_packet_rate = read_nic_byte(priv ,Initial_Tx_Rate_Reg);
//for tx tx retry count
- ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
+ ieee->softmac_stats.txretrycount = read_nic_dword(priv, Tx_Retry_Count_Reg);
}
static void dm_send_rssi_tofw(struct net_device *dev)
// If we test chariot, we should stop the TX command ?
// Because 92E will always silent reset when we send tx command. We use register
// 0x1e0(byte) to botify driver.
- write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
+ write_nic_byte(priv, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
return;
#if 1
tx_cmd.Op = TXCMD_SET_RX_RSSI;
else //pairwise key
{
if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){
- write_nic_byte(dev, 0x173, 1); //fix aes bug
+ write_nic_byte(priv, 0x173, 1); //fix aes bug
}
setKey( dev,
4,//EntryNo
ieee80211_softmac_stop_protocol(priv->ieee80211);
- write_nic_byte(dev,MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE);
+ write_nic_byte(priv, MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE);
if(!priv->ieee80211->bSupportRemoteWakeUp) {
/* disable tx/rx. In 8185 we write 0x10 (Reset bit),
* but here we make reference to WMAC and wirte 0x0.
if(!priv->ieee80211->bSupportRemoteWakeUp) {
MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT);
// 2006.11.30. System reset bit
- ulRegRead = read_nic_dword(dev, CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
ulRegRead|=CPU_GEN_SYSTEM_RESET;
- write_nic_dword(dev, CPU_GEN, ulRegRead);
+ write_nic_dword(priv, CPU_GEN, ulRegRead);
} else {
//2008.06.03 for WOL
- write_nic_dword(dev, WFCRC0, 0xffffffff);
- write_nic_dword(dev, WFCRC1, 0xffffffff);
- write_nic_dword(dev, WFCRC2, 0xffffffff);
+ write_nic_dword(priv, WFCRC0, 0xffffffff);
+ write_nic_dword(priv, WFCRC1, 0xffffffff);
+ write_nic_dword(priv, WFCRC2, 0xffffffff);
#ifdef RTL8190P
//GPIO 0 = TRUE
- ucRegRead = read_nic_byte(dev, GPO);
+ ucRegRead = read_nic_byte(priv, GPO);
ucRegRead |= BIT0;
- write_nic_byte(dev, GPO, ucRegRead);
+ write_nic_byte(priv, GPO, ucRegRead);
#endif
//Write PMR register
- write_nic_byte(dev, PMR, 0x5);
+ write_nic_byte(priv, PMR, 0x5);
//Disable tx, enanble rx
- write_nic_byte(dev, MacBlkCtrl, 0xa);
+ write_nic_byte(priv, MacBlkCtrl, 0xa);
}
out_pci_suspend:
*/
static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
unsigned long timeout;
bool rt_status = true;
u32 CPU_status = 0;
/* Check whether put code OK */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_PUT_CODE_OK)
break;
}
/* Turn On CPU */
- CPU_status = read_nic_dword(dev, CPU_GEN);
- write_nic_byte(dev, CPU_GEN,
+ CPU_status = read_nic_dword(priv, CPU_GEN);
+ write_nic_byte(priv, CPU_GEN,
(u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff));
mdelay(1);
/* Check whether CPU boot OK */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_BOOT_RDY)
break;
static bool CPUcheck_firmware_ready(struct net_device *dev)
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
unsigned long timeout;
bool rt_status = true;
u32 CPU_status = 0;
/* Check Firmware Ready */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
- CPU_status = read_nic_dword(dev, CPU_GEN);
+ CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_FIRM_RDY)
break;
* ****************************************************************************/
void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
{
-
+ struct r8192_priv *priv = ieee80211_priv(dev);
u32 OriginalValue, BitShift, NewValue;
if(dwBitMask!= bMaskDWord)
{//if not "double word" write
- OriginalValue = read_nic_dword(dev, dwRegAddr);
+ OriginalValue = read_nic_dword(priv, dwRegAddr);
BitShift = rtl8192_CalculateBitShift(dwBitMask);
NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
- write_nic_dword(dev, dwRegAddr, NewValue);
+ write_nic_dword(priv, dwRegAddr, NewValue);
}else
- write_nic_dword(dev, dwRegAddr, dwData);
+ write_nic_dword(priv, dwRegAddr, dwData);
}
/******************************************************************************
*function: This function reads specific bits from BB register
* ****************************************************************************/
u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
u32 OriginalValue, BitShift;
- OriginalValue = read_nic_dword(dev, dwRegAddr);
+ OriginalValue = read_nic_dword(priv, dwRegAddr);
BitShift = rtl8192_CalculateBitShift(dwBitMask);
return (OriginalValue & dwBitMask) >> BitShift;
}
RF90_RADIO_PATH_E eRFPath,
u32 Offset )
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
u32 Data = 0;
u8 time = 0;
//DbgPrint("FW RF CTRL\n\r");
// 5. Trigger Fw to operate the command. bit 31
Data |= 0x80000000;
// 6. We can not execute read operation if bit 31 is 1.
- while (read_nic_dword(dev, QPNR)&0x80000000)
+ while (read_nic_dword(priv, QPNR)&0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
break;
}
// 7. Execute read operation.
- write_nic_dword(dev, QPNR, Data);
+ write_nic_dword(priv, QPNR, Data);
// 8. Check if firmawre send back RF content.
- while (read_nic_dword(dev, QPNR)&0x80000000)
+ while (read_nic_dword(priv, QPNR)&0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
else
return 0;
}
- return read_nic_dword(dev, RF_DATA);
+ return read_nic_dword(priv, RF_DATA);
}
/******************************************************************************
u32 Offset,
u32 Data )
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
u8 time = 0;
//DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
Data |= 0x80000000;
// 6. Write operation. We can not write if bit 31 is 1.
- while (read_nic_dword(dev, QPNR)&0x80000000)
+ while (read_nic_dword(priv, QPNR)&0x80000000)
{
// If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100)
}
// 7. No matter check bit. We always force the write. Because FW will
// not accept the command.
- write_nic_dword(dev, QPNR, Data);
+ write_nic_dword(priv, QPNR, Data);
/* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
to finish RF write operation. */
/* 2008/01/17 MH We support delay in firmware side now. */
* ***************************************************************************/
RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
{
- //struct r8192_priv *priv = ieee80211_priv(dev);
+ struct r8192_priv *priv = ieee80211_priv(dev);
// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
RT_STATUS ret = RT_STATUS_SUCCESS;
u32 i, CheckTimes = 4, dwRegRead = 0;
case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1:
- write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
- dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
+ write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
+ dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
break;
case HW90_BLOCK_RF:
**************************************/
/*--set BB Global Reset--*/
- bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
- write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
+ bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
+ write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
/*---set BB reset Active---*/
- dwRegValue = read_nic_dword(dev, CPU_GEN);
- write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
+ dwRegValue = read_nic_dword(priv, CPU_GEN);
+ write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
/*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
// TODO: this function should be removed on ASIC , Emily 2007.2.2
rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
/*----Set BB reset de-Active----*/
- dwRegValue = read_nic_dword(dev, CPU_GEN);
- write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
+ dwRegValue = read_nic_dword(priv, CPU_GEN);
+ write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
/*----BB AGC table Initialization----*/
//==m==>Set PHY REG From Header<==m==
struct r8192_priv *priv = ieee80211_priv(dev);
#ifdef RTL8190P
priv->MCSTxPowerLevelOriginalOffset[0] =
- read_nic_dword(dev, MCS_TXAGC);
+ read_nic_dword(priv, MCS_TXAGC);
priv->MCSTxPowerLevelOriginalOffset[1] =
- read_nic_dword(dev, (MCS_TXAGC+4));
+ read_nic_dword(priv, (MCS_TXAGC+4));
priv->CCKTxPowerLevelOriginalOffset =
- read_nic_dword(dev, CCK_TXAGC);
+ read_nic_dword(priv, CCK_TXAGC);
#else
#ifdef RTL8192E
priv->MCSTxPowerLevelOriginalOffset[0] =
- read_nic_dword(dev, rTxAGC_Rate18_06);
+ read_nic_dword(priv, rTxAGC_Rate18_06);
priv->MCSTxPowerLevelOriginalOffset[1] =
- read_nic_dword(dev, rTxAGC_Rate54_24);
+ read_nic_dword(priv, rTxAGC_Rate54_24);
priv->MCSTxPowerLevelOriginalOffset[2] =
- read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
+ read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
priv->MCSTxPowerLevelOriginalOffset[3] =
- read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
+ read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
priv->MCSTxPowerLevelOriginalOffset[4] =
- read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
+ read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
priv->MCSTxPowerLevelOriginalOffset[5] =
- read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
+ read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
#endif
#endif
// read rx initial gain
- priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
- priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
- priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
- priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
+ priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
+ priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
+ priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
+ priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
// read framesync
- priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
- priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
+ priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
+ priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
rOFDM0_RxDetector3, priv->framesync);
// read SIFS (save the value read fome MACPHY_REG.txt)
- priv->SifsTime = read_nic_word(dev, SIFS);
+ priv->SifsTime = read_nic_word(priv, SIFS);
}
/******************************************************************************
rtl8192_SetTxPowerLevel(dev,channel);
break;
case CmdID_WritePortUlong:
- write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
+ write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
break;
case CmdID_WritePortUshort:
- write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
+ write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
break;
case CmdID_WritePortUchar:
- write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
+ write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
break;
case CmdID_RF_WriteReg:
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
return;
}
//<1>Set MAC register
- regBwOpMode = read_nic_byte(dev, BW_OPMODE);
+ regBwOpMode = read_nic_byte(priv, BW_OPMODE);
switch(priv->CurrentChannelBW)
{
case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ;
// 2007/02/07 Mark by Emily becasue we have not verify whether this register works
- write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ write_nic_byte(priv, BW_OPMODE, regBwOpMode);
break;
case HT_CHANNEL_WIDTH_20_40:
regBwOpMode &= ~BW_OPMODE_20MHZ;
// 2007/02/07 Mark by Emily becasue we have not verify whether this register works
- write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ write_nic_byte(priv, BW_OPMODE, regBwOpMode);
break;
default:
// write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
if(!priv->btxpower_tracking)
{
- write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
- write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
- write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
+ write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
+ write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
+ write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
}
else
CCK_Tx_Power_Track_BW_Switch(dev);
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
if(!priv->btxpower_tracking)
{
- write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
- write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
- write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
+ write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
+ write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
+ write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
}
else
CCK_Tx_Power_Track_BW_Switch(dev);
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
- write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
+ write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
- write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
+ write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
break;
case IG_Restore:
RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
projects / mv-sheeva.git / commitdiff