clk: samsung: exynos5420: update clocks for G2D and G3D blocks

This patch adds missing clocks of G2D block. It also removes
the aclkg3d alias from G3D block clocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 48a5772dca8945f0a587a2451c3d2942fc52c836..e263b7be505974b4449ca288ee370cf23a6a02cf 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -399,12 +399,12 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
        MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
 
        MUX(0, "mout_aclk66_psgen", mout_aclk66_peric_p, SRC_TOP5, 4, 1),
-       MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, SRC_TOP5,
-                       8, 1),
-       MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, SRC_TOP5,
-                       12, 1),
-       MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
-                       SRC_TOP5, 16, 1, "aclkg3d"),
+       MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
+                       SRC_TOP5, 8, 1),
+       MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
+                       SRC_TOP5, 12, 1),
+       MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
+                       SRC_TOP5, 16, 1),
        MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
                        SRC_TOP5, 20, 1),
        MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
@@ -602,7 +602,11 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 
 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
        /* G2D */
+       GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
        GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
+       GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
+       GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
+       GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 
        /* TODO: Re-verify the CG bits for all the gate clocks */
        GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
@@ -854,7 +858,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
        GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
        GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
 
-       GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
+       GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
 
        GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
        GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 6e22fddb01341a2f48fd999ceb719820d09dfc7d..bf85418a29457ee62e5feba498a235610b47306a 100644 (file)
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -177,6 +177,8 @@
 #define CLK_ACLK_G3D           500
 #define CLK_G3D                        501
 #define CLK_SMMU_MIXER         502
+#define CLK_SMMU_G2D           503
+#define CLK_SMMU_MDMA0         504
 #define CLK_SCLK_UART_ISP      510
 #define CLK_SCLK_SPI0_ISP      511
 #define CLK_SCLK_SPI1_ISP      512