ARM: zynq: DT: Migrate UART to Cadence binding

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 326ab6766c5618b498e71c1990f4c720e27bb3b4..a4bfc6211100fd7571025ff335581429a01a4c2b 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -149,19 +149,19 @@
                };
 
                uart0: serial@e0000000 {
-                       compatible = "xlnx,xuartps";
+                       compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                        status = "disabled";
                        clocks = <&clkc 23>, <&clkc 40>;
-                       clock-names = "ref_clk", "aper_clk";
+                       clock-names = "uart_clk", "pclk";
                        reg = <0xE0000000 0x1000>;
                        interrupts = <0 27 4>;
                };
 
                uart1: serial@e0001000 {
-                       compatible = "xlnx,xuartps";
+                       compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                        status = "disabled";
                        clocks = <&clkc 24>, <&clkc 41>;
-                       clock-names = "ref_clk", "aper_clk";
+                       clock-names = "uart_clk", "pclk";
                        reg = <0xE0001000 0x1000>;
                        interrupts = <0 50 4>;
                };