ENGR00221281 [MX6X] Fix BogoMIPS value is not correct

[MX6X] Fix BogoMIPS value is not correct

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 39e39bfe48d40eaf3916c1bc2a1a4ef9f1388f66..e2d203c0a0e06b8bf85edcf4437093e545b6462d 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5304,6 +5304,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 {
        __iomem void *base;
        int i, reg;
+       u32 parent_rate, rate;
+       unsigned long ipg_clk_rate, max_arm_wait_clk;
 
        external_low_reference = ckil;
        external_high_reference = ckih1;
@@ -5510,6 +5512,20 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
        lp_med_freq = 0;
        lp_audio_freq = 0;
 
+       /* Get current ARM_PODF value */
+       rate = clk_get_rate(&cpu_clk);
+       parent_rate = clk_get_rate(&pll1_sw_clk);
+       cur_arm_podf = parent_rate / rate;
+
+       /* Calculate the ARM_PODF to be applied when the system
+         * enters WAIT state.
+         * The max ARM clk is decided by the ipg_clk and has to
+         * follow the ratio of ARM_CLK:IPG_CLK of 12:5.
+         */
+       ipg_clk_rate = clk_get_rate(&ipg_clk);
+       max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
+       wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
+
        /* Turn OFF all unnecessary PHYs. */
        if (cpu_is_mx6q()) {
                /* Turn off SATA PHY. */

diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 33721a4e212f6168640f52cd94afe9cbf3b09481..9c79f744de991f9b49bcf4337c7363d59cfd1ebd 100755 (executable)
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -3982,6 +3982,8 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
        unsigned long ckih1, unsigned long ckih2)
 {
        int i;
+       u32 parent_rate, rate;
+       unsigned long ipg_clk_rate, max_arm_wait_clk;
 
        external_low_reference = ckil;
        external_high_reference = ckih1;
@@ -4094,6 +4096,20 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
        lp_high_freq = 0;
        lp_med_freq = 0;
 
+       /* Get current ARM_PODF value */
+       rate = clk_get_rate(&cpu_clk);
+       parent_rate = clk_get_rate(&pll1_sw_clk);
+       cur_arm_podf = parent_rate / rate;
+
+       /* Calculate the ARM_PODF to be applied when the system
+         * enters WAIT state.
+         * The max ARM clk is decided by the ipg_clk and has to
+         * follow the ratio of ARM_CLK:IPG_CLK of 12:5.
+         */
+       ipg_clk_rate = clk_get_rate(&ipg_clk);
+       max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
+       wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
+
        return 0;
 
 }

diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index 09940ffd49aaf66a382da645d1550c1efca778a4..75701dc6485a3fb2bd8b11e126bd3c36a5971158 100644 (file)
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -52,7 +52,6 @@ extern unsigned int gpc_wake_irq[4];
 
 static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
 
-int wait_mode_arm_podf;
 volatile unsigned int num_cpu_idle;
 volatile unsigned int num_cpu_idle_lock = 0x0;
 int wait_mode_arm_podf;