ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m...

Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.

Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.

Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.

So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input
of apll.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 7148e7c753979d1869df8829ce8e8cfd1b30bc41..f5dca1ff1d6e222876ea6a59165852a2f0781fb4 100644 (file)
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
 
        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
                compatible = "ti,mux-clock";
-               clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+               clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
                #clock-cells = <0>;
                reg = <0x021c 0x4>;
                ti,bit-shift = <7>;