ENGR00240988: ARM: dts: add gpu nodes for imx6q and imx6dl

It adds gpu nodes for imx6q and imx6dl.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit dfbafe2b0b33 from imx_3.10.y, use macro
 for clock IDs and IRQ trigger type, and add power-domains]

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index edb7414c7e38b3935fc7c3da9aa8383e1c0e6219..2f7d876d979860ffdf4d80af39695bf5538725e7 100644 (file)
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -56,6 +56,26 @@
        };
 
        soc {
+               gpu@00130000 {
+                       compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
+                       reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+                             <0x0 0x0>;
+                       reg-names = "iobase_3d", "iobase_2d",
+                                   "phys_baseaddr";
+                       interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "irq_3d", "irq_2d";
+                       clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
+                                <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                <&clks IMX6QDL_CLK_DUMMY>;
+                       clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
+                                     "gpu2d_clk", "gpu3d_clk",
+                                     "gpu3d_shader_clk";
+                       resets = <&src 0>, <&src 3>;
+                       reset-names = "gpu3d", "gpu2d";
+                       power-domains = <&gpc 1>;
+               };
+
                ocram: sram@00900000 {
                        compatible = "mmio-sram";
                        reg = <0x00900000 0x20000>;

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 5472a4cc790dd9e232957bbd6b51a77f1b1d94e7..880cacf9f20cd7dde306074273d44b56d2851500 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -78,6 +78,27 @@
        };
 
        soc {
+               gpu@00130000 {
+                       compatible = "fsl,imx6q-gpu";
+                       reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+                             <0x02204000 0x4000>, <0x0 0x0>;
+                       reg-names = "iobase_3d", "iobase_2d",
+                                   "iobase_vg", "phys_baseaddr";
+                       interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 10 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "irq_3d", "irq_2d", "irq_vg";
+                       clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>;
+                       clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+                                     "gpu3d_axi_clk", "gpu2d_clk",
+                                     "gpu3d_clk", "gpu3d_shader_clk";
+                       resets = <&src 0>, <&src 3>, <&src 3>;
+                       reset-names = "gpu3d", "gpu2d", "gpuvg";
+                       power-domains = <&gpc 1>;
+               };
+
                ocram: sram@00900000 {
                        compatible = "mmio-sram";
                        reg = <0x00900000 0x40000>;