bool set_irq_mask;
};
-static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
-{
- return container_of(gc, struct crystalcove_gpio, chip);
-}
-
static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
int reg;
static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
{
- struct crystalcove_gpio *cg = to_cg(chip);
+ struct crystalcove_gpio *cg = gpiochip_get_data(chip);
if (gpio > CRYSTALCOVE_VGPIO_NUM)
return 0;
static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
int value)
{
- struct crystalcove_gpio *cg = to_cg(chip);
+ struct crystalcove_gpio *cg = gpiochip_get_data(chip);
if (gpio > CRYSTALCOVE_VGPIO_NUM)
return 0;
static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
- struct crystalcove_gpio *cg = to_cg(chip);
+ struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int ret;
unsigned int val;
static void crystalcove_gpio_set(struct gpio_chip *chip,
unsigned gpio, int value)
{
- struct crystalcove_gpio *cg = to_cg(chip);
+ struct crystalcove_gpio *cg = gpiochip_get_data(chip);
if (gpio > CRYSTALCOVE_VGPIO_NUM)
return;
static int crystalcove_irq_type(struct irq_data *data, unsigned type)
{
- struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
+ struct crystalcove_gpio *cg =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
switch (type) {
case IRQ_TYPE_NONE:
static void crystalcove_bus_lock(struct irq_data *data)
{
- struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
+ struct crystalcove_gpio *cg =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
mutex_lock(&cg->buslock);
}
static void crystalcove_bus_sync_unlock(struct irq_data *data)
{
- struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
+ struct crystalcove_gpio *cg =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
int gpio = data->hwirq;
if (cg->update & UPDATE_IRQ_TYPE)
static void crystalcove_irq_unmask(struct irq_data *data)
{
- struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
+ struct crystalcove_gpio *cg =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
cg->set_irq_mask = false;
cg->update |= UPDATE_IRQ_MASK;
static void crystalcove_irq_mask(struct irq_data *data)
{
- struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
+ struct crystalcove_gpio *cg =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
cg->set_irq_mask = true;
cg->update |= UPDATE_IRQ_MASK;
static void crystalcove_gpio_dbg_show(struct seq_file *s,
struct gpio_chip *chip)
{
- struct crystalcove_gpio *cg = to_cg(chip);
+ struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int gpio, offset;
unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
cg->chip.dbg_show = crystalcove_gpio_dbg_show;
cg->regmap = pmic->regmap;
- retval = gpiochip_add(&cg->chip);
+ retval = gpiochip_add_data(&cg->chip, cg);
if (retval) {
dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
return retval;