[ARM] Kirkwood: add support for L2 cache WB/WT selection

Feroceon L2 cache can work in eighther write through or write back mode
on Kirkwood. Add the option to configure this mode according to Kconfig.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c8516e352d1c2537b06599acbe5f256ec5effe61..85cad05d8c5bf3bc613b9feaa4ac0c0177f3a358 100644 (file)
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -588,9 +588,15 @@ static char * __init kirkwood_id(void)
        }
 }
 
-static int __init is_l2_writethrough(void)
+static void __init kirkwood_l2_init(void)
 {
-       return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH);
+#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
+       writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
+       feroceon_l2_init(1);
+#else
+       writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
+       feroceon_l2_init(0);
+#endif
 }
 
 void __init kirkwood_init(void)
@@ -605,6 +611,6 @@ void __init kirkwood_init(void)
        kirkwood_setup_cpu_mbus();
 
 #ifdef CONFIG_CACHE_FEROCEON_L2
-       feroceon_l2_init(is_l2_writethrough());
+       kirkwood_l2_init();
 #endif
 }

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ed15f876c7254cd02ea86d53b5346cfa4efc67d0..330814d1ee2536e65dc23273ea01d225088688fe 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,14 @@ config CACHE_FEROCEON_L2
        help
          This option enables the Feroceon L2 cache controller.
 
+config CACHE_FEROCEON_L2_WRITETHROUGH
+       bool "Force Feroceon L2 cache write through"
+       depends on CACHE_FEROCEON_L2
+       default n
+       help
+         Say Y here to use the Feroceon L2 cache in writethrough mode.
+         Unless you specifically require this, say N for writeback mode.
+
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index f2e5884c513a05f0b0905a9f5c3ee023a8c702f7..207392f1ce8a15ae0cbf214fe4d818ebceffae17 100644 (file)
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -80,7 +80,8 @@ ENTRY(cpu_feroceon_proc_fin)
        msr     cpsr_c, ip
        bl      feroceon_flush_kern_cache_all
 
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mov     r0, #0
        mcr     p15, 1, r0, c15, c9, 0          @ clean L2
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
@@ -389,7 +390,8 @@ ENTRY(feroceon_range_cache_fns)
 
        .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mov     r2, r0
        mov     r3, r1
 #endif
@@ -397,7 +399,8 @@ ENTRY(cpu_feroceon_dcache_clean_area)
        add     r0, r0, #CACHE_DLINESIZE
        subs    r1, r1, #CACHE_DLINESIZE
        bhi     1b
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
 1:     mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
        add     r2, r2, #CACHE_DLINESIZE
        subs    r3, r3, #CACHE_DLINESIZE
@@ -466,7 +469,8 @@ ENTRY(cpu_feroceon_set_pte_ext)
        str     r2, [r0]                        @ hardware version
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
 #endif
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB