interrupts = <0 112 0>;
clocks = <&clock 471>;
clock-names = "secss";
--- samsung,power-domain = <&g2d_pd>;
+++ };
++++
++++ usbdrd3_0: usb@12000000 {
++++ compatible = "samsung,exynos5250-dwusb3";
++++ clocks = <&clock CLK_USBD300>;
++++ clock-names = "usbdrd30";
++++ #address-cells = <1>;
++++ #size-cells = <1>;
++++ ranges;
++++
++++ dwc3 {
++++ compatible = "snps,dwc3";
++++ reg = <0x12000000 0x10000>;
++++ interrupts = <0 72 0>;
++++ phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
++++ phy-names = "usb2-phy", "usb3-phy";
++++ };
++++ };
++++
++++ usbdrd_phy0: phy@12100000 {
++++ compatible = "samsung,exynos5420-usbdrd-phy";
++++ reg = <0x12100000 0x100>;
++++ clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
++++ clock-names = "phy", "ref";
++++ samsung,pmu-syscon = <&pmu_system_controller>;
++++ #phy-cells = <1>;
++++ };
++++
++++ usbdrd3_1: usb@12400000 {
++++ compatible = "samsung,exynos5250-dwusb3";
++++ clocks = <&clock CLK_USBD301>;
++++ clock-names = "usbdrd30";
++++ #address-cells = <1>;
++++ #size-cells = <1>;
++++ ranges;
++++
++++ dwc3 {
++++ compatible = "snps,dwc3";
++++ reg = <0x12400000 0x10000>;
++++ interrupts = <0 73 0>;
++++ phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
++++ phy-names = "usb2-phy", "usb3-phy";
++++ };
++++ };
++++
++++ usbdrd_phy1: phy@12500000 {
++++ compatible = "samsung,exynos5420-usbdrd-phy";
++++ reg = <0x12500000 0x100>;
++++ clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
++++ clock-names = "phy", "ref";
++++ samsung,pmu-syscon = <&pmu_system_controller>;
++++ #phy-cells = <1>;
+ };
};