drm/i915: Enable eDP DRRS for CHV

This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.

[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()

[Ram]: Rebased on top of previous patch modifications

Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ebb725851998cd2a89bd6ecd3c3912c2526eb49c..2ac93909cfc5315cddcd9e9cd7f0601439364a53 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5879,7 +5879,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
                 * for gen < 8) and if DRRS is supported (to make sure the
                 * registers are not unnecessarily accessed).
                 */
-               if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
+               if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
                        crtc->config->has_drrs) {
                        I915_WRITE(PIPE_DATA_M2(transcoder),
                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4d6e68c52fd9f53a73ba22e625e773beea24a8ac..686c3d5c3769978970e59b6e15b8368f6968a154 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4808,7 +4808,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
                return;
        }
 
-       if (INTEL_INFO(dev)->gen >= 8) {
+       if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
                switch (index) {
                case DRRS_HIGH_RR:
                        intel_dp_set_m_n(intel_crtc, M1_N1);