drm/radeon/kms/r7xx: add workaround for hw issue with HDP flush

commit 812d046915f48236657f02c06d7dc47140e9ceda upstream.

Use of HDP_*_COHERENCY_FLUSH_CNTL can cause a hang in certain
situations.  Add workaround.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e100f69faeec80a0c447ee186774a14ea95620c4..bb3de0158460af019457ded58a15d119e8700cf0 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -869,7 +869,17 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
        u32 tmp;
 
        /* flush hdp cache so updates hit vram */
-       WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+       if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
+               void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+               u32 tmp;
+
+               /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
+                * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
+                */
+               WREG32(HDP_DEBUG1, 0);
+               tmp = readl((void __iomem *)ptr);
+       } else
+               WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 
        WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
        WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
@@ -3512,5 +3522,15 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
  */
 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
 {
-       WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+       /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
+        * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
+        */
+       if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
+               void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+               u32 tmp;
+
+               WREG32(HDP_DEBUG1, 0);
+               tmp = readl((void __iomem *)ptr);
+       } else
+               WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 }

diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 59c1f8793e608df971466a9545ccc32c81e529fd..84bc28e7a3997defcf8def9983131e66fc7736cd 100644 (file)
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -245,6 +245,7 @@
 #define        HDP_NONSURFACE_SIZE                             0x2C0C
 #define HDP_REG_COHERENCY_FLUSH_CNTL                   0x54A0
 #define        HDP_TILING_CONFIG                               0x2F3C
+#define HDP_DEBUG1                                      0x2F34
 
 #define MC_VM_AGP_TOP                                  0x2184
 #define MC_VM_AGP_BOT                                  0x2188

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index b7fd82064922342d420cacb56a7ece8a00964393..1d6fb79de27ec29dd12fcfaf695309f4b349f9fb 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -189,7 +189,10 @@ static void rv770_mc_program(struct radeon_device *rdev)
                WREG32((0x2c20 + j), 0x00000000);
                WREG32((0x2c24 + j), 0x00000000);
        }
-       WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+       /* r7xx hw bug.  Read from HDP_DEBUG1 rather
+        * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
+        */
+       tmp = RREG32(HDP_DEBUG1);
 
        rv515_mc_stop(rdev, &save);
        if (r600_mc_wait_for_idle(rdev)) {

diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 9506f8cb99e0552a295bef5bd60dfba49bfaaee0..6111a022f76c04d72d0319b319ca3f05964778dc 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -128,6 +128,7 @@
 #define        HDP_NONSURFACE_SIZE                             0x2C0C
 #define HDP_REG_COHERENCY_FLUSH_CNTL                   0x54A0
 #define        HDP_TILING_CONFIG                               0x2F3C
+#define HDP_DEBUG1                                      0x2F34
 
 #define MC_SHARED_CHMAP                                                0x2004
 #define                NOOFCHAN_SHIFT                                  12