arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers

There are some requirements about the GIC-400 memory layout and its
mapping if using 64k aligned base addresses like on r8a7795.

See e.g.

http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9

Map the whole memory range instead of only 0x2000. This will fix
the issue that some hypervisors, e.g. Xen, fail to handle the
interrupts correctly.

Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 3285a9286786c48cce2ba1cba1b3f1be3d4d4f2f..de3e799a7bbab91474c457fb65d0ef9daed9eccf 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -157,9 +157,9 @@
                        #address-cells = <0>;
                        interrupt-controller;
                        reg = <0x0 0xf1010000 0 0x1000>,
-                             <0x0 0xf1020000 0 0x2000>,
+                             <0x0 0xf1020000 0 0x20000>,
                              <0x0 0xf1040000 0 0x20000>,
-                             <0x0 0xf1060000 0 0x2000>;
+                             <0x0 0xf1060000 0 0x20000>;
                        interrupts = <GIC_PPI 9
                                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                };