new boards should not use this option.
config SYS_TEXT_BASE
- depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP
+ depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
+ (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE
depends on !EFI_APP
hex "Text Base"
help
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
-ARM MARVELL KIRKWOOD
+ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
M: Prafulla Wadaskar <prafulla@marvell.com>
M: Luka Perkov <luka.perkov@sartura.hr>
+M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
+F: arch/arm/mach-mvebu/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
+ARM ROCKCHIP
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+T: git git://git.denx.de/u-boot-rockchip.git
+F: arch/arm/mach-rockchip/
+
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
# Prohibit date/time macros, which would make the build non-deterministic
KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
-endif
-
-export CONFIG_SYS_TEXT_BASE
-
include scripts/Makefile.extrawarn
# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
-# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU
-# SoC's, the SPL U-Boot returns to the BootROM after it completes
-# the SDRAM setup. The BootROM expects no U-Boot header in the main
-# U-Boot image. So we need to combine SPL and u-boot.bin instead of
-# u-boot.img in this case.
-ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
-u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage)
-else
u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
-endif
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
'Sane' compilers will generate smaller code if
CONFIG_PRE_CON_BUF_SZ is a power of 2
-- Safe printf() functions
- Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
- the printf() functions. These are defined in
- include/vsprintf.h and include snprintf(), vsnprintf() and
- so on. Code size increase is approximately 300-500 bytes.
- If this option is not given then these functions will
- silently discard their buffer size argument - this means
- you are not getting any overflow checking in this case.
-
- Boot Delay: CONFIG_BOOTDELAY - in seconds
Delay before automatically booting the default image;
set to -1 to disable autoboot.
to port U-Boot to your hardware platform. To do this, follow these
steps:
-1. Add a new configuration option for your board to the toplevel
- "boards.cfg" file, using the existing entries as examples.
- Follow the instructions there to keep the boards in order.
-2. Create a new directory to hold your board specific code. Add any
+1. Create a new directory to hold your board specific code. Add any
files you need. In your board directory, you will need at least
- the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
-3. Create a new configuration file "include/configs/<board>.h" for
- your board
+ the "Makefile" and a "<board>.c".
+2. Create a new configuration file "include/configs/<board>.h" for
+ your board.
3. If you're porting U-Boot to a new CPU, then also create a new
directory to hold your CPU specific code. Add any files you need.
4. Run "make <board>_defconfig" with your new name.
}
-static int dev_stor_index(block_dev_desc_t *dd)
-{
- int i, type;
-
- type = dev_stor_type(dd);
- for (i = 0; i < specs[type].max_dev; i++)
- if (dd == get_dev(specs[type].name, i))
- return i;
-
- return (specs[type].max_dev);
-}
-
-
lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
int type;
return 0;
}
- return (dd->block_read(dev_stor_index(dd), start, len, buf));
+ return dd->block_read(dd, start, len, buf);
}
select HAVE_PRIVATE_LIBGCC
select HAVE_GENERIC_BOARD
select SYS_GENERIC_BOARD
+ select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
1:
#endif
- /* Setup stack- and frame-pointers */
+ /* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
- /* Allocate and zero GD, update SP */
+ /* Allocate reserved area from current top of stack */
mov %r0, %sp
- bl board_init_f_mem
-
- /* Update stack- and frame-pointers */
+ bl board_init_f_alloc_reserve
+ /* Set stack below reserved area, adjust frame pointer accordingly */
mov %sp, %r0
mov %fp, %sp
+ /* Initialize reserved area - note: r0 already contains address */
+ bl board_init_f_init_reserve
+
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
j board_init_f
select OF_CONTROL
select OF_SEPARATE
select DM
+ select DM_ETH
select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_OF_CONTROL
+ select SPL_SIMPLE_BUS
config TARGET_DEVKIT3250
bool "Support devkit3250"
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
-config TARGET_STM32F429_DISCOVERY
- bool "Support STM32F429 Discovery"
+config STM32
+ bool "Support STM32"
select CPU_V7M
select DM
select DM_SERIAL
select CPU_V7
select DM
+config TARGET_THUNDERX_88XX
+ bool "Support ThunderX 88xx"
+ select OF_CONTROL
+
endchoice
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
+source "arch/arm/mach-stm32/Kconfig"
+
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
-source "board/Marvell/db-88f6820-gp/Kconfig"
-source "board/Marvell/db-mv784mp-gp/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
+source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
-source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
-machine-$(CONFIG_ARMADA_XP) += mvebu
+machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
+machine-$(CONFIG_STM32) += stm32
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
*/
#include <common.h>
-#include <asm/arch/cpu.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
-#include <dm.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
&clk->u3clk + (uart_id - 3));
}
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata lpc32xx_uart[] = {
+ { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK },
+};
+
+#if defined(CONFIG_LPC32XX_HSUART)
+static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+ { HS_UART1_BASE, },
+ { HS_UART2_BASE, },
+ { HS_UART7_BASE, },
+};
+#endif
+
+U_BOOT_DEVICES(lpc32xx_uarts) = {
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
+#endif
+ { "ns16550_serial", &lpc32xx_uart[0], },
+ { "ns16550_serial", &lpc32xx_uart[1], },
+ { "ns16550_serial", &lpc32xx_uart[2], },
+ { "ns16550_serial", &lpc32xx_uart[3], },
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
+#endif
+};
+#endif
+
void lpc32xx_dma_init(void)
{
/* Enable DMA interface */
omap_die_id(die_id);
- printf("OMAP die ID: %08x%08x%08x%08x", die_id[0], die_id[1], die_id[2],
- die_id[3]);
+ printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1],
+ die_id[2], die_id[3]);
}
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ if (port == 5) {
+ if (state)
+ prcm_apb0_enable(
+ PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+ else
+ prcm_apb0_disable(
+ PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+ return 0;
+ }
+
/* set the apb clock gate for twi */
if (state)
setbits_le32(&ccm->apb2_gate,
/* deassert reset for module */
setbits_le32(&prcm->apb0_reset, flags);
}
+
+void prcm_apb0_disable(u32 flags)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* assert reset for module */
+ clrbits_le32(&prcm->apb0_reset, flags);
+
+ /* close the clock for module */
+ clrbits_le32(&prcm->apb0_gate, flags);
+}
extra-y := start.o
obj-y += cpu.o
-
-obj-$(CONFIG_STM32F1) += stm32f1/
-obj-$(CONFIG_STM32F4) += stm32f4/
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
+obj-y += fwcall.o
obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_SYS_FULL_VA
+static void set_ptl1_entry(u64 index, u64 ptl2_entry)
+{
+ u64 *pgd = (u64 *)gd->arch.tlb_addr;
+ u64 value;
+
+ value = ptl2_entry | PTL1_TYPE_TABLE;
+ pgd[index] = value;
+}
+
+static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs)
+{
+ u64 *pmd = (u64 *)ptl1;
+ u64 value;
+
+ value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
+ value |= memory_attrs;
+ pmd[bfn] = value;
+}
+
+static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
+
+#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
+#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+
+static void setup_pgtables(void)
+{
+ int l1_e, l2_e;
+ unsigned long pmd = 0;
+ unsigned long address;
+
+ /* Setup the PMD pointers */
+ for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
+ gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr +
+ PTL1_ENTRIES * sizeof(u64);
+ gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;
+ gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e],
+ 0x10000UL);
+ }
+
+ /* Setup the page tables */
+ for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) {
+ if (mem_map[pmd].base ==
+ (uintptr_t)l1_e << PTL2_BITS) {
+ set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]);
+
+ for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) {
+ address = mem_map[pmd].base
+ + (uintptr_t)l2_e * BLOCK_SIZE;
+ set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e,
+ address, mem_map[pmd].attrs);
+ }
+
+ pmd++;
+ } else {
+ set_ptl1_entry(l1_e, 0);
+ }
+ }
+}
+
+#else
+
inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
u64 memory_type, u64 attribute)
{
value = (u64)table_addr | PMD_TYPE_TABLE;
page_table[index] = value;
}
+#endif
/* to activate the MMU we need to set up virtual memory */
__weak void mmu_setup(void)
{
+#ifndef CONFIG_SYS_FULL_VA
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
+#endif
int el;
+#ifdef CONFIG_SYS_FULL_VA
+ unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK;
+
+ /* Set up page tables only on BSP */
+ if (coreid == BSP_COREID)
+ setup_pgtables();
+#else
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
set_pgtable_section(page_table, i, i << SECTION_SHIFT,
}
}
+#endif
/* load TTBR0 */
el = current_el();
if (el == 1) {
return NULL;
}
+#ifndef CONFIG_SYS_FULL_VA
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
flush_dcache_range(start, end);
asm volatile("dsb sy");
}
+#endif
+
#else /* CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/system.h>
+
+/*
+ * Issue the hypervisor call
+ *
+ * x0~x7: input arguments
+ * x0~x3: output arguments
+ */
+void hvc_call(struct pt_regs *args)
+{
+ asm volatile(
+ "ldr x0, %0\n"
+ "ldr x1, %1\n"
+ "ldr x2, %2\n"
+ "ldr x3, %3\n"
+ "ldr x4, %4\n"
+ "ldr x5, %5\n"
+ "ldr x6, %6\n"
+ "ldr x7, %7\n"
+ "hvc #0\n"
+ "str x0, %0\n"
+ "str x1, %1\n"
+ "str x2, %2\n"
+ "str x3, %3\n"
+ : "+m" (args->regs[0]), "+m" (args->regs[1]),
+ "+m" (args->regs[2]), "+m" (args->regs[3])
+ : "m" (args->regs[4]), "m" (args->regs[5]),
+ "m" (args->regs[6]), "m" (args->regs[7])
+ : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17");
+}
+
+/*
+ * void smc_call(arg0, arg1...arg7)
+ *
+ * issue the secure monitor call
+ *
+ * x0~x7: input arguments
+ * x0~x3: output arguments
+ */
+
+void smc_call(struct pt_regs *args)
+{
+ asm volatile(
+ "ldr x0, %0\n"
+ "ldr x1, %1\n"
+ "ldr x2, %2\n"
+ "ldr x3, %3\n"
+ "ldr x4, %4\n"
+ "ldr x5, %5\n"
+ "ldr x6, %6\n"
+ "smc #0\n"
+ "str x0, %0\n"
+ "str x1, %1\n"
+ "str x2, %2\n"
+ "str x3, %3\n"
+ : "+m" (args->regs[0]), "+m" (args->regs[1]),
+ "+m" (args->regs[2]), "+m" (args->regs[3])
+ : "m" (args->regs[4]), "m" (args->regs[5]),
+ "m" (args->regs[6])
+ : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17");
+}
.quad __bss_end - _start
reset:
+#ifdef CONFIG_SYS_RESET_SCTRL
+ bl reset_sctrl
+#endif
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
bl _main
+#ifdef CONFIG_SYS_RESET_SCTRL
+reset_sctrl:
+ switch_el x1, 3f, 2f, 1f
+3:
+ mrs x0, sctlr_el3
+ b 0f
+2:
+ mrs x0, sctlr_el2
+ b 0f
+1:
+ mrs x0, sctlr_el1
+
+0:
+ ldr x1, =0xfdfffffa
+ and x0, x0, x1
+
+ switch_el x1, 6f, 5f, 4f
+6:
+ msr sctlr_el3, x0
+ b 7f
+5:
+ msr sctlr_el2, x0
+ b 7f
+4:
+ msr sctlr_el1, x0
+
+7:
+ dsb sy
+ isb
+ b __asm_invalidate_tlb_all
+ ret
+#endif
+
/*-----------------------------------------------------------------------*/
WEAK(apply_core_errata)
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
+ armada-388-clearfog.dtb \
armada-388-gp.dtb \
- armada-xp-gp.dtb
+ armada-xp-gp.dtb \
+ armada-xp-maxbcm.dtb \
+ armada-xp-synology-ds414.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
zynqmp-ep108.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
+dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
serial0 = &uart0;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
+ spi0 = &qspi;
};
cpus {
qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
- reg = <0x47900000 0x100>;
+ reg = <0x47900000 0x100>,
+ <0x30000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "mx66l51235l";
+ compatible = "mx66l51235l","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ u-boot,dm-pre-reloc;
rtc@10300 {
compatible = "marvell,orion-rtc";
--- /dev/null
+/*
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-388.dtsi"
+
+/ {
+ model = "SolidRun Clearfog A1";
+ compatible = "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* 256 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+ ethernet@30000 {
+ mac-address = [00 50 43 02 02 02];
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@34000 {
+ mac-address = [00 50 43 02 02 03];
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+ };
+
+ ethernet@70000 {
+ mac-address = [00 50 43 02 02 01];
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
+
+ i2c@11000 {
+ /* Is there anything on this? */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ /* The MCP3021 is 100kHz clock only */
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ /* Also something at 0x64 */
+ };
+
+ i2c@11100 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ mdio@72004 {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy_dedicated: ethernet-phy@0 {
+ /*
+ * Annoyingly, the marvell phy driver
+ * configures the LED register, rather
+ * than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <0>;
+ };
+ };
+
+ pinctrl@18000 {
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "ref";
+ };
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
+ marvell,pins = "mpp23", "mpp41";
+ marvell,function = "gpio";
+ };
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_sdhci_pins: clearfog-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ };
+
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+ };
+
+ sata@a8000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sata@e0000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ bus-width = <4>;
+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-0 = <&clearfog_sdhci_pins
+ &clearfog_sdhci_cd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <®_3p3v>;
+ wp-inverted;
+ };
+
+ serial@12000 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ serial@12100 {
+ /* mikrobus uart */
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ spi@10680 {
+ /*
+ * We don't seem to have the W25Q32 on the
+ * A1 Rev 2.0 boards, so disable SPI.
+ * CS0: W25Q32 (doesn't appear to be present)
+ * CS1:
+ * CS2: mikrobus
+ */
+ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "w25q32", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+ status = "disabled";
+ };
+ };
+
+ usb3@f8000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+ pcie@2,0 {
+ /* Port 1, Lane 0. CONN3, nearest power. */
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ pcie@3,0 {
+ /* Port 2, Lane 0. CONN2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+ moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
+ sfp,ethernet = <ð2>;
+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ dsa@0 {
+ compatible = "marvell,dsa";
+ dsa,ethernet = <ð1>;
+ dsa,mii-bus = <&mdio>;
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4 0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ };
+
+ port@6 {
+ /* 88E1512 external phy */
+ reg = <6>;
+ label = "lan6";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+};
+
+/*
++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
+MPP18: gpio ? (pca9655 int?)
+MPP19: gpio ? (clkreq?)
+MPP20: gpio ? (sd0 detect)
+MPP21: sd0:cmd x sd0
+MPP22: gpio x mikro int
+MPP23: gpio x switch irq
++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
+MPP24: ua1:rxd x mikro rx
+MPP25: ua1:txd x mikro tx
+MPP26: i2c1:sck x mikro sck
+MPP27: i2c1:sda x mikro sda
+MPP28: sd0:clk x sd0
+MPP29: gpio x mikro rst
+MPP30: ge1:txd2 ? (config)
+MPP31: ge1:txd3 ? (config)
++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
+MPP32: ge1:txctl ? (unused)
+MPP33: gpio ? (pic_com0)
+MPP34: gpio x rear button (pic_com1)
+MPP35: gpio ? (pic_com2)
+MPP36: gpio ? (unused)
+MPP37: sd0:d3 x sd0
+MPP38: sd0:d0 x sd0
+MPP39: sd0:d1 x sd0
++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
+MPP40: sd0:d2 x sd0
+MPP41: gpio x switch reset
+MPP42: gpio ? sw1-1
+MPP43: spi1:cs2 x mikro cs
+MPP44: sata3:prsnt ? (unused)
+MPP45: ref:clk_out0 ?
+MPP46: ref:clk_out1 x switch clk
+MPP47: 4 ? (unused)
++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
+MPP48: tdm:pclk
+MPP49: tdm:fsync
+MPP50: tdm:drx
+MPP51: tdm:dtx
+MPP52: tdm:int
+MPP53: tdm:rst
+MPP54: gpio ? (pwm)
+MPP55: spi1:cs1 x slic
++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
+MPP56: spi1:mosi x mikro mosi
+MPP57: spi1:sck x mikro sck
+MPP58: spi1:miso x mikro miso
+MPP59: spi1:cs0 x w25q32
+*/
stdout-path = "serial0:115200n8";
};
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi0 = &spi0;
+ };
+
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
+ u-boot,dm-pre-reloc;
};
/* GE1 CON15 */
soc {
compatible = "marvell,armada380-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
internal-regs {
compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
stdout-path = "serial0:115200n8";
};
+ aliases {
+ spi0 = &spi0;
+ };
+
memory {
device_type = "memory";
/*
internal-regs {
serial@12000 {
status = "okay";
+ u-boot,dm-pre-reloc;
};
serial@12100 {
status = "okay";
spi0: spi@10600 {
status = "okay";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
--- /dev/null
+/*
+ * Device Tree file for Marvell Armada XP maxbcm board
+ *
+ * Copyright (C) 2013-2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78460.dtsi"
+
+/ {
+ model = "Marvell Armada XP MAXBCM";
+ compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ /*
+ * 8 GB of plug-in RAM modules by default.The amount
+ * of memory available can be changed by the
+ * bootloader according the size of the module
+ * actually plugged. However, memory between
+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
+ * the address range used for I/O (internal registers,
+ * MBus windows).
+ */
+ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
+ <0x00000001 0x00000000 0x00000001 0x00000000>;
+ };
+
+ cpus {
+ pm_pic {
+ ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
+ <&gpio0 17 GPIO_ACTIVE_LOW>,
+ <&gpio0 18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor@0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+ serial@12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+ serial@12100 {
+ status = "okay";
+ };
+ serial@12200 {
+ status = "okay";
+ };
+ serial@12300 {
+ status = "okay";
+ };
+ pinctrl {
+ pinctrl-0 = <&pic_pins>;
+ pinctrl-names = "default";
+ pic_pins: pic-pins-0 {
+ marvell,pins = "mpp16", "mpp17",
+ "mpp18";
+ marvell,function = "gpio";
+ };
+ };
+ sata@a0000 {
+ nr-ports = <2>;
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+ ethernet@74000 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+ ethernet@30000 {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ ethernet@34000 {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };
+
+ /* Front-side USB slot */
+ usb@50000 {
+ status = "okay";
+ };
+
+ /* Back-side USB slot */
+ usb@51000 {
+ status = "okay";
+ };
+
+ spi0: spi@10600 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+ };
+
+ nand@d0000 {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree file for Synology DS414
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+ model = "Synology DS414";
+ compatible = "synology,ds414", "marvell,armadaxp-mv78230",
+ "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * Connected to Marvell 88SX7042 SATA-II controller
+ * handling the four disks.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * Connected to EtronTech EJ168A XHCI controller
+ * providing the two rear USB 3.0 ports.
+ */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+
+ /* RTC is provided by Seiko S-35390A below */
+ rtc@10300 {
+ status = "disabled";
+ };
+
+ spi0: spi@10600 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q064";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+
+ /*
+ * Warning!
+ *
+ * Synology u-boot uses its compiled-in environment
+ * and it seems Synology did not care to change u-boot
+ * default configuration in order to allow saving a
+ * modified environment at a sensible location. So,
+ * if you do a 'saveenv' under u-boot, your modified
+ * environment will be saved at 1MB after the start
+ * of the flash, i.e. in the middle of the uImage.
+ * For that reason, it is strongly advised not to
+ * change the default environment, unless you know
+ * what you are doing.
+ */
+ partition@00000000 { /* u-boot */
+ label = "RedBoot";
+ reg = <0x00000000 0x000d0000>; /* 832KB */
+ };
+
+ partition@000c0000 { /* uImage */
+ label = "zImage";
+ reg = <0x000d0000 0x002d0000>; /* 2880KB */
+ };
+
+ partition@003a0000 { /* uInitramfs */
+ label = "rd.gz";
+ reg = <0x003a0000 0x00430000>; /* 4250KB */
+ };
+
+ partition@007d0000 { /* MAC address and serial number */
+ label = "vendor";
+ reg = <0x007d0000 0x00010000>; /* 64KB */
+ };
+
+ partition@007e0000 {
+ label = "RedBoot config";
+ reg = <0x007e0000 0x00010000>; /* 64KB */
+ };
+
+ partition@007f0000 {
+ label = "FIS directory";
+ reg = <0x007f0000 0x00010000>; /* 64KB */
+ };
+ };
+ };
+
+ i2c@11000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ s35390a: s35390a@30 {
+ compatible = "sii,s35390a";
+ reg = <0x30>;
+ };
+ };
+
+ /* Connected to a header on device's PCB. This
+ * provides the main console for the device.
+ *
+ * Warning: the device may not boot with a 3.3V
+ * USB-serial converter connected when the power
+ * button is pressed. The converter needs to be
+ * connected a few seconds after pressing the
+ * power button. This is possibly due to UART0_TXD
+ * pin being sampled at reset (bit 0 of SAR).
+ */
+ serial@12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ /* Connected to a Microchip PIC16F883 for power control */
+ serial@12100 {
+ status = "okay";
+ };
+
+ poweroff@12100 {
+ compatible = "synology,power-off";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ };
+
+ /* Front USB 2.0 port */
+ usb@50000 {
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
+ &sata3_pwr_pin &sata4_pwr_pin>;
+ pinctrl-names = "default";
+
+ sata1_regulator: sata1-regulator {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA1 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <2000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata2_regulator: sata2-regulator {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "SATA2 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <4000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata3_regulator: sata3-regulator {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "SATA3 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <6000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata4_regulator: sata4-regulator {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "SATA4 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <8000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ sata1_pwr_pin: sata1-pwr-pin {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+
+ sata2_pwr_pin: sata2-pwr-pin {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ sata3_pwr_pin: sata3-pwr-pin {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
+ sata4_pwr_pin: sata4-pwr-pin {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ sata1_pres_pin: sata1-pres-pin {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ sata2_pres_pin: sata2-pres-pin {
+ marvell,pins = "mpp35";
+ marvell,function = "gpio";
+ };
+
+ sata3_pres_pin: sata3-pres-pin {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+
+ sata4_pres_pin: sata4-pres-pin {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit0_pin: syno-id-bit0-pin {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit1_pin: syno-id-bit1-pin {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit2_pin: syno-id-bit2-pin {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ fan1_alarm_pin: fan1-alarm-pin {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+
+ fan2_alarm_pin: fan2-alarm-pin {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
bootrom {
compatible = "marvell,bootrom";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
ethernet1 = &cpsw_emac1;
d_can0 = &dcan1;
d_can1 = &dcan2;
+ spi0 = &qspi;
};
timer {
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
- reg = <0x4b300000 0x100>;
- reg-names = "qspi_base";
+ reg = <0x4b300000 0x100>,
+ <0x5c000000 0x4000000>,
+ <0x4a002558 0x4>;
+ reg-names = "qspi_base", "qspi_mmap",
+ "qspi_ctrlmod";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
--- /dev/null
+/*
+ * Cavium Thunder DTS file - Thunder board description
+ *
+ * Copyright (C) 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ *
+ */
+
+/dts-v1/;
+
+/include/ "thunderx-88xx.dtsi"
+
+/ {
+ model = "Cavium ThunderX CN88XX board";
+ compatible = "cavium,thunder-88xx";
+
+ aliases {
+ serial0 = &uaa0;
+ serial1 = &uaa1;
+ };
+
+ chosen {
+ stdout-path = &uaa0;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x80000000>;
+ };
+};
--- /dev/null
+/*
+ * Cavium Thunder DTS file - Thunder SoC description
+ *
+ * Copyright (C) 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ *
+ */
+
+/ {
+ compatible = "cavium,thunder-88xx";
+ interrupt-parent = <&gic0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x000>;
+ enable-method = "psci";
+ };
+ cpu@001 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x001>;
+ enable-method = "psci";
+ };
+ cpu@002 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x002>;
+ enable-method = "psci";
+ };
+ cpu@003 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x003>;
+ enable-method = "psci";
+ };
+ cpu@004 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x004>;
+ enable-method = "psci";
+ };
+ cpu@005 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x005>;
+ enable-method = "psci";
+ };
+ cpu@006 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x006>;
+ enable-method = "psci";
+ };
+ cpu@007 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x007>;
+ enable-method = "psci";
+ };
+ cpu@008 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x008>;
+ enable-method = "psci";
+ };
+ cpu@009 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x009>;
+ enable-method = "psci";
+ };
+ cpu@00a {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00a>;
+ enable-method = "psci";
+ };
+ cpu@00b {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00b>;
+ enable-method = "psci";
+ };
+ cpu@00c {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00c>;
+ enable-method = "psci";
+ };
+ cpu@00d {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00d>;
+ enable-method = "psci";
+ };
+ cpu@00e {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00e>;
+ enable-method = "psci";
+ };
+ cpu@00f {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00f>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ };
+ cpu@104 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x104>;
+ enable-method = "psci";
+ };
+ cpu@105 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x105>;
+ enable-method = "psci";
+ };
+ cpu@106 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x106>;
+ enable-method = "psci";
+ };
+ cpu@107 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x107>;
+ enable-method = "psci";
+ };
+ cpu@108 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x108>;
+ enable-method = "psci";
+ };
+ cpu@109 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x109>;
+ enable-method = "psci";
+ };
+ cpu@10a {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10a>;
+ enable-method = "psci";
+ };
+ cpu@10b {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10b>;
+ enable-method = "psci";
+ };
+ cpu@10c {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10c>;
+ enable-method = "psci";
+ };
+ cpu@10d {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10d>;
+ enable-method = "psci";
+ };
+ cpu@10e {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10e>;
+ enable-method = "psci";
+ };
+ cpu@10f {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10f>;
+ enable-method = "psci";
+ };
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x201>;
+ enable-method = "psci";
+ };
+ cpu@202 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x202>;
+ enable-method = "psci";
+ };
+ cpu@203 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x203>;
+ enable-method = "psci";
+ };
+ cpu@204 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x204>;
+ enable-method = "psci";
+ };
+ cpu@205 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x205>;
+ enable-method = "psci";
+ };
+ cpu@206 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x206>;
+ enable-method = "psci";
+ };
+ cpu@207 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x207>;
+ enable-method = "psci";
+ };
+ cpu@208 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x208>;
+ enable-method = "psci";
+ };
+ cpu@209 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x209>;
+ enable-method = "psci";
+ };
+ cpu@20a {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20a>;
+ enable-method = "psci";
+ };
+ cpu@20b {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20b>;
+ enable-method = "psci";
+ };
+ cpu@20c {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20c>;
+ enable-method = "psci";
+ };
+ cpu@20d {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20d>;
+ enable-method = "psci";
+ };
+ cpu@20e {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20e>;
+ enable-method = "psci";
+ };
+ cpu@20f {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20f>;
+ enable-method = "psci";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xff01>,
+ <1 14 0xff01>,
+ <1 11 0xff01>,
+ <1 10 0xff01>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ refclk50mhz: refclk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "refclk50mhz";
+ };
+
+ gic0: interrupt-controller@8010,00000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
+ <0x8010 0x80000000 0x0 0x600000>; /* GICR */
+ interrupts = <1 9 0xf04>;
+ };
+
+ uaa0: serial@87e0,24000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x87e0 0x24000000 0x0 0x1000>;
+ interrupts = <1 21 4>;
+ clocks = <&refclk50mhz>;
+ clock-names = "apb_pclk";
+ uboot,skip-init;
+ };
+
+ uaa1: serial@87e0,25000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x87e0 0x25000000 0x0 0x1000>;
+ interrupts = <1 22 4>;
+ clocks = <&refclk50mhz>;
+ clock-names = "apb_pclk";
+ uboot,skip-init;
+ };
+ };
+};
#define CONFIG_NR_DRAM_BANKS_MAX 2
/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
-#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
(CONFIG_SYS_LPC32XX_UART == 7)
+#if !defined(CONFIG_LPC32XX_HSUART)
#define CONFIG_LPC32XX_HSUART
-#else
-#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_NS16550_COM1 UART3_BASE
-#define CONFIG_SYS_NS16550_COM2 UART4_BASE
-#define CONFIG_SYS_NS16550_COM3 UART5_BASE
-#define CONFIG_SYS_NS16550_COM4 UART6_BASE
#endif
-#if defined(CONFIG_LPC32XX_HSUART)
-#if CONFIG_SYS_LPC32XX_UART == 1
-#define HS_UART_BASE HS_UART1_BASE
-#elif CONFIG_SYS_LPC32XX_UART == 2
-#define HS_UART_BASE HS_UART2_BASE
-#else /* CONFIG_SYS_LPC32XX_UART == 7 */
-#define HS_UART_BASE HS_UART7_BASE
+#if !defined(CONFIG_SYS_NS16550_CLK)
+#define CONFIG_SYS_NS16550_CLK 13000000
#endif
+
+#if !defined(CONFIG_LPC32XX_HSUART)
+#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
+#else
+#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _OMAP4_EHCI_H_
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_R8A7740_H__
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7740_H
#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
#define SUN6I_CPUCFG_BASE 0x01f01c00
+#define SUNXI_R_TWI_BASE 0x01f02400
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUN6I_P2WI_BASE 0x01f03400
#define SUN6I_GPL1_R_P2WI_SDA 3
#define SUN8I_GPL_R_RSB 2
+#define SUN8I_H3_GPL_R_TWI 2
+#define SUN8I_A23_GPL_R_TWI 3
#define SUN8I_GPL_R_UART 2
#define SUN9I_GPN_R_RSB 3
#ifdef CONFIG_I2C4_ENABLE
#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE
#endif
+#ifdef CONFIG_R_I2C_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
+#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
#define CONFIG_SYS_TCLK 24000000
};
void prcm_apb0_enable(u32 flags);
+void prcm_apb0_disable(u32 flags);
+
#endif /* __ASSEMBLY__ */
#endif /* _PRCM_H */
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra high-level function multiplexing */
*
* Copyright 2010-2011 NVIDIA Corporation
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA_I2C_H_
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 clock PLL tables */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 clock control functions */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_FLOW_H_
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 high-level function multiplexing */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_GP_PADCTRL_H_
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_GPIO_H_
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_PMU_H_
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_SYSCTR_H_
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_H_
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA124_MC_H_
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 clock PLL tables */
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 clock control functions */
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_FLOW_H_
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 high-level function multiplexing */
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_GP_PADCTRL_H_
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_GPIO_H_
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_PMU_H_
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_H_
* The following definitions are related each other, shoud be
* calculated specifically.
*/
+
+#ifndef CONFIG_SYS_FULL_VA
#define VA_BITS (42) /* 42 bits virtual address */
+#else
+#define VA_BITS CONFIG_SYS_VA_BITS
+#define PTL2_BITS CONFIG_SYS_PTL2_BITS
+#endif
/* PAGE_SHIFT determines the page size */
#undef PAGE_SIZE
#define PAGE_MASK (~(PAGE_SIZE-1))
/*
- * section address mask and size definitions.
+ * block/section address mask and size definitions.
*/
+#ifndef CONFIG_SYS_FULL_VA
#define SECTION_SHIFT 29
#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
#define SECTION_MASK (~(SECTION_SIZE-1))
+#else
+#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT
+#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT)
+#define BLOCK_MASK (~(BLOCK_SIZE-1))
+#endif
+
/***************************************************************/
/*
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
-#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
- (0x04 << (MT_DEVICE_NGNRE*8)) | \
- (0x0c << (MT_DEVICE_GRE*8)) | \
- (0x44 << (MT_NORMAL_NC*8)) | \
- (UL(0xff) << (MT_NORMAL*8)))
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
+ (0x04 << (MT_DEVICE_NGNRE * 8)) | \
+ (0x0c << (MT_DEVICE_GRE * 8)) | \
+ (0x44 << (MT_NORMAL_NC * 8)) | \
+ (UL(0xff) << (MT_NORMAL * 8)))
/*
* Hardware page table definitions.
*
+ */
+
+#ifdef CONFIG_SYS_FULL_VA
+/*
+ * Level 1 descriptor (PGD).
+ */
+
+#define PTL1_TYPE_MASK (3 << 0)
+#define PTL1_TYPE_TABLE (3 << 0)
+
+#define PTL1_TABLE_PXN (1UL << 59)
+#define PTL1_TABLE_XN (1UL << 60)
+#define PTL1_TABLE_AP (1UL << 61)
+#define PTL1_TABLE_NS (1UL << 63)
+
+
+/*
+ * Level 2 descriptor (PMD).
+ */
+
+#define PTL2_TYPE_MASK (3 << 0)
+#define PTL2_TYPE_FAULT (0 << 0)
+#define PTL2_TYPE_TABLE (3 << 0)
+#define PTL2_TYPE_BLOCK (1 << 0)
+
+/*
+ * Block
+ */
+#define PTL2_MEMTYPE(x) ((x) << 2)
+#define PTL2_BLOCK_NON_SHARE (0 << 8)
+#define PTL2_BLOCK_OUTER_SHARE (2 << 8)
+#define PTL2_BLOCK_INNER_SHARE (3 << 8)
+#define PTL2_BLOCK_AF (1 << 10)
+#define PTL2_BLOCK_NG (1 << 11)
+#define PTL2_BLOCK_PXN (UL(1) << 53)
+#define PTL2_BLOCK_UXN (UL(1) << 54)
+
+#else
+/*
* Level 2 descriptor (PMD).
*/
#define PMD_TYPE_MASK (3 << 0)
#define PMD_SECT_PXN (UL(1) << 53)
#define PMD_SECT_UXN (UL(1) << 54)
+#endif
+
/*
* AttrIndx[2:0]
*/
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
+
+#ifndef CONFIG_SYS_FULL_VA
#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
+#else
+#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS
+#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS
+#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS
+#endif
/* PTWs cacheable, inner/outer WBWA and inner shareable */
#define TCR_FLAGS (TCR_TG0_64K | \
#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
#ifndef __ASSEMBLY__
+#ifndef CONFIG_SYS_FULL_VA
void set_pgtable_section(u64 *page_table, u64 index,
u64 section, u64 memory_type,
void set_pgtable_table(u64 *page_table, u64 index,
u64 *table_addr);
+#endif
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
asm volatile("dsb sy");
}
asm volatile("isb");
}
+
+struct mm_region {
+ u64 base;
+ u64 size;
+ u64 attrs;
+};
#endif
+
#endif /* _ASM_ARMV8_MMU_H_ */
static inline void atomic_add(int i, volatile atomic_t *v)
{
- unsigned long flags;
+ unsigned long flags = 0;
local_irq_save(flags);
v->counter += i;
static inline void atomic_sub(int i, volatile atomic_t *v)
{
- unsigned long flags;
+ unsigned long flags = 0;
local_irq_save(flags);
v->counter -= i;
static inline void atomic_inc(volatile atomic_t *v)
{
- unsigned long flags;
+ unsigned long flags = 0;
local_irq_save(flags);
v->counter += 1;
static inline void atomic_dec(volatile atomic_t *v)
{
- unsigned long flags;
+ unsigned long flags = 0;
local_irq_save(flags);
v->counter -= 1;
static inline int atomic_dec_and_test(volatile atomic_t *v)
{
- unsigned long flags;
+ unsigned long flags = 0;
int val;
local_irq_save(flags);
static inline int atomic_add_negative(int i, volatile atomic_t *v)
{
- unsigned long flags;
+ unsigned long flags = 0;
int val;
local_irq_save(flags);
static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
{
- unsigned long flags;
+ unsigned long flags = 0;
local_irq_save(flags);
*addr &= ~mask;
static inline int test_and_set_bit(int nr, volatile void * addr)
{
- unsigned long flags;
+ unsigned long flags = 0;
int out;
local_irq_save(flags);
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
- unsigned long flags;
+ unsigned long flags = 0;
int out;
local_irq_save(flags);
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _OMAP_COMMON_EHCI_H_
unsigned long long timer_reset_value;
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
+#if defined(CONFIG_SYS_FULL_VA)
+ unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES];
+#endif
unsigned long tlb_size;
#endif
#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
+#include <common.h>
+#include <linux/compiler.h>
+
#ifdef CONFIG_ARM64
/*
#define CR_WXN (1 << 19) /* Write Permision Imply XN */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
+#ifndef CONFIG_SYS_FULL_VA
#define PGTABLE_SIZE (0x10000)
+#else
+#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE
+#endif
+
/* 2MB granularity */
#define MMU_SECTION_SHIFT 21
#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
asm volatile("isb");
}
+static inline unsigned long read_mpidr(void)
+{
+ unsigned long val;
+
+ asm volatile("mrs %0, mpidr_el1" : "=r" (val));
+
+ return val;
+}
+
+#define BSP_COREID 0
+
void __asm_flush_dcache_all(void);
void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
void flush_l3_cache(void);
+/*
+ *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void hvc_call(struct pt_regs *args);
+
+/*
+ *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void smc_call(struct pt_regs *args);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
#define CR_AFE (1 << 29) /* Access flag enable */
#define CR_TE (1 << 30) /* Thumb exception enable */
+#ifndef PGTABLE_SIZE
#define PGTABLE_SIZE (4096 * 4)
+#endif
/*
* This is used to ensure the compiler did actually allocate the register we
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#endif
mov r0, sp
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mov sp, r0
+ /* set up gd here, outside any C code */
+ mov r9, r0
+ bl board_init_f_init_reserve
mov r0, #0
bl board_init_f
bl spl_relocate_stack_gd
cmp r0, #0
movne sp, r0
+ movne r9, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
- bl board_init_f_mem
+ mov x0, sp
+ bl board_init_f_alloc_reserve
mov sp, x0
+ /* set up gd here, outside any C code */
+ mov x18, x0
+ bl board_init_f_init_reserve
mov x0, #0
bl board_init_f
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
.globl lowlevel_init
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#define CONFIG_SYS_I2C_SPEED 100000
#endif
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
+
#endif /* _KW_CONFIG_H */
if ARCH_MVEBU
+config ARMADA_38X
+ bool
+
+config ARMADA_XP
+ bool
+
+config MV78230
+ bool
+ select ARMADA_XP
+
+config MV78260
+ bool
+ select ARMADA_XP
+
+config MV78460
+ bool
+ select ARMADA_XP
+
+config DB_88F6820_GP
+ bool
+ select ARMADA_38X
+
choice
prompt "Marvell MVEBU (Armada XP/38x) board select"
optional
+config TARGET_CLEARFOG
+ bool "Support ClearFog"
+ select DB_88F6820_GP
+
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
+ select DB_88F6820_GP
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
+ select MV78460
+
+config TARGET_DS414
+ bool "Support Synology DS414"
+ select MV78230
config TARGET_MAXBCM
bool "Support maxbcm"
+ select MV78460
endchoice
-config SYS_SOC
- default "mvebu"
+config SYS_BOARD
+ default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds414" if TARGET_DS414
+ default "maxbcm" if TARGET_MAXBCM
-config MVEBU_BOOTROM_UARTBOOT
- bool "Use kwboot to boot via BootROM xmodem protocol"
- help
- This option provides support for booting via the Marvell
- xmodem protocol, used by the kwboot tool.
+config SYS_CONFIG_NAME
+ default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds414" if TARGET_DS414
+ default "maxbcm" if TARGET_MAXBCM
- Please don't forget to configure the boot device in
- the board specific kwbimage.cfg file this way:
- BOOT_FROM uart
+config SYS_VENDOR
+ default "Marvell" if TARGET_DB_MV784MP_GP
+ default "Marvell" if TARGET_DB_88F6820_GP
+ default "solidrun" if TARGET_CLEARFOG
+ default "Synology" if TARGET_DS414
+
+config SYS_SOC
+ default "mvebu"
endif
obj-y = cpu.o
obj-y += dram.o
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o
+obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
+obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
endif
obj-y += gpio.o
obj-y += mbus.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/
+obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
+obj-$(CONFIG_ARMADA_XP) += serdes/axp/
endif
/*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <netdev.h>
#include <ahci.h>
#include <linux/mbus.h>
#include <asm/io.h>
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
- if (devid == SOC_MV78460_ID)
+ switch (devid) {
+ case SOC_MV78230_ID:
+ case SOC_MV78260_ID:
+ case SOC_MV78460_ID:
return MVEBU_SOC_AXP;
-
- if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
- devid == SOC_88F6828_ID)
+ case SOC_88F6810_ID:
+ case SOC_88F6820_ID:
+ case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
-
+ }
return MVEBU_SOC_UNKNOWN;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
+
+#if defined(CONFIG_ARMADA_38X)
+/* SAR frequency values for Armada 38x */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0x0, 0x0, 666, 333, 333 },
+ { 0x2, 0x0, 800, 400, 400 },
+ { 0x4, 0x0, 1066, 533, 533 },
+ { 0x6, 0x0, 1200, 600, 600 },
+ { 0x8, 0x0, 1332, 666, 666 },
+ { 0xc, 0x0, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#else
+/* SAR frequency values for Armada XP */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0xa, 0x5, 800, 400, 400 },
+ { 0x1, 0x5, 1066, 533, 533 },
+ { 0x2, 0x5, 1200, 600, 600 },
+ { 0x2, 0x9, 1200, 600, 400 },
+ { 0x3, 0x5, 1333, 667, 667 },
+ { 0x4, 0x5, 1500, 750, 750 },
+ { 0x4, 0x9, 1500, 750, 500 },
+ { 0xb, 0x9, 1600, 800, 533 },
+ { 0xb, 0xa, 1600, 800, 640 },
+ { 0xb, 0x5, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#endif
+
+void get_sar_freq(struct sar_freq_modes *sar_freq)
+{
+ u32 val;
+ u32 freq;
+ int i;
+
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+ freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
+#if !defined(CONFIG_ARMADA_38X)
+ /*
+ * Shift CPU0 clock frequency select bit from SAR2 register
+ * into correct position
+ */
+ freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
+ >> SAR2_CPU_FREQ_OFFS) << 3;
+#endif
+ for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
+ if (sar_freq_tab[i].val == freq) {
+#if defined(CONFIG_ARMADA_38X)
+ *sar_freq = sar_freq_tab[i];
+ return;
+#else
+ int k;
+ u8 ffc;
+
+ ffc = (val & SAR_FFC_FREQ_MASK) >>
+ SAR_FFC_FREQ_OFFS;
+ for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
+ if (sar_freq_tab[k].ffc == ffc) {
+ *sar_freq = sar_freq_tab[k];
+ return;
+ }
+ }
+ i = k;
+#endif
+ }
+ }
+
+ /* SAR value not found, return 0 for frequencies */
+ *sar_freq = sar_freq_tab[i - 1];
+}
+
int print_cpuinfo(void)
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+ struct sar_freq_modes sar_freq;
puts("SoC: ");
switch (devid) {
+ case SOC_MV78230_ID:
+ puts("MV78230-");
+ break;
+ case SOC_MV78260_ID:
+ puts("MV78260-");
+ break;
case SOC_MV78460_ID:
puts("MV78460-");
break;
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
switch (revid) {
case 1:
- puts("A0\n");
+ puts("A0");
break;
case 2:
- puts("B0\n");
+ puts("B0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
switch (revid) {
case MV_88F68XX_Z1_ID:
- puts("Z1\n");
+ puts("Z1");
break;
case MV_88F68XX_A0_ID:
- puts("A0\n");
+ puts("A0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
+ get_sar_freq(&sar_freq);
+ printf(" at %d MHz\n", sar_freq.p_clk);
+
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
/* Power up PLL and PHY channel */
- clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
+ setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
/* Assert VCOCAL_START */
- clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
+ setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
mdelay(1);
*/
for (dev = 0; dev < 3; dev++) {
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
+ setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
/* Assert REG_RCAL_START in channel REG 1 */
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
+ setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
udelay(40);
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
+ clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
}
}
+/*
+ * This function is not called from the SPL U-Boot version
+ */
int arch_cpu_init(void)
{
-#if !defined(CONFIG_SPL_BUILD)
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
* still locked to cache.
*/
mmu_disable();
-#endif
/* Linux expects the internal registers to be at 0xf1000000 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-#if !defined(CONFIG_SPL_BUILD)
/*
* From this stage on, the SoC detection is working. As we have
* configured the internal register base to the value used
* in the macros / defines in the U-Boot header (soc.h).
*/
- /*
- * To fully release / unlock this area from cache, we need
- * to flush all caches and disable the L2 cache.
- */
- icache_disable();
- dcache_disable();
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-#endif
+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+ /*
+ * To fully release / unlock this area from cache, we need
+ * to flush all caches and disable the L2 cache.
+ */
+ icache_disable();
+ dcache_disable();
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
/*
* We need to call mvebu_mbus_probe() before calling
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
- u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
- MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- int i;
-
- /*
- * Only Armada XP supports all 4 ethernet interfaces. A38x has
- * slightly different base addresses for its 2-3 interfaces.
- */
- if (mvebu_soc_family() != MVEBU_SOC_AXP) {
- enet_base[1] = MVEBU_EGIGA2_BASE;
- enet_base[2] = MVEBU_EGIGA3_BASE;
- }
-
- for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
- mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_MV_SDHCI
int board_mmc_init(bd_t *bis)
{
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
- struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
- /* First disable L2 cache - may still be enable from BootROM */
- if (mvebu_soc_family() == MVEBU_SOC_A38X)
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
-#endif
+
+void v7_outer_cache_enable(void)
+{
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ u32 u;
+
+ /* The L2 cache is already disabled at this point */
+
+ /*
+ * For Aurora cache in no outer mode, enable via the CP15
+ * coprocessor broadcasting of cache commands to L2.
+ */
+ asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+ u |= BIT(8); /* Set the FW bit */
+ asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+
+ isb();
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#ifdef CONFIG_SYS_MVEBU_DDR_A38X
-#include "../../../drivers/ddr/marvell/axp/xor.h"
-#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
-#endif
-#ifdef CONFIG_SYS_MVEBU_DDR_AXP
+#if defined(CONFIG_ARCH_MVEBU)
+/* Use common XOR definitions for A3x and AXP */
#include "../../../drivers/ddr/marvell/axp/xor.h"
#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif
mvebu_sdram_bs_set(bank, size);
}
-#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP)
+#if defined(CONFIG_ARCH_MVEBU)
static u32 xor_ctrl_save;
static u32 xor_base_save;
static u32 xor_mask_save;
}
}
+#if defined(CONFIG_ARCH_MVEBU)
void board_add_ram_info(int use_default)
{
+ struct sar_freq_modes sar_freq;
+
+ get_sar_freq(&sar_freq);
+ printf(" (%d MHz, ", sar_freq.d_clk);
+
if (ecc_enabled())
- printf(" (ECC");
+ printf("ECC");
else
- printf(" (ECC not");
+ printf("ECC not");
printf(" enabled)");
}
+#endif
#include <asm/arch/soc.h>
-#if defined(CONFIG_ARMADA_XP)
+#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
+/*
+ * Set this for the common xor register definitions needed in dram.c
+ * for A38x as well here.
+ */
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif
#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#endif
+
/*
* By default kwbimage.cfg from board specific folder is used
* If for some board, different configuration file need to be used,
* SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI 1
-#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_KIRKWOOD_SPI
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS 0
#endif
#endif
#endif
+/* Needed for SPI NOR booting in SPL */
+#define CONFIG_DM_SEQ_ALIAS 1
+
/*
* Ethernet Driver configuration
*/
#define CONFIG_SYS_I2C_SPEED 100000
#endif
-/* Common SPL configuration */
-#ifndef CONFIG_SPL_LDSCRIPT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds"
-#endif
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE 25000000
#endif /* __MVEBU_CONFIG_H */
u32 irq_level;
};
+struct sar_freq_modes {
+ u8 val;
+ u8 ffc; /* Fabric Frequency Configuration */
+ u32 p_clk;
+ u32 nb_clk;
+ u32 d_clk;
+};
+
/* Needed for dynamic (board-specific) mbus configuration */
extern struct mvebu_mbus_state mbus_state;
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+void get_sar_freq(struct sar_freq_modes *sar_freq);
+
/*
* Highspeed SERDES PHY config init, ported from bin_hdr
* to mainline U-Boot
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
+#define SOC_MV78230_ID 0x7823
+#define SOC_MV78260_ID 0x7826
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
#if defined(CONFIG_SPL_BUILD)
/*
- * On A38x switching the regs base address without running from
- * SDRAM doesn't seem to work. So let the SPL still use the
- * default base address and switch to the new address in the
- * main u-boot later.
+ * The SPL U-Boot version still runs with the default
+ * address for the internal registers, configured by
+ * the BootROM. Only the main U-Boot version uses the
+ * new internal register base address, that also is
+ * required for the Linux kernel.
*/
#define SOC_REGS_PHY_BASE 0xd0000000
#else
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
-#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
-#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
-#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
-#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
-#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
#define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
-#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
-#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
+#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
+
+/* BootROM error register (also includes some status infos) */
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS 28
+#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
+#define BOOTROM_ERR_MODE_UART 0x6
+
+#if defined(CONFIG_ARMADA_38X)
+/* SAR values for Armada 38x */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
+
+#define SAR_CPU_FREQ_OFFS 10
+#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 4
+#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 4
+#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x28
+#define BOOT_FROM_SPI 0x32
+#define BOOT_FROM_MMC 0x30
+#define BOOT_FROM_MMC_ALT 0x31
+#else
+/* SAR values for Armada XP */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
+#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
+
+#define SAR_CPU_FREQ_OFFS 21
+#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_FFC_FREQ_OFFS 24
+#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
+#define SAR2_CPU_FREQ_OFFS 20
+#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 5
+#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 5
+#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x2
+#define BOOT_FROM_SPI 0x3
+#endif
+
#endif /* _MVEBU_SOC_H */
#include <config.h>
#include <linux/linkage.h>
-#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
ENDPROC(return_to_bootrom)
-#else
-ENTRY(save_boot_params)
- b save_boot_params_ret
-ENDPROC(save_boot_params)
-#endif
/*
* cache_inv - invalidate Cache line
#if defined(CONFIG_KIRKWOOD)
mbus_state.soc = &kirkwood_mbus_data;
#endif
-#if defined(CONFIG_ARMADA_XP)
+#if defined(CONFIG_ARCH_MVEBU)
mbus_state.soc = &armada_370_xp_mbus_data;
#endif
#define BOARD_ID_BASE 0x0
/* New board ID numbers */
-#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
+#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1)
#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
-#define INVALID_BAORD_ID 0xFFFFFFFF
+#define INVALID_BOARD_ID 0xFFFFFFFF
/* Sample at Reset */
#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
#endif
}
-static u8 board_sat_r_get(u8 dev_num, u8 reg)
+__weak u8 board_sat_r_get(u8 dev_num, u8 reg)
{
u8 data;
u8 *dev;
u32 board_id = board_id_get();
int ret;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
switch (board_id) {
+ case DB_78X60_AMC_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_CUSTOMER_ID:
+ case RD_78460_SERVER_ID:
+ case RD_78460_SERVER_REV2_ID:
+ case DB_78X60_PCAC_ID:
+ return (0x1 << 1) | 1;
+ case FPGA_88F78XX0_ID:
+ case RD_78460_NAS_ID:
+ return (0x0 << 1) | 1;
case DB_784MP_GP_ID:
dev = rd78460gp_twsi_dev;
dev = db88f78xx0rev2_twsi_dev;
break;
- case DB_78X60_PCAC_ID:
- case FPGA_88F78XX0_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_SERVER_REV2_ID:
default:
return 0;
}
/* Read MPP module ID */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
if (ret)
return MV_ERROR;
u16 ctrl_model_get(void)
{
- /* Right now only MV78460 supported */
+ /*
+ * SoC version can't be autodetected. So we need to rely on a define
+ * from the config system here.
+ */
+#if defined(CONFIG_MV78230)
+ return MV_78230_DEV_ID;
+#elif defined(CONFIG_MV78260)
+ return MV_78260_DEV_ID;
+#else
return MV_78460_DEV_ID;
+#endif
}
u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
}
+static int serdes_max_lines_get(void)
+{
+ switch (ctrl_model_get()) {
+ case MV_78230_DEV_ID:
+ return 7;
+ case MV_78260_DEV_ID:
+ return 12;
+ case MV_78460_DEV_ID:
+ return 16;
+ }
+
+ return 0;
+}
+
int serdes_phy_config(void)
{
int status = MV_OK;
u8 device_rev;
u32 rx_high_imp_mode;
u16 ctrl_mode;
- u32 board_id = board_id_get();
u32 pex_if;
u32 pex_if_num;
/*
- * TODO:
- * Right now we only support the MV78460 with 16 serdes lines
+ * Get max. serdes lines count
*/
- max_serdes_lines = 16;
+ max_serdes_lines = serdes_max_lines_get();
if (max_serdes_lines == 0)
return MV_OK;
- switch (board_id) {
- case DB_78X60_AMC_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_CUSTOMER_ID:
- case RD_78460_SERVER_ID:
- case RD_78460_SERVER_REV2_ID:
- case DB_78X60_PCAC_ID:
- satr11 = (0x1 << 1) | 1;
- break;
- case FPGA_88F78XX0_ID:
- case RD_78460_NAS_ID:
- satr11 = (0x0 << 1) | 1;
- break;
- case DB_88F78XX0_BP_REV2_ID:
- case DB_784MP_GP_ID:
- case DB_88F78XX0_BP_ID:
- satr11 = board_sat_r_get(1, 1);
- if ((u8) MV_ERROR == (u8) satr11)
- return MV_ERROR;
- break;
- }
+ satr11 = board_sat_r_get(1, 1);
+ if ((u8) MV_ERROR == (u8) satr11)
+ return MV_ERROR;
board_modules_scan();
memset(addr, 0, sizeof(addr));
pex_if, PEX_DEVICE_AND_VENDOR_ID));
devId &= 0xFFFF;
devId |= ((ctrl_mode << 16) & 0xffff0000);
- DEBUG_INIT_S("Update Device ID PEX");
- DEBUG_INIT_D(pex_if, 1);
- DEBUG_INIT_D(devId, 8);
- DEBUG_INIT_S("\n");
+ DEBUG_INIT_FULL_S("Update Device ID PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_D(devId, 8);
+ DEBUG_INIT_FULL_S("\n");
reg_write(PEX_CFG_DIRECT_ACCESS
(pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
if ((pex_if < 8) &&
(info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
pex_if += 3;
}
- DEBUG_INIT_S("Update PEX Device ID 0x");
- DEBUG_INIT_D(ctrl_mode, 4);
- DEBUG_INIT_S("0\n");
+ DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
+ DEBUG_INIT_FULL_D(ctrl_mode, 4);
+ DEBUG_INIT_FULL_S("0\n");
}
tmp = reg_read(PEX_DBG_STATUS_REG(0));
DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <debug_uart.h>
+#include <fdtdec.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
+static u32 get_boot_device(void)
{
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
- return BOOT_DEVICE_SPI;
-#endif
-#if defined(CONFIG_SPL_MMC_SUPPORT)
- return BOOT_DEVICE_MMC1;
+ u32 val;
+ u32 boot_device;
+
+ /*
+ * First check, if UART boot-mode is active. This can only
+ * be done, via the bootrom error register. Here the
+ * MSB marks if the UART mode is active.
+ */
+ val = readl(CONFIG_BOOTROM_ERR_REG);
+ boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
+ debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+ if (boot_device == BOOTROM_ERR_MODE_UART)
+ return BOOT_DEVICE_UART;
+
+ /*
+ * Now check the SAR register for the strapped boot-device
+ */
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
+ debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+ switch (boot_device) {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case BOOT_FROM_MMC:
+ case BOOT_FROM_MMC_ALT:
+ return BOOT_DEVICE_MMC1;
#endif
+ case BOOT_FROM_UART:
+ return BOOT_DEVICE_UART;
+ case BOOT_FROM_SPI:
+ default:
+ return BOOT_DEVICE_SPI;
+ };
+}
+
+u32 spl_boot_device(void)
+{
+ return get_boot_device();
}
#ifdef CONFIG_SPL_MMC_SUPPORT
void board_init_f(ulong dummy)
{
-#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT
- /*
- * Only call arch_cpu_init() when not returning to the
- * Marvell BootROM, which is done when booting via
- * the xmodem protocol (kwboot tool). Otherwise the
- * internal register will get remapped and the BootROM
- * can't continue to run correctly.
- */
-
- /* Linux expects the internal registers to be at 0xf1000000 */
- arch_cpu_init();
-#endif
+ int ret;
/*
* Pin muxing needs to be done before UART output, since
*/
board_early_init_f();
+ /* Example code showing how to enable the debug UART on MVEBU */
+#ifdef EARLY_UART
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+#endif
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Use special translation offset for SPL */
+ dm_set_translation_offset(0xd0000000 - 0xf1000000);
+
preloader_console_init();
timer_init();
/* Setup DDR */
ddr3_init();
-#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
/*
* Return to the BootROM to continue the Marvell xmodem
* UART boot protocol. As initiated by the kwboot tool.
* need to return to the BootROM to enable this xmodem
* UART download.
*/
- return_to_bootrom();
-#endif
+ if (get_boot_device() == BOOT_DEVICE_UART)
+ return_to_bootrom();
}
* Copyright (C) Marvell International Ltd. and its affiliates
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/arch/soc.h>
-#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG &tmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
-#if defined(CONFIG_ARMADA_XP)
-#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
-#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
-#else
-#define CTCR_ARM_TIMER_25MHZ(cntr) 0
-#endif
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static int init_done __attribute__((section(".data"))) = 0;
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct kwtmr_val tmr[4];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
DECLARE_GLOBAL_DATA_PTR;
-static struct kwtmr_registers *tmr_regs =
- (struct kwtmr_registers *)MVEBU_TIMER_BASE;
-
-static inline ulong read_timer(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
- }
- lastdec = now;
+#define TIMER_LOAD_VAL 0xffffffff
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- uint current;
- ulong delayticks;
-
- current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
- if (current < delayticks) {
- delayticks -= current;
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
- while ((TIMER_LOAD_VAL - delayticks) <
- readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
- } else {
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
- (current - delayticks)) ;
- }
-}
+static int init_done __attribute__((section(".data"))) = 0;
/*
- * init the counter
+ * Timer initialization
*/
int timer_init(void)
{
init_done = 1;
/* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10);
+ writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14);
+#if defined(CONFIG_ARCH_MVEBU)
+ /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */
+ setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11));
+#endif
/* enable timer in auto reload mode */
- clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
- CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
- CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
-
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
+ setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3);
return 0;
}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- *(.vectors)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*_i2c_*)));
- } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \
+ ${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
}
usage() {
- echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
echo "Process QTS-generated headers into U-Boot compatible ones."
echo ""
- echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5',"
- echo " input_dir\t\tDirectory with the QTS project."
- echo " output_dir\t\tDirectory to store the U-Boot compatible headers."
+ echo -e " soc_type\t-\tType of SoC, either 'cyclone5' or 'arria5'."
+ echo -e " input_qts_dir\t-\tDirectory with compiled Quartus project"
+ echo -e "\t\t\t\tand containing the Quartus project file (QPF)."
+ echo -e " input_bsp_dir\t-\tDirectory with generated bsp containing"
+ echo -e "\t\t\t\tthe settings.bsp file."
+ echo -e " output_dir\t-\tDirectory to store the U-Boot compatible"
+ echo -e "\t\t\t\theaders."
echo ""
}
soc="$1"
-in_dir="$2"
-out_dir="$3"
+in_qts_dir="$2"
+in_bsp_dir="$3"
+out_dir="$4"
-if [ "$#" -ne 3 ] ; then
+if [ "$#" -ne 4 ] ; then
usage
exit 1
fi
-if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then
+if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
+ ! -d "${out_dir}" -o -z "${soc}" ] ; then
usage
exit 3
fi
-process_iocsr_config "${soc}" "${in_dir}" "${out_dir}"
-process_pinmux_config "${soc}" "${in_dir}" "${out_dir}"
-process_pll_config "${soc}" "${in_dir}" "${out_dir}"
-process_sdram_config "${soc}" "${in_dir}" "${out_dir}"
+process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
--- /dev/null
+if STM32
+
+config STM32F4
+ bool "stm32f4 family"
+
+config STM32F1
+ bool "stm32f1 family"
+
+source "arch/arm/mach-stm32/stm32f4/Kconfig"
+source "arch/arm/mach-stm32/stm32f1/Kconfig"
+
+endif
#
-# (C) Copyright 2011
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_CPPFLAGS += -mtune=4kc
+obj-$(CONFIG_STM32F1) += stm32f1/
+obj-$(CONFIG_STM32F4) += stm32f4/
--- /dev/null
+if STM32F1
+
+endif
--- /dev/null
+if STM32F4
+
+config TARGET_STM32F429_DISCOVERY
+ bool "STM32F429 Discovery board"
+
+source "board/st/stm32f429-discovery/Kconfig"
+
+endif
/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra cache routines */
/*
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra SoC common clock control functions */
/*
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra vpr routines */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 high-level function multiplexing */
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 high-level function multiplexing */
#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
+static void uniphier_cache_sync(void)
+{
+ writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
+ readl(SSCOPE); /* need a read back to confirm */
+}
+
static void uniphier_cache_maint_all(u32 operation)
{
/* try until the command is successfully set */
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
- writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
- readl(SSCOPE); /* need a read back to confirm */
+ uniphier_cache_sync();
}
void v7_outer_cache_flush_all(void)
*/
start = start & ~(SSC_LINE_SIZE - 1);
- if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
+ size = end - start;
+
+ if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
* If end address is not aligned to cache-line,
* do cache operation for the last cache-line
*/
- size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
+ size = ALIGN(size, SSC_LINE_SIZE);
while (size) {
u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
size -= chunk_size;
}
- writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
- readl(SSCOPE); /* need a read back to confirm */
+ uniphier_cache_sync();
}
void v7_outer_cache_flush_range(u32 start, u32 end)
void v7_outer_cache_inval_range(u32 start, u32 end)
{
+ if (start & (SSC_LINE_SIZE - 1)) {
+ start &= ~(SSC_LINE_SIZE - 1);
+ __uniphier_cache_maint_range(start, SSC_LINE_SIZE,
+ SSCOQM_CM_WB_INV);
+ start += SSC_LINE_SIZE;
+ }
+
+ if (start >= end) {
+ uniphier_cache_sync();
+ return;
+ }
+
+ if (end & (SSC_LINE_SIZE - 1)) {
+ end &= ~(SSC_LINE_SIZE - 1);
+ __uniphier_cache_maint_range(end, SSC_LINE_SIZE,
+ SSCOQM_CM_WB_INV);
+ }
+
+ if (start >= end) {
+ uniphier_cache_sync();
+ return;
+ }
+
uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
}
void v7_outer_cache_enable(void)
{
u32 tmp;
+
+ writel(U32_MAX, SSCLPDAWCR); /* activate all ways */
tmp = readl(SSCC);
tmp |= SSCC_ON;
writel(tmp, SSCC);
writel(0x0000040B, &phy->dcr);
if (freq == 1333) {
writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x1a8363c0, &phy->dtpr[1]);
writel(0x5002c200, &phy->dtpr[2]);
writel(0x00000b51, &phy->mr0);
} else {
writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
+ writel(0x1a878400, &phy->dtpr[1]);
writel(0xa00214f8, &phy->dtpr[2]);
writel(0x00000d71, &phy->mr0);
}
#include "../init.h"
#include "../soc-info.h"
#include "ddrmphy-regs.h"
-
-/* UM registers */
-#define UMC_MBUS0 0x00080004
-#define UMC_MBUS1 0x00081004
-#define UMC_MBUS2 0x00082004
-#define UMC_MBUS3 0x00083004
-
-/* UD registers */
-#define UMC_BITPERPIXELMODE_D0 0x010
-#define UMC_PAIR1DOFF_D0 0x054
-
-/* DC registers */
-#define UMC_INITSET 0x014
-#define UMC_INITSTAT 0x018
-#define UMC_CMDCTLA 0x000
-#define UMC_CMDCTLB 0x004
-#define UMC_SPCCTLA 0x030
-#define UMC_SPCCTLB 0x034
-#define UMC_SPCSETB 0x03c
-#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
-#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
-#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
-#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
-#define UMC_ACSSETA 0x060
-#define UMC_FLOWCTLA 0x400
-#define UMC_FLOWCTLB 0x404
-#define UMC_FLOWCTLC 0x408
-#define UMC_FLOWCTLG 0x508
-#define UMC_FLOWCTLOB0 0x520
-#define UMC_FLOWCTLOB1 0x524
-#define UMC_RDATACTL_D0 0x600
-#define UMC_RDATACTL_RADLTY_SHIFT 4
-#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
-#define UMC_RDATACTL_RAD2LTY_SHIFT 8
-#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
-#define UMC_WDATACTL_D0 0x604
-#define UMC_RDATACTL_D1 0x608
-#define UMC_WDATACTL_D1 0x60c
-#define UMC_DATASET 0x610
-#define UMC_RESPCTL 0x624
-#define UMC_DCCGCTL 0x720
-#define UMC_ERRMASKA 0x958
-#define UMC_ERRMASKB 0x95c
-#define UMC_BSICMAPSET 0x988
-#define UMC_DIOCTLA 0xc00
-#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
-#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
-#define UMC_DFICUPDCTLA 0xc20
+#include "umc-regs.h"
enum dram_freq {
FREQ_1866M,
#define UMC_SPCCTLB 0x00000034
#define UMC_SPCSETA 0x00000038
#define UMC_SPCSETB 0x0000003C
+#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
+#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
+#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
+#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
#define UMC_SPCSETC 0x00000040
#define UMC_SPCSETD 0x00000044
#define UMC_SPCSTATA 0x00000050
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
#define UMC_FLOWCTLG 0x00000508
+#define UMC_FLOWCTLOB0 0x00000520
+#define UMC_FLOWCTLOB1 0x00000524
#define UMC_RDATACTL_D0 0x00000600
+#define UMC_RDATACTL_RADLTY_SHIFT 4
+#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define UMC_RDATACTL_RAD2LTY_SHIFT 8
+#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
#define UMC_WDATACTL_D0 0x00000604
#define UMC_RDATACTL_D1 0x00000608
#define UMC_WDATACTL_D1 0x0000060C
#define UMC_DATASET 0x00000610
+#define UMC_RESPCTL 0x00000624
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
+#define UMC_ERRMASKA 0x00000958
+#define UMC_ERRMASKB 0x0000095c
+#define UMC_BSICMAPSET 0x00000988
#define UMC_DIOCTLA 0x00000C00
+#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
+#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
#define UMC_DFICUPDCTLA 0x00000C20
+/* UM registers */
+#define UMC_MBUS0 0x00080004
+#define UMC_MBUS1 0x00081004
+#define UMC_MBUS2 0x00082004
+#define UMC_MBUS3 0x00083004
+
+/* UD registers */
+#define UMC_BITPERPIXELMODE_D0 0x010
+#define UMC_PAIR1DOFF_D0 0x054
+
#ifndef __ASSEMBLY__
#include <linux/types.h>
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = dram.o
-obj-y += gpio.o
-obj-$(CONFIG_ARMADA_XP) += mbus.o
-obj-y += timer.o
-
-obj-y += serdes/
#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
-#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
+#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
/* copy 4 boot pages to dram as soon as possible */
/* each page is 996 bytes (1056 total with 60 ECC bytes */
move.l #0x00000000, %a1 /* src */
- move.l #TEXT_BASE, %a2 /* dst */
+ move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
move.l #0x3E0, %d0 /* sz in long */
asm_boot_nand_copy:
move.l #4, %d2 /* start at 4 */
move.l #0xFC0FFF04, %a0 /* cmd2 */
move.l #0xFC0FFF0C, %a1 /* rar */
- move.l #(TEXT_BASE + 0xF80), %a2 /* dst */
+ move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2 /* dst */
asm_nand_read:
move.l #0x11000000, %d0 /* rar */
bgt asm_nand_read
/* jump to memory and execute */
- move.l #(TEXT_BASE + 0x400), %a0
+ move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
jmp (%a0)
#endif /* CONFIG_SYS_NAND_BOOT */
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_I2C_H_
addi r8, r0, __end
mts rslr, r8
- /* TODO: Redo this code to call board_init_f_mem() */
+ /* TODO: Redo this code to call board_init_f_*() */
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
mts rshr, r1
ori r12, r12, 0x1a0
mts rmsr, r12
- /* TODO: Redo this code to call board_init_f_mem() */
+ /* TODO: Redo this code to call board_init_f_*() */
clear_bss:
/* clear BSS segments */
addi r5, r0, __bss_start
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SWAP_IO_SPACE
+ select MIPS_L1_CACHE_SHIFT_6
config TARGET_VCT
bool "Support vct"
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select MIPS_TUNE_4KC
config TARGET_PB1X00
bool "Support pb1x00"
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
-
+ select MIPS_TUNE_4KC
endchoice
bool
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+config MIPS_TUNE_4KC
+ bool
+
+config MIPS_TUNE_14KC
+ bool
+
+config MIPS_TUNE_24KC
+ bool
+
config 32BIT
bool
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config MIPS_L1_CACHE_SHIFT_4
+ bool
+
+config MIPS_L1_CACHE_SHIFT_5
+ bool
+
+config MIPS_L1_CACHE_SHIFT_6
+ bool
+
+config MIPS_L1_CACHE_SHIFT_7
+ bool
+
+config MIPS_L1_CACHE_SHIFT
+ int
+ default "7" if MIPS_L1_CACHE_SHIFT_7
+ default "6" if MIPS_L1_CACHE_SHIFT_6
+ default "5" if MIPS_L1_CACHE_SHIFT_5
+ default "4" if MIPS_L1_CACHE_SHIFT_4
+ default "5"
+
endif
endmenu
libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
-libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+machine-$(CONFIG_SOC_AU1X00) += au1x00
+
+machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
+libs-y += $(machdirs)
+
+PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+
+# Optimize for MIPS architectures
+arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
+arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
+arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+
+# Allow extra optimization for specific CPUs/SoCs
+tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
+tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
+tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+
+# Include default header files
+cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
+
+PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y)
OBJCOPYFLAGS += -O $(64bit-bfd)
endif
-cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
-cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
-cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
-cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
-PLATFORM_CPPFLAGS += $(cpuflags-y)
-
PLATFORM_CPPFLAGS += -D__MIPS__
#
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
+ifdef CONFIG_SPL_BUILD
+PF_ABICALLS := -mno-abicalls
+PF_PIC := -fno-pic
+PF_PIE :=
+else
+PF_ABICALLS := -mabicalls
+PF_PIC := -fpic
+PF_PIE := -pie
+PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding
+PF_OBJCOPY += -j .dtb.init.rodata
+endif
+
+PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC)
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections -pie
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding
+LDFLAGS_FINAL += --gc-sections $(PF_PIE)
+OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY)
.set noreorder
- .globl _start
- .text
-_start:
+ENTRY(_start)
/* U-boot entry point */
b reset
nop
jr t9
move ra, zero
+ END(_start)
+
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* a1 = gd
* a2 = destination address
*/
- .globl relocate_code
- .ent relocate_code
-relocate_code:
+ENTRY(relocate_code)
move sp, a0 # set new stack pointer
move fp, sp
jr t9
move ra, zero
- .end relocate_code
+ END(relocate_code)
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+dtb-y +=
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+../../../../include/dt-bindings
\ No newline at end of file
--- /dev/null
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ };
+
+ aliases {
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+};
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
+#include <spaces.h>
+
/*
* Configure language
*/
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
- _CONST64_(0x000000ffffffffff))
+ _CONST64_(0x0000ffffffffffff))
#ifdef CONFIG_64BIT
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
* Not used for the kernel but here seems to be the right place.
*/
#ifdef __PIC__
-#define CPRESTORE(register) \
+#define CPRESTORE(register) \
.cprestore register
-#define CPADD(register) \
+#define CPADD(register) \
.cpadd register
-#define CPLOAD(register) \
- .cpload register
+#define CPLOAD(register) \
+ .cpload register
#else
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
+#define ENTRY(symbol) \
+ .globl symbol; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
+symbol:
+
/*
* LEAF - declare leaf routine
*/
-#define LEAF(symbol) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define LEAF(symbol) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
+ .section .text.symbol, "x"; \
symbol: .frame sp, 0, ra
/*
* NESTED - declare nested routine entry point
*/
-#define NESTED(symbol, framesize, rpc) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define NESTED(symbol, framesize, rpc) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
+ .section .text.symbol, "x"; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
-#define END(function) \
- .end function; \
+#define END(function) \
+ .end function; \
.size function, .-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
- .globl symbol; \
+ .globl symbol; \
symbol:
/*
/*
* ABS - export absolute symbol
*/
-#define ABS(symbol,value) \
- .globl symbol; \
+#define ABS(symbol,value) \
+ .globl symbol; \
symbol = value
-#define PANIC(msg) \
+#define PANIC(msg) \
.set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal panic; \
-9: b 9b; \
+ .set reorder; \
+ PTR_LA a0, 8f; \
+ jal panic; \
+9: b 9b; \
.set pop; \
TEXT(msg)
* Print formatted string
*/
#ifdef CONFIG_PRINTK
-#define PRINT(string) \
+#define PRINT(string) \
.set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal printk; \
+ .set reorder; \
+ PTR_LA a0, 8f; \
+ jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#endif
-#define TEXT(msg) \
+#define TEXT(msg) \
.pushsection .data; \
-8: .asciiz msg; \
+8: .asciiz msg; \
.popsection;
/*
* Build text tables
*/
-#define TTABLE(string) \
+#define TTABLE(string) \
.pushsection .text; \
- .word 1f; \
+ .word 1f; \
.popsection \
.pushsection .data; \
-1: .asciiz string; \
+1: .asciiz string; \
.popsection
/*
*/
#ifdef CONFIG_CPU_HAS_PREFETCH
-#define PREF(hint,addr) \
+#define PREF(hint, addr) \
.set push; \
- .set mips4; \
+ .set arch=r5000; \
pref hint, addr; \
.set pop
-#define PREFX(hint,addr) \
+#define PREFE(hint, addr) \
+ .set push; \
+ .set mips0; \
+ .set eva; \
+ prefe hint, addr; \
+ .set pop
+
+#define PREFX(hint, addr) \
.set push; \
- .set mips4; \
+ .set arch=r5000; \
prefx hint, addr; \
.set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint, addr)
+#define PREFE(hint, addr)
#define PREFX(hint, addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
.set push; \
.set reorder; \
- beqz rt, 9f; \
- move rd, rs; \
+ beqz rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
.set push; \
.set reorder; \
- bnez rt, 9f; \
- move rd, rs; \
+ bnez rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
.set push; \
.set noreorder; \
- bnezl rt, 9f; \
- move rd, rs; \
+ bnezl rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
.set push; \
.set noreorder; \
- beqzl rt, 9f; \
- move rd, rs; \
+ beqzl rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
movn rd, rs, rt
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
movz rd, rs, rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
+#define LONG_SP swp
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
+#define LONG_SP sdp
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org)
* Copyright (c) 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
#ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__
-/*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 128
-#endif
+#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
#endif /* __MIPS_CACHE_H__ */
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
/*
* Cache operations for the cache instruction.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
--- /dev/null
+/*
+ * const.h: Macros for dealing with constants.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code. Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally. We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define __AC(X,Y) (X##Y)
+#define _AC(X,Y) __AC(X,Y)
+#define _AT(T,X) ((T)(X))
+#endif
+
+#define _BITUL(x) (_AC(1,UL) << (x))
+#define _BITULL(x) (_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */
--- /dev/null
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <cpu-feature-overrides.h>
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 1
+# endif
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
--- /dev/null
+#include <asm-generic/gpio.h>
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 FSMLabs, Inc.
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
+ * Author: Maciej W. Rozycki <macro@mips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#if 0
-#include <linux/pagemap.h>
-#endif
+#include <linux/compiler.h>
+#include <linux/types.h>
+
#include <asm/addrspace.h>
#include <asm/byteorder.h>
+#include <asm/cpu-features.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+#include <asm/string.h>
+
+#include <ioremap.h>
+#include <mangle-port.h>
+#include <spaces.h>
/*
* Slowdown I/O port space accesses for antique hardware.
#undef CONF_SLOWDOWN_IO
/*
- * Sane hardware offers swapping of I/O space accesses in hardware; less
- * sane hardware forces software to fiddle with this ...
+ * Raw operations are never swapped in software. OTOH values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware. An example use would be for flash memory that's used for
+ * execute in place.
*/
-#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
+# define __raw_ioswabb(a, x) (x)
+# define __raw_ioswabw(a, x) (x)
+# define __raw_ioswabl(a, x) (x)
+# define __raw_ioswabq(a, x) (x)
+# define ____raw_ioswabq(a, x) (x)
-#define __ioswab8(x) (x)
-#define __ioswab16(x) swab16(x)
-#define __ioswab32(x) swab32(x)
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
-#else
-
-#define __ioswab8(x) (x)
-#define __ioswab16(x) (x)
-#define __ioswab32(x) (x)
-
-#endif
-
-/*
- * This file contains the definitions for the MIPS counterpart of the
- * x86 in/out instructions. This heap of macros and C results in much
- * better code than the approach of doing it in plain C. The macros
- * result in code that is to fast for certain hardware. On the other
- * side the performance of the string functions should be improved for
- * sake of certain devices like EIDE disks that do highspeed polled I/O.
- *
- * Ralf
- *
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
+#define IO_SPACE_LIMIT 0xffff
/*
* On MIPS I/O ports are memory mapped, so we access them using normal
static inline void set_io_port_base(unsigned long base)
{
* (unsigned long *) &mips_io_port_base = base;
+ barrier();
}
/*
#endif
/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/MIPS mapping
+ * virt_to_phys - map virtual addresses to physical
+ * @address: address to remap
+ *
+ * The returned physical address is the physical (CPU) mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses directly mapped or allocated via kmalloc.
+ *
+ * This function does not give bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
*/
-static inline phys_addr_t virt_to_phys(volatile void * address)
+static inline unsigned long virt_to_phys(volatile const void *address)
{
-#ifndef CONFIG_64BIT
- return CPHYSADDR(address);
+ unsigned long addr = (unsigned long)address;
+
+ /* this corresponds to kernel implementation of __pa() */
+#ifdef CONFIG_64BIT
+ if (addr < CKSEG0)
+ return XPHYSADDR(addr);
+
+ return CPHYSADDR(addr);
#else
- return XPHYSADDR(address);
+ return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
}
-static inline void * phys_to_virt(unsigned long address)
+/*
+ * phys_to_virt - map physical address to virtual
+ * @address: address to remap
+ *
+ * The returned virtual address is a current CPU mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses that have a kernel mapping
+ *
+ * This function does not handle bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+static inline void *phys_to_virt(unsigned long address)
{
-#ifndef CONFIG_64BIT
- return (void *)KSEG0ADDR(address);
-#else
- return (void *)CKSEG0ADDR(address);
-#endif
+ return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}
/*
- * IO bus memory addresses are also 1:1 with the physical address
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
*/
-static inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long isa_virt_to_bus(volatile void *address)
{
-#ifndef CONFIG_64BIT
- return CPHYSADDR(address);
-#else
- return XPHYSADDR(address);
-#endif
+ return (unsigned long)address - PAGE_OFFSET;
}
-static inline void * bus_to_virt(unsigned long address)
+static inline void *isa_bus_to_virt(unsigned long address)
{
-#ifndef CONFIG_64BIT
- return (void *)KSEG0ADDR(address);
-#else
- return (void *)CKSEG0ADDR(address);
-#endif
+ return (void *)(address + PAGE_OFFSET);
}
+#define isa_page_to_bus page_to_phys
+
/*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
*/
-extern unsigned long isa_slot_offset;
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
-extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-
-#if 0
-static inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
{
- return __ioremap(offset, size, _CACHE_UNCACHED);
-}
+ void __iomem *addr;
+ phys_addr_t phys_addr;
-static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
-{
- return __ioremap(offset, size, _CACHE_UNCACHED);
-}
+ addr = plat_ioremap(offset, size, flags);
+ if (addr)
+ return addr;
-extern void iounmap(void *addr);
-#endif
+ phys_addr = fixup_bigphys_addr(offset, size);
+ return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
+}
/*
- * XXX We need system specific versions of these to handle EISA address bits
- * 24-31 on SNI.
- * XXX more SNI hacks.
+ * ioremap - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
*/
-#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
-#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
-#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
-#define readb(addr) __raw_readb((addr))
-#define readw(addr) __ioswab16(__raw_readw((addr)))
-#define readl(addr) __ioswab32(__raw_readl((addr)))
-
-#define __raw_writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
-#define __raw_writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
-#define __raw_writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
-#define writeb(b, addr) __raw_writeb((b), (addr))
-#define writew(b, addr) __raw_writew(__ioswab16(b), (addr))
-#define writel(b, addr) __raw_writel(__ioswab32(b), (addr))
-
-#define memset_io(a,b,c) memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-
-/* END SNI HACKS ... */
+#define ioremap(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
+ * ioremap_nocache - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * on the CPU as well as honouring existing caching rules from things like
+ * the PCI bus. Note that there are other caches and buffers on many
+ * busses. In particular driver authors should read up on PCI writes
+ *
+ * It's useful if some control registers are in such an area and
+ * write combining or read caching is not desirable:
*/
-#define __ISA_IO_base ((char *)(PAGE_OFFSET))
+#define ioremap_nocache(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+#define ioremap_uc ioremap_nocache
-#define isa_readb(a) readb(a)
-#define isa_readw(a) readw(a)
-#define isa_readl(a) readl(a)
-#define isa_writeb(b,a) writeb(b,a)
-#define isa_writew(w,a) writew(w,a)
-#define isa_writel(l,a) writel(l,a)
-
-#define isa_memset_io(a,b,c) memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
+/*
+ * ioremap_cachable - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU. Also enables full write-combining. Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size) \
+ __ioremap_mode((offset), (size), _page_cachable_default)
/*
- * We don't have csum_partial_copy_fromio() yet, so we cheat here and
- * just copy it. The net code will then do the checksum later.
+ * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
+ * requests a cachable mapping, ioremap_uncached_accelerated requests a
+ * mapping using the uncached accelerated mode which isn't supported on
+ * all processors.
*/
-#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
-#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
+#define ioremap_cacheable_cow(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
-static inline int check_signature(unsigned long io_addr,
- const unsigned char *signature, int length)
+static inline void iounmap(const volatile void __iomem *addr)
{
- int retval = 0;
- do {
- if (readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
+ plat_iounmap(addr);
}
-#define isa_check_signature(io, s, l) check_signature(i,s,l)
-/*
- * Talk about misusing macros..
- */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define war_octeon_io_reorder_wmb() wmb()
+#else
+#define war_octeon_io_reorder_wmb() do { } while (0)
+#endif
-#define __OUT1(s) \
-static inline void __out##s(unsigned int value, unsigned int port) {
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
+ \
+static inline void pfx##write##bwlq(type val, \
+ volatile void __iomem *mem) \
+{ \
+ volatile type *__mem; \
+ type __val; \
+ \
+ war_octeon_io_reorder_wmb(); \
+ \
+ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
+ \
+ __val = pfx##ioswab##bwlq(__mem, val); \
+ \
+ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+ *__mem = __val; \
+ else if (cpu_has_64bits) { \
+ type __tmp; \
+ \
+ __asm__ __volatile__( \
+ ".set arch=r4000" "\t\t# __writeq""\n\t" \
+ "dsll32 %L0, %L0, 0" "\n\t" \
+ "dsrl32 %L0, %L0, 0" "\n\t" \
+ "dsll32 %M0, %M0, 0" "\n\t" \
+ "or %L0, %L0, %M0" "\n\t" \
+ "sd %L0, %2" "\n\t" \
+ ".set mips0" "\n" \
+ : "=r" (__tmp) \
+ : "0" (__val), "m" (*__mem)); \
+ } else \
+ BUG(); \
+} \
+ \
+static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
+{ \
+ volatile type *__mem; \
+ type __val; \
+ \
+ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
+ \
+ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+ __val = *__mem; \
+ else if (cpu_has_64bits) { \
+ __asm__ __volatile__( \
+ ".set arch=r4000" "\t\t# __readq" "\n\t" \
+ "ld %L0, %1" "\n\t" \
+ "dsra32 %M0, %L0, 0" "\n\t" \
+ "sll %L0, %L0, 0" "\n\t" \
+ ".set mips0" "\n" \
+ : "=r" (__val) \
+ : "m" (*__mem)); \
+ } else { \
+ __val = 0; \
+ BUG(); \
+ } \
+ \
+ return pfx##ioswab##bwlq(__mem, __val); \
+}
-#define __OUT2(m) \
-__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
+ \
+static inline void pfx##out##bwlq##p(type val, unsigned long port) \
+{ \
+ volatile type *__addr; \
+ type __val; \
+ \
+ war_octeon_io_reorder_wmb(); \
+ \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ \
+ __val = pfx##ioswab##bwlq(__addr, val); \
+ \
+ /* Really, we want this to be atomic */ \
+ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
+ \
+ *__addr = __val; \
+ slow; \
+} \
+ \
+static inline type pfx##in##bwlq##p(unsigned long port) \
+{ \
+ volatile type *__addr; \
+ type __val; \
+ \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ \
+ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
+ \
+ __val = *__addr; \
+ slow; \
+ \
+ return pfx##ioswab##bwlq(__addr, __val); \
+}
-#define __OUT(m,s,w) \
-__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
-__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
-__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
- SLOW_DOWN_IO; } \
-__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
- SLOW_DOWN_IO; }
+#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
+ \
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
+
+#define BUILDIO_MEM(bwlq, type) \
+ \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
+__BUILD_MEMORY_PFX(, bwlq, type) \
+__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
+
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+
+#define BUILDIO_IOPORT(bwlq, type) \
+ __BUILD_IOPORT_PFX(, bwlq, type) \
+ __BUILD_IOPORT_PFX(__mem_, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
-#define __IN1(t,s) \
-static inline t __in##s(unsigned int port) { t _v;
+#define __BUILDIO(bwlq, type) \
+ \
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
+
+__BUILDIO(q, u64)
+
+#define readb_relaxed readb
+#define readw_relaxed readw
+#define readl_relaxed readl
+#define readq_relaxed readq
+
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
+#define writeq_relaxed writeq
+
+#define readb_be(addr) \
+ __raw_readb((__force unsigned *)(addr))
+#define readw_be(addr) \
+ be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr) \
+ be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr) \
+ be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr) \
+ __raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr) \
+ __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr) \
+ __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr) \
+ __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
/*
- * Required nops will be inserted by the assembler
+ * Some code tests for these symbols
*/
-#define __IN2(m) \
-__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
-
-#define __IN(t,m,s,w) \
-__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
-__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
-__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
-__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
-
-#define __INS1(s) \
-static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-
-#define __INS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,%4(%5)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,(%0)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), \
- "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__INS1(s##c) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), \
- "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-#define __OUTS1(s) \
-static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,(%0)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,%4(%5)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__OUTS1(s##c) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-__IN(unsigned char,b,b,8)
-__IN(unsigned short,h,w,16)
-__IN(unsigned int,w,l,32)
-
-__OUT(b,b,8)
-__OUT(h,w,16)
-__OUT(w,l,32)
-
-__INS(b,b,1)
-__INS(h,w,2)
-__INS(w,l,4)
-
-__OUTS(b,b,1)
-__OUTS(h,w,2)
-__OUTS(w,l,4)
+#define readq readq
+#define writeq writeq
+
+#define __BUILD_MEMORY_STRING(bwlq, type) \
+ \
+static inline void writes##bwlq(volatile void __iomem *mem, \
+ const void *addr, unsigned int count) \
+{ \
+ const volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ __mem_write##bwlq(*__addr, mem); \
+ __addr++; \
+ } \
+} \
+ \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
+ unsigned int count) \
+{ \
+ volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ *__addr = __mem_read##bwlq(mem); \
+ __addr++; \
+ } \
+}
+#define __BUILD_IOPORT_STRING(bwlq, type) \
+ \
+static inline void outs##bwlq(unsigned long port, const void *addr, \
+ unsigned int count) \
+{ \
+ const volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ __mem_out##bwlq(*__addr, port); \
+ __addr++; \
+ } \
+} \
+ \
+static inline void ins##bwlq(unsigned long port, void *addr, \
+ unsigned int count) \
+{ \
+ volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ *__addr = __mem_in##bwlq(port); \
+ __addr++; \
+ } \
+}
-/*
- * Note that due to the way __builtin_constant_p() works, you
- * - can't use it inside an inline function (it will never be true)
- * - you don't have to worry about side effects within the __builtin..
- */
-#define outb(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc((val),(port)) : \
- __outb((val),(port)))
-
-#define inb(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc(port) : \
- __inb(port))
-
-#define outb_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc_p((val),(port)) : \
- __outb_p((val),(port)))
-
-#define inb_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc_p(port) : \
- __inb_p(port))
-
-#define outw(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc((val),(port)) : \
- __outw((val),(port)))
-
-#define inw(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc(port) : \
- __inw(port))
-
-#define outw_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc_p((val),(port)) : \
- __outw_p((val),(port)))
-
-#define inw_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc_p(port) : \
- __inw_p(port))
-
-#define outl(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc((val),(port)) : \
- __outl((val),(port)))
-
-#define inl(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc(port) : \
- __inl(port))
-
-#define outl_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc_p((val),(port)) : \
- __outl_p((val),(port)))
-
-#define inl_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc_p(port) : \
- __inl_p(port))
-
-
-#define outsb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outsbc((port),(addr),(count)) : \
- __outsb ((port),(addr),(count)))
-
-#define insb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __insbc((port),(addr),(count)) : \
- __insb((port),(addr),(count)))
-
-#define outsw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outswc((port),(addr),(count)) : \
- __outsw ((port),(addr),(count)))
-
-#define insw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inswc((port),(addr),(count)) : \
- __insw((port),(addr),(count)))
-
-#define outsl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outslc((port),(addr),(count)) : \
- __outsl ((port),(addr),(count)))
-
-#define insl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inslc((port),(addr),(count)) : \
- __insl((port),(addr),(count)))
+#define BUILDSTRING(bwlq, type) \
+ \
+__BUILD_MEMORY_STRING(bwlq, type) \
+__BUILD_IOPORT_STRING(bwlq, type)
-#define IO_SPACE_LIMIT 0xffff
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
+BUILDSTRING(q, u64)
+#endif
-/*
- * The caches on some architectures aren't dma-coherent and have need to
- * handle this in software. There are three types of operations that
- * can be applied to dma buffers.
- *
- * - dma_cache_wback_inv(start, size) makes caches and coherent by
- * writing the content of the caches back to memory, if necessary.
- * The function also invalidates the affected part of the caches as
- * necessary before DMA transfers from outside to memory.
- * - dma_cache_wback(start, size) makes caches and coherent by
- * writing the content of the caches back to memory, if necessary.
- * The function also invalidates the affected part of the caches as
- * necessary before DMA transfers from outside to memory.
- * - dma_cache_inv(start, size) invalidates the affected parts of the
- * caches. Dirty lines of the caches may be written back or simply
- * be discarded. This operation is necessary before dma operations
- * to the memory.
- */
-extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
-#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
-#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define mmiowb() wmb()
+#else
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+#endif
-static inline void sync(void)
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+ memset((void __force *)addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+ memcpy(dst, (void __force *)src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
+ memcpy((void __force *)dst, src, count);
}
/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
+ */
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
+
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+
+/*
+ * U-Boot specific
*/
-#define MAP_NOCACHE (0)
+#define sync() mmiowb()
+
+#define MAP_NOCACHE (1)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+ if (flags == MAP_NOCACHE)
+ return ioremap(paddr, len);
+
return (void *)paddr;
}
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
+}
+#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
}
+#define __BUILD_SETBITS(bwlq, sfx, end, type) \
+ \
+static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
+ type clr, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+__BUILD_CLRBITS(bwlq, sfx, end, type) \
+__BUILD_SETBITS(bwlq, sfx, end, type) \
+__BUILD_CLRSETBITS(bwlq, sfx, end, type)
+
+#define __to_cpu(v) (v)
+#define cpu_to__(v) (v)
+
+BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, le16, u16)
+BUILD_CLRSETBITS(w, be16, be16, u16)
+BUILD_CLRSETBITS(w, 16, _, u16)
+BUILD_CLRSETBITS(l, le32, le32, u32)
+BUILD_CLRSETBITS(l, be32, be32, u32)
+BUILD_CLRSETBITS(l, 32, _, u32)
+BUILD_CLRSETBITS(q, le64, le64, u64)
+BUILD_CLRSETBITS(q, be64, be64, u64)
+BUILD_CLRSETBITS(q, 64, _, u64)
+
#endif /* _ASM_IO_H */
* of Coprocessor 0 registers.
*
* Copyright (c) 1998 Harald Koerfgen
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ISADEP_H
* kernel or user mode? (CP0_STATUS)
*/
#define KU_MASK 0x08
-#define KU_USER 0x08
+#define KU_USER 0x08
#define KU_KERN 0x00
#else
* kernel or user mode?
*/
#define KU_MASK 0x18
-#define KU_USER 0x10
+#define KU_USER 0x10
#define KU_KERN 0x00
#endif
--- /dev/null
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ... */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return 0;
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
--- /dev/null
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port) (port)
+#define __swizzle_addr_w(port) (port)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time. Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses. The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) le16_to_cpu(x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) le32_to_cpu(x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) le64_to_cpu(x)
+# define __mem_ioswabq(a, x) (x)
+
+#else
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
--- /dev/null
+/*
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002 Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <asm/const.h>
+
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET _AC(0, UL)
+#endif
+
+#ifdef CONFIG_32BIT
+#ifdef CONFIG_KVM_GUEST
+#define CAC_BASE _AC(0x40000000, UL)
+#else
+#define CAC_BASE _AC(0x80000000, UL)
+#endif
+#ifndef IO_BASE
+#define IO_BASE _AC(0xa0000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE _AC(0xa0000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#ifdef CONFIG_KVM_GUEST
+#define MAP_BASE _AC(0x60000000, UL)
+#else
+#define MAP_BASE _AC(0xc0000000, UL)
+#endif
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START _AC(0x20000000, UL)
+#endif
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifndef CAC_BASE
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE _AC(0x9800000000000000, UL)
+#else
+#define CAC_BASE _AC(0xa800000000000000, UL)
+#endif
+#endif
+
+#ifndef IO_BASE
+#define IO_BASE _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef UNCAC_BASE
+#define UNCAC_BASE _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#define MAP_BASE _AC(0xc000000000000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future. Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
+#endif
+
+#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
+#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET)
+#endif
+
+#ifndef FIXADDR_TOP
+#ifdef CONFIG_KVM_GUEST
+#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000)
+#else
+#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
+#endif
+#endif
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000, 07 MIPS Technologies, Inc.
* Copyright (C) 2003, 2004 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
-#if 0
-#include <linux/linkage.h>
-#endif
-
/*
* The following macros are especially useful for __asm__
* inline assembler.
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
#define CP0_INFO $7
+#define CP0_HWRENA $7, 0
#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
+#define CP0_EBASE $15, 1
+#define CP0_CMGCRBASE $15, 3
#define CP0_CONFIG $16
+#define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG5 $16, 5
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
/*
* Coprocessor 0 Set 2 register names
*/
-#define CP0_S2_SRSCTL $12 /* MIPSR2 */
+#define CP0_S2_SRSCTL $12 /* MIPSR2 */
/*
* Coprocessor 0 Set 3 register names
*/
-#define CP0_S3_SRSMAP $12 /* MIPSR2 */
+#define CP0_S3_SRSMAP $12 /* MIPSR2 */
/*
* TX39 Series
*/
#define CP0_TX39_CACHE $7
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION $0
-#define CP1_STATUS $31
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
+/* Generic EntryLo bit definitions */
+#define ENTRYLO_G (_ULCAST_(1) << 0)
+#define ENTRYLO_V (_ULCAST_(1) << 1)
+#define ENTRYLO_D (_ULCAST_(1) << 2)
+#define ENTRYLO_C_SHIFT 3
+#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
-#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
-#define FPU_CSR_COND 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
-#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
-#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
-#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
-#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
-#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
-#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
+/* R3000 EntryLo bit definitions */
+#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
+#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
+#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
+#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
- */
-#define FPU_CSR_ALL_X 0x0003f000
-#define FPU_CSR_UNI_X 0x00020000
-#define FPU_CSR_INV_X 0x00010000
-#define FPU_CSR_DIV_X 0x00008000
-#define FPU_CSR_OVF_X 0x00004000
-#define FPU_CSR_UDF_X 0x00002000
-#define FPU_CSR_INE_X 0x00001000
-
-#define FPU_CSR_ALL_E 0x00000f80
-#define FPU_CSR_INV_E 0x00000800
-#define FPU_CSR_DIV_E 0x00000400
-#define FPU_CSR_OVF_E 0x00000200
-#define FPU_CSR_UDF_E 0x00000100
-#define FPU_CSR_INE_E 0x00000080
-
-#define FPU_CSR_ALL_S 0x0000007c
-#define FPU_CSR_INV_S 0x00000040
-#define FPU_CSR_DIV_S 0x00000020
-#define FPU_CSR_OVF_S 0x00000010
-#define FPU_CSR_UDF_S 0x00000008
-#define FPU_CSR_INE_S 0x00000004
-
-/* rounding mode */
-#define FPU_CSR_RN 0x0 /* nearest */
-#define FPU_CSR_RZ 0x1 /* towards zero */
-#define FPU_CSR_RU 0x2 /* towards +Infinity */
-#define FPU_CSR_RD 0x3 /* towards -Infinity */
+/* MIPS32/64 EntryLo bit definitions */
+#define MIPS_ENTRYLO_PFN_SHIFT 6
+#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
/*
* Values for PageMask register
#else
#define PM_4K 0x00000000
+#define PM_8K 0x00002000
#define PM_16K 0x00006000
+#define PM_32K 0x0000e000
#define PM_64K 0x0001e000
+#define PM_128K 0x0003e000
#define PM_256K 0x0007e000
+#define PM_512K 0x000fe000
#define PM_1M 0x001fe000
+#define PM_2M 0x003fe000
#define PM_4M 0x007fe000
+#define PM_8M 0x00ffe000
#define PM_16M 0x01ffe000
+#define PM_32M 0x03ffe000
#define PM_64M 0x07ffe000
#define PM_256M 0x1fffe000
+#define PM_1G 0x7fffe000
#endif
#define PL_64M 26
#define PL_256M 28
+/*
+ * PageGrain bits
+ */
+#define PG_RIE (_ULCAST_(1) << 31)
+#define PG_XIE (_ULCAST_(1) << 30)
+#define PG_ELPA (_ULCAST_(1) << 29)
+#define PG_ESP (_ULCAST_(1) << 28)
+#define PG_IEC (_ULCAST_(1) << 27)
+
+/* MIPS32/64 EntryHI bit definitions */
+#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
+
/*
* R4x00 interrupt enable / cause bits
*/
-#define IE_SW0 (_ULCAST_(1) << 8)
-#define IE_SW1 (_ULCAST_(1) << 9)
+#define IE_SW0 (_ULCAST_(1) << 8)
+#define IE_SW1 (_ULCAST_(1) << 9)
#define IE_IRQ0 (_ULCAST_(1) << 10)
#define IE_IRQ1 (_ULCAST_(1) << 11)
#define IE_IRQ2 (_ULCAST_(1) << 12)
/*
* R4x00 interrupt cause bits
*/
-#define C_SW0 (_ULCAST_(1) << 8)
-#define C_SW1 (_ULCAST_(1) << 9)
+#define C_SW0 (_ULCAST_(1) << 8)
+#define C_SW1 (_ULCAST_(1) << 9)
#define C_IRQ0 (_ULCAST_(1) << 10)
#define C_IRQ1 (_ULCAST_(1) << 11)
#define C_IRQ2 (_ULCAST_(1) << 12)
/*
* Bits specific to the R4640/R4650
*/
-#define ST0_UM (_ULCAST_(1) << 4)
+#define ST0_UM (_ULCAST_(1) << 4)
#define ST0_IL (_ULCAST_(1) << 23)
#define ST0_DL (_ULCAST_(1) << 24)
*/
#define ST0_MX 0x01000000
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT 19
-#define TX39_CONF_ICS_MASK 0x00380000
-#define TX39_CONF_ICS_1KB 0x00000000
-#define TX39_CONF_ICS_2KB 0x00080000
-#define TX39_CONF_ICS_4KB 0x00100000
-#define TX39_CONF_ICS_8KB 0x00180000
-#define TX39_CONF_ICS_16KB 0x00200000
-
-#define TX39_CONF_DCS_SHIFT 16
-#define TX39_CONF_DCS_MASK 0x00070000
-#define TX39_CONF_DCS_1KB 0x00000000
-#define TX39_CONF_DCS_2KB 0x00010000
-#define TX39_CONF_DCS_4KB 0x00020000
-#define TX39_CONF_DCS_8KB 0x00030000
-#define TX39_CONF_DCS_16KB 0x00040000
-
-#define TX39_CONF_CWFON 0x00004000
-#define TX39_CONF_WBON 0x00002000
-#define TX39_CONF_RF_SHIFT 10
-#define TX39_CONF_RF_MASK 0x00000c00
-#define TX39_CONF_DOZE 0x00000200
-#define TX39_CONF_HALT 0x00000100
-#define TX39_CONF_LOCK 0x00000080
-#define TX39_CONF_ICE 0x00000020
-#define TX39_CONF_DCE 0x00000010
-#define TX39_CONF_IRSIZE_SHIFT 2
-#define TX39_CONF_IRSIZE_MASK 0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT 0
-#define TX39_CONF_DRSIZE_MASK 0x00000003
-
/*
* Status register bits available in all MIPS CPUs.
*/
#define ST0_IM 0x0000ff00
-#define STATUSB_IP0 8
-#define STATUSF_IP0 (_ULCAST_(1) << 8)
-#define STATUSB_IP1 9
-#define STATUSF_IP1 (_ULCAST_(1) << 9)
-#define STATUSB_IP2 10
-#define STATUSF_IP2 (_ULCAST_(1) << 10)
-#define STATUSB_IP3 11
-#define STATUSF_IP3 (_ULCAST_(1) << 11)
-#define STATUSB_IP4 12
-#define STATUSF_IP4 (_ULCAST_(1) << 12)
-#define STATUSB_IP5 13
-#define STATUSF_IP5 (_ULCAST_(1) << 13)
-#define STATUSB_IP6 14
-#define STATUSF_IP6 (_ULCAST_(1) << 14)
-#define STATUSB_IP7 15
-#define STATUSF_IP7 (_ULCAST_(1) << 15)
-#define STATUSB_IP8 0
-#define STATUSF_IP8 (_ULCAST_(1) << 0)
-#define STATUSB_IP9 1
-#define STATUSF_IP9 (_ULCAST_(1) << 1)
-#define STATUSB_IP10 2
-#define STATUSF_IP10 (_ULCAST_(1) << 2)
-#define STATUSB_IP11 3
-#define STATUSF_IP11 (_ULCAST_(1) << 3)
-#define STATUSB_IP12 4
-#define STATUSF_IP12 (_ULCAST_(1) << 4)
-#define STATUSB_IP13 5
-#define STATUSF_IP13 (_ULCAST_(1) << 5)
-#define STATUSB_IP14 6
-#define STATUSF_IP14 (_ULCAST_(1) << 6)
-#define STATUSB_IP15 7
-#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define STATUSB_IP0 8
+#define STATUSF_IP0 (_ULCAST_(1) << 8)
+#define STATUSB_IP1 9
+#define STATUSF_IP1 (_ULCAST_(1) << 9)
+#define STATUSB_IP2 10
+#define STATUSF_IP2 (_ULCAST_(1) << 10)
+#define STATUSB_IP3 11
+#define STATUSF_IP3 (_ULCAST_(1) << 11)
+#define STATUSB_IP4 12
+#define STATUSF_IP4 (_ULCAST_(1) << 12)
+#define STATUSB_IP5 13
+#define STATUSF_IP5 (_ULCAST_(1) << 13)
+#define STATUSB_IP6 14
+#define STATUSF_IP6 (_ULCAST_(1) << 14)
+#define STATUSB_IP7 15
+#define STATUSF_IP7 (_ULCAST_(1) << 15)
+#define STATUSB_IP8 0
+#define STATUSF_IP8 (_ULCAST_(1) << 0)
+#define STATUSB_IP9 1
+#define STATUSF_IP9 (_ULCAST_(1) << 1)
+#define STATUSB_IP10 2
+#define STATUSF_IP10 (_ULCAST_(1) << 2)
+#define STATUSB_IP11 3
+#define STATUSF_IP11 (_ULCAST_(1) << 3)
+#define STATUSB_IP12 4
+#define STATUSF_IP12 (_ULCAST_(1) << 4)
+#define STATUSB_IP13 5
+#define STATUSF_IP13 (_ULCAST_(1) << 5)
+#define STATUSB_IP14 6
+#define STATUSF_IP14 (_ULCAST_(1) << 6)
+#define STATUSB_IP15 7
+#define STATUSF_IP15 (_ULCAST_(1) << 7)
#define ST0_CH 0x00040000
+#define ST0_NMI 0x00080000
#define ST0_SR 0x00100000
#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000 /* MIPS IV naming */
+/*
+ * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
+ */
+#define INTCTLB_IPFDC 23
+#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
+#define INTCTLB_IPPCI 26
+#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
+#define INTCTLB_IPTI 29
+#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
+
/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
-#define CAUSEB_EXCCODE 2
-#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
-#define CAUSEB_IP 8
-#define CAUSEF_IP (_ULCAST_(255) << 8)
-#define CAUSEB_IP0 8
-#define CAUSEF_IP0 (_ULCAST_(1) << 8)
-#define CAUSEB_IP1 9
-#define CAUSEF_IP1 (_ULCAST_(1) << 9)
-#define CAUSEB_IP2 10
-#define CAUSEF_IP2 (_ULCAST_(1) << 10)
-#define CAUSEB_IP3 11
-#define CAUSEF_IP3 (_ULCAST_(1) << 11)
-#define CAUSEB_IP4 12
-#define CAUSEF_IP4 (_ULCAST_(1) << 12)
-#define CAUSEB_IP5 13
-#define CAUSEF_IP5 (_ULCAST_(1) << 13)
-#define CAUSEB_IP6 14
-#define CAUSEF_IP6 (_ULCAST_(1) << 14)
-#define CAUSEB_IP7 15
-#define CAUSEF_IP7 (_ULCAST_(1) << 15)
-#define CAUSEB_IV 23
-#define CAUSEF_IV (_ULCAST_(1) << 23)
-#define CAUSEB_CE 28
-#define CAUSEF_CE (_ULCAST_(3) << 28)
-#define CAUSEB_BD 31
-#define CAUSEF_BD (_ULCAST_(1) << 31)
+#define CAUSEB_EXCCODE 2
+#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
+#define CAUSEB_IP 8
+#define CAUSEF_IP (_ULCAST_(255) << 8)
+#define CAUSEB_IP0 8
+#define CAUSEF_IP0 (_ULCAST_(1) << 8)
+#define CAUSEB_IP1 9
+#define CAUSEF_IP1 (_ULCAST_(1) << 9)
+#define CAUSEB_IP2 10
+#define CAUSEF_IP2 (_ULCAST_(1) << 10)
+#define CAUSEB_IP3 11
+#define CAUSEF_IP3 (_ULCAST_(1) << 11)
+#define CAUSEB_IP4 12
+#define CAUSEF_IP4 (_ULCAST_(1) << 12)
+#define CAUSEB_IP5 13
+#define CAUSEF_IP5 (_ULCAST_(1) << 13)
+#define CAUSEB_IP6 14
+#define CAUSEF_IP6 (_ULCAST_(1) << 14)
+#define CAUSEB_IP7 15
+#define CAUSEF_IP7 (_ULCAST_(1) << 15)
+#define CAUSEB_FDCI 21
+#define CAUSEF_FDCI (_ULCAST_(1) << 21)
+#define CAUSEB_IV 23
+#define CAUSEF_IV (_ULCAST_(1) << 23)
+#define CAUSEB_PCI 26
+#define CAUSEF_PCI (_ULCAST_(1) << 26)
+#define CAUSEB_CE 28
+#define CAUSEF_CE (_ULCAST_(3) << 28)
+#define CAUSEB_TI 30
+#define CAUSEF_TI (_ULCAST_(1) << 30)
+#define CAUSEB_BD 31
+#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
* Bits in the coprocessor 0 config register.
#define CONF_BE (_ULCAST_(1) << 15)
/* Bits common to various processors. */
-#define CONF_CU (_ULCAST_(1) << 3)
-#define CONF_DB (_ULCAST_(1) << 4)
-#define CONF_IB (_ULCAST_(1) << 5)
-#define CONF_DC (_ULCAST_(7) << 6)
-#define CONF_IC (_ULCAST_(7) << 9)
+#define CONF_CU (_ULCAST_(1) << 3)
+#define CONF_DB (_ULCAST_(1) << 4)
+#define CONF_IB (_ULCAST_(1) << 5)
+#define CONF_DC (_ULCAST_(7) << 6)
+#define CONF_IC (_ULCAST_(7) << 9)
#define CONF_EB (_ULCAST_(1) << 13)
#define CONF_EM (_ULCAST_(1) << 14)
#define CONF_SM (_ULCAST_(1) << 16)
#define CONF_SC (_ULCAST_(1) << 17)
#define CONF_EW (_ULCAST_(3) << 18)
-#define CONF_EP (_ULCAST_(15)<< 24)
+#define CONF_EP (_ULCAST_(15) << 24)
#define CONF_EC (_ULCAST_(7) << 28)
#define CONF_CM (_ULCAST_(1) << 31)
-/* Bits specific to the R4xx0. */
+/* Bits specific to the R4xx0. */
#define R4K_CONF_SW (_ULCAST_(1) << 20)
#define R4K_CONF_SS (_ULCAST_(1) << 21)
#define R4K_CONF_SB (_ULCAST_(3) << 22)
-/* Bits specific to the R5000. */
+/* Bits specific to the R5000. */
#define R5K_CONF_SE (_ULCAST_(1) << 12)
#define R5K_CONF_SS (_ULCAST_(3) << 20)
-/* Bits specific to the RM7000. */
-#define RM7K_CONF_SE (_ULCAST_(1) << 3)
+/* Bits specific to the RM7000. */
+#define RM7K_CONF_SE (_ULCAST_(1) << 3)
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
-/* Bits specific to the R10000. */
-#define R10K_CONF_DN (_ULCAST_(3) << 3)
-#define R10K_CONF_CT (_ULCAST_(1) << 5)
-#define R10K_CONF_PE (_ULCAST_(1) << 6)
-#define R10K_CONF_PM (_ULCAST_(3) << 7)
-#define R10K_CONF_EC (_ULCAST_(15)<< 9)
+/* Bits specific to the R10000. */
+#define R10K_CONF_DN (_ULCAST_(3) << 3)
+#define R10K_CONF_CT (_ULCAST_(1) << 5)
+#define R10K_CONF_PE (_ULCAST_(1) << 6)
+#define R10K_CONF_PM (_ULCAST_(3) << 7)
+#define R10K_CONF_EC (_ULCAST_(15) << 9)
#define R10K_CONF_SB (_ULCAST_(1) << 13)
#define R10K_CONF_SK (_ULCAST_(1) << 14)
#define R10K_CONF_SS (_ULCAST_(7) << 16)
#define R10K_CONF_DC (_ULCAST_(7) << 26)
#define R10K_CONF_IC (_ULCAST_(7) << 29)
-/* Bits specific to the VR41xx. */
+/* Bits specific to the VR41xx. */
#define VR41_CONF_CS (_ULCAST_(1) << 12)
#define VR41_CONF_P4K (_ULCAST_(1) << 13)
#define VR41_CONF_BP (_ULCAST_(1) << 16)
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
#define VR41_CONF_AD (_ULCAST_(1) << 23)
-/* Bits specific to the R30xx. */
+/* Bits specific to the R30xx. */
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
-/* Bits specific to the MIPS32/64 PRA. */
-#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+/* Bits specific to the MIPS32/64 PRA. */
+#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
+#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
/*
* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
*/
-#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
-#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
-#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
-#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
-#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
-#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
-#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
-#define MIPS_CONF1_DA_SHIFT 7
-#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
-#define MIPS_CONF1_DL_SHIFT 10
+#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
+#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
+#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
+#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
+#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
+#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
+#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
+#define MIPS_CONF1_DA_SHF 7
+#define MIPS_CONF1_DA_SZ 3
+#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
+#define MIPS_CONF1_DL_SHF 10
+#define MIPS_CONF1_DL_SZ 3
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS_SHIFT 13
+#define MIPS_CONF1_DS_SHF 13
+#define MIPS_CONF1_DS_SZ 3
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA_SHIFT 16
+#define MIPS_CONF1_IA_SHF 16
+#define MIPS_CONF1_IA_SZ 3
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL_SHIFT 19
+#define MIPS_CONF1_IL_SHF 19
+#define MIPS_CONF1_IL_SZ 3
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS_SHIFT 22
+#define MIPS_CONF1_IS_SHF 22
+#define MIPS_CONF1_IS_SZ 3
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
-#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
-#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
-#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
+#define MIPS_CONF1_TLBS_SHIFT (25)
+#define MIPS_CONF1_TLBS_SIZE (6)
+#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
+
+#define MIPS_CONF2_SA (_ULCAST_(15) << 0)
+#define MIPS_CONF2_SL (_ULCAST_(15) << 4)
+#define MIPS_CONF2_SS (_ULCAST_(15) << 8)
+#define MIPS_CONF2_SU (_ULCAST_(15) << 12)
+#define MIPS_CONF2_TA (_ULCAST_(15) << 16)
+#define MIPS_CONF2_TL (_ULCAST_(15) << 20)
+#define MIPS_CONF2_TS (_ULCAST_(15) << 24)
#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
-#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
-#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
-#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
-#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
-#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
-#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
-#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
+#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
+#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
+#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
+#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
+#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
+#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
+#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
+#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
+#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
+#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
+#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
+#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
+#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
+
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
+#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT (0)
+#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
+#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
+/* bits 10:8 in FTLB-only configurations */
+#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+/* bits 12:8 in VTLB-FTLB only configurations */
+#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
+#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
+
+#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
+#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
+#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
+#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
+#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
+#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
+#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
+#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
+#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
+#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
+#define MIPS_CONF5_K (_ULCAST_(1) << 30)
+
+#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
+/* proAptiv FTLB on/off bit */
+#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
+/* FTLB probability bits */
+#define MIPS_CONF6_FTLBP_SHIFT (16)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+/* FTLB probability bits for R6 */
+#define MIPS_CONF7_FTLBP_SHIFT (18)
+
+/* MAAR bit definitions */
+#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
+#define MIPS_MAAR_ADDR_SHIFT 12
+#define MIPS_MAAR_S (_ULCAST_(1) << 1)
+#define MIPS_MAAR_V (_ULCAST_(1) << 0)
+
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE 11
+#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT 9
+#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT 4
+#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT 3
+#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT 0
+#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK _ULCAST_(7)
+#define MIPS_SEGCFG_USK _ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
+#define MIPS_SEGCFG_MUSK _ULCAST_(3)
+#define MIPS_SEGCFG_MSK _ULCAST_(2)
+#define MIPS_SEGCFG_MK _ULCAST_(1)
+#define MIPS_SEGCFG_UK _ULCAST_(0)
+
+#define MIPS_PWFIELD_GDI_SHIFT 24
+#define MIPS_PWFIELD_GDI_MASK 0x3f000000
+#define MIPS_PWFIELD_UDI_SHIFT 18
+#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
+#define MIPS_PWFIELD_MDI_SHIFT 12
+#define MIPS_PWFIELD_MDI_MASK 0x0003f000
+#define MIPS_PWFIELD_PTI_SHIFT 6
+#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
+#define MIPS_PWFIELD_PTEI_SHIFT 0
+#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
+
+#define MIPS_PWSIZE_GDW_SHIFT 24
+#define MIPS_PWSIZE_GDW_MASK 0x3f000000
+#define MIPS_PWSIZE_UDW_SHIFT 18
+#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
+#define MIPS_PWSIZE_MDW_SHIFT 12
+#define MIPS_PWSIZE_MDW_MASK 0x0003f000
+#define MIPS_PWSIZE_PTW_SHIFT 6
+#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
+#define MIPS_PWSIZE_PTEW_SHIFT 0
+#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
+
+#define MIPS_PWCTL_PWEN_SHIFT 31
+#define MIPS_PWCTL_PWEN_MASK 0x80000000
+#define MIPS_PWCTL_DPH_SHIFT 7
+#define MIPS_PWCTL_DPH_MASK 0x00000080
+#define MIPS_PWCTL_HUGEPG_SHIFT 6
+#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
+#define MIPS_PWCTL_PSN_SHIFT 0
+#define MIPS_PWCTL_PSN_MASK 0x0000003f
+
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT 19
+#define TX39_CONF_ICS_MASK 0x00380000
+#define TX39_CONF_ICS_1KB 0x00000000
+#define TX39_CONF_ICS_2KB 0x00080000
+#define TX39_CONF_ICS_4KB 0x00100000
+#define TX39_CONF_ICS_8KB 0x00180000
+#define TX39_CONF_ICS_16KB 0x00200000
+
+#define TX39_CONF_DCS_SHIFT 16
+#define TX39_CONF_DCS_MASK 0x00070000
+#define TX39_CONF_DCS_1KB 0x00000000
+#define TX39_CONF_DCS_2KB 0x00010000
+#define TX39_CONF_DCS_4KB 0x00020000
+#define TX39_CONF_DCS_8KB 0x00030000
+#define TX39_CONF_DCS_16KB 0x00040000
+
+#define TX39_CONF_CWFON 0x00004000
+#define TX39_CONF_WBON 0x00002000
+#define TX39_CONF_RF_SHIFT 10
+#define TX39_CONF_RF_MASK 0x00000c00
+#define TX39_CONF_DOZE 0x00000200
+#define TX39_CONF_HALT 0x00000100
+#define TX39_CONF_LOCK 0x00000080
+#define TX39_CONF_ICE 0x00000020
+#define TX39_CONF_DCE 0x00000010
+#define TX39_CONF_IRSIZE_SHIFT 2
+#define TX39_CONF_IRSIZE_MASK 0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT 0
+#define TX39_CONF_DRSIZE_MASK 0x00000003
+
+/*
+ * Interesting Bits in the R10K CP0 Branch Diagnostic Register
+ */
+/* Disable Branch Target Address Cache */
+#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
+/* Enable Branch Prediction Global History */
+#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
+/* Disable Branch Return Cache */
+#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION $0
+#define CP1_UFR $1
+#define CP1_UNFR $4
+#define CP1_FCCR $25
+#define CP1_FEXR $26
+#define CP1_FENR $28
+#define CP1_STATUS $31
+
+
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
+ */
+#define MIPS_FCCR_CONDX_S 0
+#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S 0
+#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S 1
+#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S 2
+#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S 3
+#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S 4
+#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S 5
+#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S 6
+#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S 7
+#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S 2
+#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
+
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_COND_S 23 /* $fcc0 */
+#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
+#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
+#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25 /* $fcc1 */
+#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26 /* $fcc2 */
+#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27 /* $fcc3 */
+#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28 /* $fcc4 */
+#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29 /* $fcc5 */
+#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30 /* $fcc6 */
+#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31 /* $fcc7 */
+#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
+
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
+
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X 0x00020000
+#define FPU_CSR_INV_X 0x00010000
+#define FPU_CSR_DIV_X 0x00008000
+#define FPU_CSR_OVF_X 0x00004000
+#define FPU_CSR_UDF_X 0x00002000
+#define FPU_CSR_INE_X 0x00001000
+
+#define FPU_CSR_ALL_E 0x00000f80
+#define FPU_CSR_INV_E 0x00000800
+#define FPU_CSR_DIV_E 0x00000400
+#define FPU_CSR_OVF_E 0x00000200
+#define FPU_CSR_UDF_E 0x00000100
+#define FPU_CSR_INE_E 0x00000080
+
+#define FPU_CSR_ALL_S 0x0000007c
+#define FPU_CSR_INV_S 0x00000040
+#define FPU_CSR_DIV_S 0x00000020
+#define FPU_CSR_OVF_S 0x00000010
+#define FPU_CSR_UDF_S 0x00000008
+#define FPU_CSR_INE_S 0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM 0x00000003
+#define FPU_CSR_RN 0x0 /* nearest */
+#define FPU_CSR_RZ 0x1 /* towards zero */
+#define FPU_CSR_RU 0x2 /* towards +Infinity */
+#define FPU_CSR_RD 0x3 /* towards -Infinity */
+
#ifndef __ASSEMBLY__
/*
- * Functions to access the R10000 performance counters. These are basically
+ * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
+ */
+#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
+ defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
+#define get_isa16_mode(x) ((x) & 0x1)
+#define msk_isa16_mode(x) ((x) & ~0x1)
+#define set_isa16_mode(x) do { (x) |= 0x1; } while (0)
+#else
+#define get_isa16_mode(x) 0
+#define msk_isa16_mode(x) (x)
+#define set_isa16_mode(x) do { } while (0)
+#endif
+
+/*
+ * microMIPS instructions can be 16-bit or 32-bit in length. This
+ * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
+ */
+static inline int mm_insn_16bit(u16 insn)
+{
+ u16 opcode = (insn >> 10) & 0x7;
+
+ return (opcode >= 1 && opcode <= 3) ? 1 : 0;
+}
+
+/*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".word 0x42000004\n\t" /* tlbinvf */
+ ".set pop");
+}
+
+
+/*
+ * Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
* performance counter number encoded into bits 1 ... 5 of the instruction.
* Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
: "r" (val), "i" (counter)); \
} while (0)
+
/*
* Macros to access the system control coprocessor
*/
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
+ "dsra\t%M0, %M0, 32\n\t" \
+ "dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
else \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
+ "dsra\t%M0, %M0, 32\n\t" \
+ "dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
local_irq_restore(__flags); \
local_irq_restore(__flags); \
} while (0)
+#define __readx_32bit_c0_register(source) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " .set mips32r2 \n" \
+ " .insn \n" \
+ " # mfhc0 $1, %1 \n" \
+ " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (source)); \
+ __res; \
+})
+
+#define __writex_32bit_c0_register(register, value) \
+({ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " .set mips32r2 \n" \
+ " move $1, %0 \n" \
+ " # mthc0 $1, %1 \n" \
+ " .insn \n" \
+ " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
+ " .set pop \n" \
+ : \
+ : "r" (value), "i" (register)); \
+})
+
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
+#define read_c0_random() __read_32bit_c0_register($1, 0)
+#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
+
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
+#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
+#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
+
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
+#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
+#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
+
#define read_c0_conf() __read_32bit_c0_register($3, 0)
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
-#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
+#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
+
#define read_c0_wired() __read_32bit_c0_register($6, 0)
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
#define read_c0_info() __read_32bit_c0_register($7, 0)
-#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
+#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
-#ifdef CONFIG_MIPS_MT_SMTC
-#define write_c0_status(val) \
-do { \
- __write_32bit_c0_register($12, 0, val); \
- __ehb(); \
-} while (0)
-#else
-/*
- * Legacy non-SMTC code, which may be hazardous
- * but which might not support EHB
- */
+
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
-#endif /* CONFIG_MIPS_MT_SMTC */
#define read_c0_cause() __read_32bit_c0_register($13, 0)
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
#define read_c0_prid() __read_32bit_c0_register($15, 0)
+#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
+
#define read_c0_config() __read_32bit_c0_register($16, 0)
#define read_c0_config1() __read_32bit_c0_register($16, 1)
#define read_c0_config2() __read_32bit_c0_register($16, 2)
#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
+#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
+#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
+#define read_c0_maar() __read_ulong_c0_register($17, 1)
+#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
+#define read_c0_maari() __read_32bit_c0_register($17, 2)
+#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
+
/*
- * The WatchLo register. There may be upto 8 of them.
+ * The WatchLo register. There may be up to 8 of them.
*/
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
/*
- * The WatchHi register. There may be upto 8 of them.
+ * The WatchHi register. There may be up to 8 of them.
*/
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
-
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
#define read_c0_diag() __read_32bit_c0_register($22, 0)
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
+/* R10K CP0 Branch Diagnostic register is 64bits wide */
+#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
+#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
+
#define read_c0_diag1() __read_32bit_c0_register($22, 1)
#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
* MIPS32 / MIPS64 performance counters
*/
#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
-#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
-#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
-#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
-#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
-#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
-#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
-#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
-#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
-
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
+#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo() __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
+
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
+#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
+
+/* MIPSR3 */
+#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
+
+/* Hardware Page Table Walker */
+#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
+#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
+
+#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
+#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
+
+#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
+#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
+
+#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
+#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
+
+/* Cavium OCTEON (cnMIPS) */
+#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
+#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
+
+#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
+#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
+
+#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
+#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
/*
- * Macros to access the floating point coprocessor control registers
+ * The cacheerr registers are not standardized. On OCTEON, they are
+ * 64 bits wide.
*/
-#define read_32bit_cp1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc1\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
+#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
+#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
-#define rddsp(mask) \
+#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
+#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
+
+/* BMIPS3300 */
+#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS43xx */
+#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define _read_32bit_cp1_register(source, gas_hardfloat) \
({ \
unsigned int __res; \
\
__asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # rddsp $1, %x1 \n" \
- " .word 0x7c000cb8 | (%x1 << 16) \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__res) \
- : "i" (mask)); \
+ " .set push \n" \
+ " .set reorder \n" \
+ " # gas fails to assemble cfc1 for some archs, \n" \
+ " # like Octeon. \n" \
+ " .set mips1 \n" \
+ " "STR(gas_hardfloat)" \n" \
+ " cfc1 %0,"STR(source)" \n" \
+ " .set pop \n" \
+ : "=r" (__res)); \
__res; \
})
-#define wrdsp(val, mask) \
-do { \
+#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
- " .set noat \n" \
- " move $1, %0 \n" \
- " # wrdsp $1, %x1 \n" \
- " .word 0x7c2004f8 | (%x1 << 11) \n" \
+ " .set reorder \n" \
+ " "STR(gas_hardfloat)" \n" \
+ " ctc1 %0,"STR(dest)" \n" \
" .set pop \n" \
+ : : "r" (val)); \
+})
+
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source) \
+ _read_32bit_cp1_register(source, .set hardfloat)
+#define write_32bit_cp1_register(dest, val) \
+ _write_32bit_cp1_register(dest, val, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source) \
+ _read_32bit_cp1_register(source, )
+#define write_32bit_cp1_register(dest, val) \
+ _write_32bit_cp1_register(dest, val, )
+#endif
+
+#ifdef HAVE_AS_DSP
+#define rddsp(mask) \
+({ \
+ unsigned int __dspctl; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " rddsp %0, %x1 \n" \
+ " .set pop \n" \
+ : "=r" (__dspctl) \
+ : "i" (mask)); \
+ __dspctl; \
+})
+
+#define wrdsp(val, mask) \
+({ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " wrdsp %0, %x1 \n" \
+ " .set pop \n" \
: \
: "r" (val), "i" (mask)); \
-} while (0)
+})
+
+#define mflo0() \
+({ \
+ long mflo0; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac0 \n" \
+ " .set pop \n" \
+ : "=r" (mflo0)); \
+ mflo0; \
+})
+
+#define mflo1() \
+({ \
+ long mflo1; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac1 \n" \
+ " .set pop \n" \
+ : "=r" (mflo1)); \
+ mflo1; \
+})
+
+#define mflo2() \
+({ \
+ long mflo2; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac2 \n" \
+ " .set pop \n" \
+ : "=r" (mflo2)); \
+ mflo2; \
+})
+
+#define mflo3() \
+({ \
+ long mflo3; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac3 \n" \
+ " .set pop \n" \
+ : "=r" (mflo3)); \
+ mflo3; \
+})
#define mfhi0() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac0 \n" \
- " .word 0x00000810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi0; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac0 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi0)); \
+ mfhi0; \
})
#define mfhi1() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac1 \n" \
- " .word 0x00200810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi1; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac1 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi1)); \
+ mfhi1; \
})
#define mfhi2() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac2 \n" \
- " .word 0x00400810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi2; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac2 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi2)); \
+ mfhi2; \
})
#define mfhi3() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac3 \n" \
- " .word 0x00600810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi3; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac3 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi3)); \
+ mfhi3; \
})
-#define mflo0() \
+
+#define mtlo0(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac0 \n" \
- " .word 0x00000812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac0 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo1() \
+#define mtlo1(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac1 \n" \
- " .word 0x00200812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac1 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo2() \
+#define mtlo2(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac2 \n" \
- " .word 0x00400812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac2 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo3() \
+#define mtlo3(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac3 \n" \
- " .word 0x00600812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac3 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
#define mthi0(x) \
-do { \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac0 \n" \
- " .word 0x00200011 \n" \
- " .set pop \n" \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac0 \n" \
+ " .set pop \n" \
: \
: "r" (x)); \
-} while (0)
+})
#define mthi1(x) \
-do { \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac1 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#define mthi2(x) \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac2 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#define mthi3(x) \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac3 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#else
+
+#ifdef CONFIG_CPU_MICROMIPS
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac1 \n" \
- " .word 0x00200811 \n" \
+ " # rddsp $1, %x1 \n" \
+ " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
+ " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
-#define mthi2(x) \
-do { \
+#define wrdsp(val, mask) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mthi $1, $ac2 \n" \
- " .word 0x00201011 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
+ " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (mask)); \
+})
-#define mthi3(x) \
-do { \
+#define _umips_dsp_mfxxx(ins) \
+({ \
+ unsigned long __treg; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac3 \n" \
- " .word 0x00201811 \n" \
+ " .hword 0x0001 \n" \
+ " .hword %x1 \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__treg) \
+ : "i" (ins)); \
+ __treg; \
+})
-#define mtlo0(x) \
-do { \
+#define _umips_dsp_mtxxx(val, ins) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac0 \n" \
- " .word 0x00200013 \n" \
+ " .hword 0x0001 \n" \
+ " .hword %x1 \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (ins)); \
+})
-#define mtlo1(x) \
-do { \
+#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
+#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
+
+#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
+#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
+
+#define mflo0() _umips_dsp_mflo(0)
+#define mflo1() _umips_dsp_mflo(1)
+#define mflo2() _umips_dsp_mflo(2)
+#define mflo3() _umips_dsp_mflo(3)
+
+#define mfhi0() _umips_dsp_mfhi(0)
+#define mfhi1() _umips_dsp_mfhi(1)
+#define mfhi2() _umips_dsp_mfhi(2)
+#define mfhi3() _umips_dsp_mfhi(3)
+
+#define mtlo0(x) _umips_dsp_mtlo(x, 0)
+#define mtlo1(x) _umips_dsp_mtlo(x, 1)
+#define mtlo2(x) _umips_dsp_mtlo(x, 2)
+#define mtlo3(x) _umips_dsp_mtlo(x, 3)
+
+#define mthi0(x) _umips_dsp_mthi(x, 0)
+#define mthi1(x) _umips_dsp_mthi(x, 1)
+#define mthi2(x) _umips_dsp_mthi(x, 2)
+#define mthi3(x) _umips_dsp_mthi(x, 3)
+
+#else /* !CONFIG_CPU_MICROMIPS */
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # rddsp $1, %x1 \n" \
+ " .word 0x7c000cb8 | (%x1 << 16) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
+
+#define wrdsp(val, mask) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac1 \n" \
- " .word 0x00200813 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .word 0x7c2004f8 | (%x1 << 11) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (mask)); \
+})
-#define mtlo2(x) \
-do { \
+#define _dsp_mfxxx(ins) \
+({ \
+ unsigned long __treg; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mtlo $1, $ac2 \n" \
- " .word 0x00201013 \n" \
+ " .word (0x00000810 | %1) \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__treg) \
+ : "i" (ins)); \
+ __treg; \
+})
-#define mtlo3(x) \
-do { \
+#define _dsp_mtxxx(val, ins) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac3 \n" \
- " .word 0x00201813 \n" \
+ " .word (0x00200011 | %1) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (ins)); \
+})
+
+#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
+#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
+
+#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
+#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
+
+#define mflo0() _dsp_mflo(0)
+#define mflo1() _dsp_mflo(1)
+#define mflo2() _dsp_mflo(2)
+#define mflo3() _dsp_mflo(3)
+
+#define mfhi0() _dsp_mfhi(0)
+#define mfhi1() _dsp_mfhi(1)
+#define mfhi2() _dsp_mfhi(2)
+#define mfhi3() _dsp_mfhi(3)
+
+#define mtlo0(x) _dsp_mtlo(x, 0)
+#define mtlo1(x) _dsp_mtlo(x, 1)
+#define mtlo2(x) _dsp_mtlo(x, 2)
+#define mtlo3(x) _dsp_mtlo(x, 3)
+
+#define mthi0(x) _dsp_mthi(x, 0)
+#define mthi1(x) _dsp_mthi(x, 1)
+#define mthi2(x) _dsp_mthi(x, 2)
+#define mthi3(x) _dsp_mthi(x, 3)
+
+#endif /* CONFIG_CPU_MICROMIPS */
+#endif
/*
* TLB operations.
static inline unsigned int \
set_c0_##name(unsigned int set) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res |= set; \
- write_c0_##name(res); \
+ new = res | set; \
+ write_c0_##name(new); \
\
return res; \
} \
static inline unsigned int \
clear_c0_##name(unsigned int clear) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res &= ~clear; \
- write_c0_##name(res); \
+ new = res & ~clear; \
+ write_c0_##name(new); \
\
return res; \
} \
\
static inline unsigned int \
-change_c0_##name(unsigned int change, unsigned int new) \
+change_c0_##name(unsigned int change, unsigned int val) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res &= ~change; \
- res |= (new & change); \
- write_c0_##name(res); \
+ new = res & ~change; \
+ new |= (val & change); \
+ write_c0_##name(new); \
\
return res; \
}
__BUILD_SET_C0(status)
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
+__BUILD_SET_C0(config5)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
+
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+ return read_c0_ebase() & 0x3ff;
+}
#endif /* !__ASSEMBLY__ */
--- /dev/null
+/*
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software. We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page. On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things. The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_NO_EXEC_SHIFT 0
+#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK (7 << _CACHE_SHIFT)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT (24)
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+/*
+ * Bits for extended EntryLo0/EntryLo1 registers
+ */
+#define _PFNX_MASK 0xffffff
+
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT (0)
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
+#define _CACHE_MASK _CACHE_UNCACHED
+
+#define _PFN_SHIFT PAGE_SHIFT
+
+#else
+/*
+ * Below are the "Normal" R4K cases
+ */
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT 0
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#else
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#endif
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+/* Huge TLB page */
+#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
+#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
+#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
+#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+/* XI - page cannot be executed */
+#ifdef _PAGE_SPLITTING_SHIFT
+#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
+
+/* RI - page cannot be read */
+#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
+#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
+#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
+#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
+
+#if defined(_PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
+#elif defined(_PAGE_SPLITTING_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK (7 << _CACHE_SHIFT)
+
+#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
+
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC 0
+#endif
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ 0
+#endif
+
+#define _PAGE_SILENT_READ _PAGE_VALID
+#define _PAGE_SILENT_WRITE _PAGE_DIRTY
+
+#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
+
+/*
+ * The final layouts of the PTE bits are:
+ *
+ * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
+ * 32-bit, R1 or earler: CCC D V G M A W R P
+ * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
+ * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
+ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * pte_to_entrylo converts a page table entry (PTE) into a Mips
+ * entrylo0/1 value.
+ */
+static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+{
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+ if (cpu_has_rixi) {
+ int sa;
+#ifdef CONFIG_32BIT
+ sa = 31 - _PAGE_NO_READ_SHIFT;
+#else
+ sa = 63 - _PAGE_NO_READ_SHIFT;
+#endif
+ /*
+ * C has no way to express that this is a DSRL
+ * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
+ * in the fast path this is done in assembly
+ */
+ return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+ ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+ }
+#endif
+
+ return pte_val >> _PAGE_GLOBAL_SHIFT;
+}
+#endif
+
+/*
+ * Cache attributes
+ */
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
+
+#elif defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+ use it for "noncoherent" spaces, too. Shouldn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+
+#elif defined(CONFIG_CPU_LOONGSON3)
+
+/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
+#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
+
+#elif defined(CONFIG_MACH_INGENIC)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
+#endif
+
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
+#endif
+
+#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
+#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
+ _PFN_MASK | _CACHE_MASK)
+
+#endif /* _ASM_PGTABLE_BITS_H */
-/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
+/*
* Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_POSIX_TYPES_H
#define _ASM_POSIX_TYPES_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_PTRACE_H
#define _ASM_PTRACE_H
-/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
-#define FPR_BASE 32
-#define PC 64
-#define CAUSE 65
-#define BADVADDR 66
-#define MMHI 67
-#define MMLO 68
-#define FPC_CSR 69
-#define FPC_EIR 70
-#define DSP_BASE 71 /* 3 more hi / lo register pairs */
-#define DSP_CONTROL 77
-#define ACX 78
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/isadep.h>
/*
* This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved.
+ *
+ * If you add a register here, also add it to regoffset_table[] in
+ * arch/mips/kernel/ptrace.c.
*/
struct pt_regs {
#ifdef CONFIG_32BIT
/* Pad bytes for argument save space on the stack. */
- unsigned long pad0[6];
+ unsigned long pad0[8];
#endif
/* Saved main processor registers. */
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
- unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-} __attribute__ ((aligned (8)));
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[6]; /* MTM{0-5} */
+ unsigned long long mtp[6]; /* MTP{0-5} */
+#endif
+ unsigned long __last[0];
+} __aligned(8);
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-/* #define PTRACE_GETFPXREGS 18 */
-/* #define PTRACE_SETFPXREGS 19 */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+ return regs->regs[31];
+}
-#define PTRACE_OLDSETOPTIONS 21
+/*
+ * Don't use asm-generic/ptrace.h it defines FP accessors that don't make
+ * sense on MIPS. We rather want an error if they get invoked.
+ */
-#define PTRACE_GET_THREAD_AREA 25
-#define PTRACE_SET_THREAD_AREA 26
+static inline void instruction_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ regs->cp0_epc = val;
+}
-/* Calls to trace a 64bit program from a 32bit program. */
-#define PTRACE_PEEKTEXT_3264 0xc0
-#define PTRACE_PEEKDATA_3264 0xc1
-#define PTRACE_POKETEXT_3264 0xc2
-#define PTRACE_POKEDATA_3264 0xc3
-#define PTRACE_GET_THREAD_AREA_3264 0xc4
+/* Query offset/name of register from its name/offset */
+extern int regs_query_register_offset(const char *name);
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
-#ifdef __KERNEL__
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs: pt_regs from which register value is gotten.
+ * @offset: offset number of the register.
+ *
+ * regs_get_register returns the value of a register. The @offset is the
+ * offset of the register in struct pt_regs address which specified by @regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+ unsigned int offset)
+{
+ if (unlikely(offset > MAX_REG_OFFSET))
+ return 0;
-#include <asm/isadep.h>
+ return *(unsigned long *)((unsigned long)regs + offset);
+}
/*
* Does the process account for user or for system time?
#define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs)
-#endif
+/* Helpers for working with the user stack pointer */
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+ return regs->regs[29];
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ regs->regs[29] = val;
+}
#endif /* _ASM_PTRACE_H */
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_REBOOT_H
#define _ASM_REBOOT_H
* Various register offset definitions for debuggers, core file
* examiners and whatnot.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1995, 1999 by Ralf Baechle
* Copyright (C) 1995, 1999 Silicon Graphics
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_MIPS_REG_H
#define __ASM_MIPS_REG_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ * written by Ralf Baechle <ralf@linux-mips.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
#define t2 $10
#define t3 $11
#define t4 $12
+#define ta0 $12
#define t5 $13
+#define ta1 $13
#define t6 $14
+#define ta2 $14
#define t7 $15
+#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 1999, 2001 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_SGIDEFS_H
#define __ASM_SGIDEFS_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
* Copyright (c) 2000 by Silicon Graphics, Inc.
* Copyright (c) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_STRING_H
#define _ASM_STRING_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994 - 1999 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1994 - 1999 by Ralf Baechle
*
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MIPS_UNALIGNED_H
#define _ASM_MIPS_UNALIGNED_H
{
unsigned long conf1, il;
conf1 = read_c0_config1();
- il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+ il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
return 0;
return 2 << il;
{
unsigned long conf1, dl;
conf1 = read_c0_config1();
- dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+ dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
return 0;
return 2 << dl;
mfc0 $1, CP0_CONFIG, 1
/* detect line size */
- srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
- andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+ srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
+ andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
move \sz, zero
beqz \line_sz, 10f
li \sz, 2
sllv \line_sz, \sz, \line_sz
/* detect associativity */
- srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
- andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
+ srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
+ andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
addi \sz, \sz, 1
/* sz *= line_sz */
mul \sz, \sz, \line_sz
/* detect log32(sets) */
- srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
- andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+ srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
+ andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
addiu $1, $1, 1
andi $1, $1, 0x7
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
#else
- l1_info t2, t8, MIPS_CONF1_IA_SHIFT
+ l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifdef CONFIG_SYS_DCACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
#else
- l1_info t3, t9, MIPS_CONF1_DA_SHIFT
+ l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
#include <net.h>
#include <command.h>
#include <asm/io.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#if defined(CONFIG_CMD_MII)
#include <miiphy.h>
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "Au1X00 ethernet");
+ strcpy(dev->name, "Au1X00 ethernet");
dev->iobase = 0;
dev->priv = 0;
dev->init = au1x00_init;
#include <config.h>
#include <common.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <serial.h>
#include <linux/compiler.h>
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <usb.h>
#include "au1x00_usb_ohci.h"
stw r0, 4(sp)
mov fp, sp
- /* Allocate and zero GD, update SP */
+ /* Allocate and initialize reserved area, update SP */
mov r4, sp
- movhi r2, %hi(board_init_f_mem@h)
- ori r2, r2, %lo(board_init_f_mem@h)
+ movhi r2, %hi(board_init_f_alloc_reserve@h)
+ ori r2, r2, %lo(board_init_f_alloc_reserve@h)
callr r2
-
- /* Update stack- and frame-pointers */
mov sp, r2
+ mov r4, sp
+ movhi r2, %hi(board_init_f_init_reserve@h)
+ ori r2, r2, %lo(board_init_f_init_reserve@h)
+ callr r2
+
+ /* Update frame-pointer */
mov fp, sp
/* Call board_init_f -- never returns */
dev = (struct eth_device *) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "SCC");
+ strcpy(dev->name, "SCC");
dev->init = sec_init;
dev->halt = sec_halt;
dev->send = sec_send;
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/* for FEC1 make sure that the name of the interface is the same
as the old one for compatibility reasons */
if (i == 0) {
- sprintf (dev->name, "FEC");
+ strcpy(dev->name, "FEC");
} else {
sprintf (dev->name, "FEC%d",
ether_fcc_info[i].ether_index + 1);
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "SCC");
+ strcpy(dev->name, "SCC");
dev->iobase = 0;
dev->priv = 0;
dev->init = scc_init;
U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
- sprintf (info, "(C) 2002 DENX Software Engineering");
+ strcpy(info, "(C) 2002 DENX Software Engineering");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
info);
- sprintf (info, " Wolfgang DENK, wd@denx.de");
+ strcpy(info, " Wolfgang DENK, wd@denx.de");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
bl cpu_init_f /* run low-level CPU init code (from Flash) */
#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mr r1, r3
+ bl board_init_f_init_reserve
li r0,0
stwu r0, -4(r1)
stwu r0, -4(r1)
bl cpu_init_f /* run low-level CPU init code (from Flash) */
#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mr r1, r3
+ bl board_init_f_init_reserve
stwu r0, -4(r1)
stwu r0, -4(r1)
#endif
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_DMA_H_
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_I2C_H_
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _FSL_LAW_H_
*
* Copyright 2008 Qstreams Networks, Inc.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MPC8XXX_SPI_H_
addr.sin_family = AF_INET;
addr.sin_port = udph->source;
addr.sin_addr.s_addr = iph->saddr;
- retval = bind(priv->local_bind_sd, &addr, sizeof(addr));
+ retval = bind(priv->local_bind_sd, (struct sockaddr *)&addr,
+ sizeof(addr));
if (retval < 0)
printf("Failed to bind: %d %s\n", errno,
strerror(errno));
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
+ * SPDX-License-Identifier: GPL-2.0
*
*/
#ifndef _SH_MMC_H_
help
Additional size of malloc() pool before relocation.
+config FSP_USE_UPD
+ bool
+ depends on HAVE_FSP
+ default y
+ help
+ Most FSPs use UPD data region for some FSP customization. But there
+ are still some FSPs that might not even have UPD. For such FSPs,
+ override this to n in their platform Kconfig files.
+
config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT
};
/**
- * Override the FSP's UPD.
+ * Override the FSP's configuration data.
* If the device tree does not specify an integer setting, use the default
* provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
*/
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
+ struct upd_region *fsp_upd = &config->fsp_upd;
struct memory_down_data *mem;
const void *blob = gd->fdt_blob;
int node;
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMM_TSEG
- select HAVE_INTEL_ME
select X86_RAMTEST
config SMM_TSEG_SIZE
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/sipi.h>
+#include <asm/fw_cfg.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
#include <linux/linkage.h>
DECLARE_GLOBAL_DATA_PTR;
}
}
-static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
+static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
{
struct udevice *dev;
enable_lapic();
apic_id = lapicid();
- ret = find_cpu_by_apid_id(apic_id, &dev);
+ ret = find_cpu_by_apic_id(apic_id, &dev);
if (ret) {
debug("Unknown CPU apic_id %x\n", apic_id);
goto done;
return msr_count;
}
-static int load_sipi_vector(atomic_t **ap_countp)
+static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
{
struct sipi_params_16bit *params16;
struct sipi_params *params;
params->idt_ptr = (uint32_t)x86_get_idt();
params->stack_size = CONFIG_AP_STACK_SIZE;
- size = params->stack_size * CONFIG_MAX_CPUS;
+ size = params->stack_size * num_cpus;
stack = memalign(size, 4096);
if (!stack)
return -ENOMEM;
lapic_setup();
apic_id = lapicid();
- ret = find_cpu_by_apid_id(apic_id, devp);
+ ret = find_cpu_by_apic_id(apic_id, devp);
if (ret) {
printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
return ret;
return 0;
}
+#ifdef CONFIG_QEMU
+static int qemu_cpu_fixup(void)
+{
+ int ret;
+ int cpu_num;
+ int cpu_online;
+ struct udevice *dev, *pdev;
+ struct cpu_platdata *plat;
+ char *cpu;
+
+ /* first we need to find '/cpus' */
+ for (device_find_first_child(dm_root(), &pdev);
+ pdev;
+ device_find_next_child(&pdev)) {
+ if (!strcmp(pdev->name, "cpus"))
+ break;
+ }
+ if (!pdev) {
+ printf("unable to find cpus device\n");
+ return -ENODEV;
+ }
+
+ /* calculate cpus that are already bound */
+ cpu_num = 0;
+ for (uclass_find_first_device(UCLASS_CPU, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ cpu_num++;
+ }
+
+ /* get actual cpu number */
+ cpu_online = qemu_fwcfg_online_cpus();
+ if (cpu_online < 0) {
+ printf("unable to get online cpu number: %d\n", cpu_online);
+ return cpu_online;
+ }
+
+ /* bind addtional cpus */
+ dev = NULL;
+ for (; cpu_num < cpu_online; cpu_num++) {
+ /*
+ * allocate device name here as device_bind_driver() does
+ * not copy device name, 8 bytes are enough for
+ * sizeof("cpu@") + 3 digits cpu number + '\0'
+ */
+ cpu = malloc(8);
+ if (!cpu) {
+ printf("unable to allocate device name\n");
+ return -ENOMEM;
+ }
+ sprintf(cpu, "cpu@%d", cpu_num);
+ ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev);
+ if (ret) {
+ printf("binding cpu@%d failed: %d\n", cpu_num, ret);
+ return ret;
+ }
+ plat = dev_get_parent_platdata(dev);
+ plat->cpu_id = cpu_num;
+ }
+ return 0;
+}
+#endif
+
int mp_init(struct mp_params *p)
{
int num_aps;
if (ret)
return ret;
+#ifdef CONFIG_QEMU
+ ret = qemu_cpu_fixup();
+ if (ret)
+ return ret;
+#endif
+
ret = init_bsp(&cpu);
if (ret) {
debug("Cannot init boot CPU: err=%d\n", ret);
mp_info.records = p->flight_plan;
/* Load the SIPI vector */
- ret = load_sipi_vector(&ap_count);
+ ret = load_sipi_vector(&ap_count, num_cpus);
if (ap_count == NULL)
return -1;
ifndef CONFIG_EFI_STUB
obj-y += car.o dram.o
endif
-obj-y += qemu.o
+obj-y += cpu.o fw_cfg.o qemu.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
--- /dev/null
+/*
+ * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu.h>
+#include <asm/fw_cfg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
+static int cpu_qemu_get_count(struct udevice *dev)
+{
+ return qemu_fwcfg_online_cpus();
+}
+
+static const struct cpu_ops cpu_qemu_ops = {
+ .get_desc = cpu_qemu_get_desc,
+ .get_count = cpu_qemu_get_count,
+};
+
+static const struct udevice_id cpu_qemu_ids[] = {
+ { .compatible = "cpu-qemu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_qemu_drv) = {
+ .name = "cpu_qemu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_qemu_ids,
+ .ops = &cpu_qemu_ops,
+};
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/fw_cfg.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+ uint32_t size, void *address)
+{
+ uint32_t i = 0;
+ uint8_t *data = address;
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ outw(entry, FW_CONTROL_PORT);
+ while (size--)
+ data[i++] = inb(FW_DATA_PORT);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+ uint32_t size, void *address)
+{
+ struct fw_cfg_dma_access dma;
+
+ dma.length = cpu_to_be32(size);
+ dma.address = cpu_to_be64((uintptr_t)address);
+ dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+ barrier();
+
+ debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
+ address, size, be32_to_cpu(dma.control));
+
+ outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
+
+ while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
+ __asm__ __volatile__ ("pause");
+}
+
+static bool qemu_fwcfg_present(void)
+{
+ uint32_t qemu;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+ return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
+}
+
+static bool qemu_fwcfg_dma_present(void)
+{
+ uint8_t dma_enabled;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+ if (dma_enabled & FW_CFG_DMA_ENABLED)
+ return true;
+
+ return false;
+}
+
+static void qemu_fwcfg_read_entry(uint16_t entry,
+ uint32_t length, void *address)
+{
+ if (fwcfg_dma_present)
+ qemu_fwcfg_read_entry_dma(entry, length, address);
+ else
+ qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+ uint16_t nb_cpus;
+
+ if (!fwcfg_present)
+ return -ENODEV;
+
+ qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+ return le16_to_cpu(nb_cpus);
+}
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+ char *data_addr;
+ uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+ if (setup_size == 0 || kernel_size == 0) {
+ printf("warning: no kernel available\n");
+ return -1;
+ }
+
+ data_addr = load_addr;
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+ le32_to_cpu(setup_size), data_addr);
+ data_addr += le32_to_cpu(setup_size);
+
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+ le32_to_cpu(kernel_size), data_addr);
+ data_addr += le32_to_cpu(kernel_size);
+
+ data_addr = initrd_addr;
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+ if (initrd_size == 0) {
+ printf("warning: no initrd available\n");
+ } else {
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+ le32_to_cpu(initrd_size), data_addr);
+ data_addr += le32_to_cpu(initrd_size);
+ }
+
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+ if (cmdline_size) {
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+ le32_to_cpu(cmdline_size), data_addr);
+ /*
+ * if kernel cmdline only contains '\0', (e.g. no -append
+ * when invoking qemu), do not update bootargs
+ */
+ if (*data_addr != '\0') {
+ if (setenv("bootargs", data_addr) < 0)
+ printf("warning: unable to change bootargs\n");
+ }
+ }
+
+ printf("loading kernel to address %p size %x", load_addr,
+ le32_to_cpu(kernel_size));
+ if (initrd_size)
+ printf(" initrd %p size %x\n",
+ initrd_addr,
+ le32_to_cpu(initrd_size));
+ else
+ printf("\n");
+
+ return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+ int i;
+ uint32_t count;
+ struct fw_cfg_files *files;
+
+ qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+ if (!count)
+ return 0;
+
+ count = be32_to_cpu(count);
+ files = malloc(count * sizeof(struct fw_cfg_file));
+ if (!files)
+ return -ENOMEM;
+
+ files->count = count;
+ qemu_fwcfg_read_entry(FW_CFG_INVALID,
+ count * sizeof(struct fw_cfg_file),
+ files->files);
+
+ for (i = 0; i < files->count; i++)
+ printf("%-56s\n", files->files[i].name);
+ free(files);
+ return 0;
+}
+
+void qemu_fwcfg_init(void)
+{
+ fwcfg_present = qemu_fwcfg_present();
+ if (fwcfg_present)
+ fwcfg_dma_present = qemu_fwcfg_dma_present();
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (qemu_fwcfg_list_firmware() < 0)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int ret = qemu_fwcfg_online_cpus();
+ if (ret < 0) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ char *env;
+ void *load_addr;
+ void *initrd_addr;
+
+ env = getenv("loadaddr");
+ load_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+ (void *)CONFIG_LOADADDR;
+
+ env = getenv("ramdiskaddr");
+ initrd_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+ (void *)CONFIG_RAMDISK_ADDR;
+
+ if (argc == 2) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ } else if (argc == 1) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ }
+
+ return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+ U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+ U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+ U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ cmd_tbl_t *fwcfg_cmd;
+
+ if (!fwcfg_present) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_USAGE;
+ }
+
+ fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+ ARRAY_SIZE(fwcfg_commands));
+ argc -= 2;
+ argv += 2;
+ if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+ return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+ qfw, 4, 1, do_qemu_fw,
+ "QEMU firmware interface",
+ "<command>\n"
+ " - list : print firmware(s) currently loaded\n"
+ " - cpus : print online cpu number\n"
+ " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/qemu.h>
+#include <asm/fw_cfg.h>
static bool i440fx;
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
}
+
+ qemu_fwcfg_init();
}
int arch_cpu_init(void)
*/
quark_setup_bars();
- /*
- * Initialize PCIe controller
- *
- * Quark SoC holds the PCIe controller in reset following a power on.
- * U-Boot needs to release the PCIe controller from reset. The PCIe
- * controller (D23:F0/F1) will not be visible in PCI configuration
- * space and any access to its PCI configuration registers will cause
- * system hang while it is held in reset.
- */
- quark_pcie_early_init();
-
/* Initialize USB2 PHY */
quark_usb_early_init();
return 0;
}
+int arch_cpu_init_dm(void)
+{
+ /*
+ * Initialize PCIe controller
+ *
+ * Quark SoC holds the PCIe controller in reset following a power on.
+ * U-Boot needs to release the PCIe controller from reset. The PCIe
+ * controller (D23:F0/F1) will not be visible in PCI configuration
+ * space and any access to its PCI configuration registers will cause
+ * system hang while it is held in reset.
+ */
+ quark_pcie_early_init();
+
+ return 0;
+}
+
int print_cpuinfo(void)
{
post_code(POST_CPU_INFO);
#include <common.h>
#include <asm/fsp/fsp_support.h>
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
- /* Override any UPD setting if required */
-
- /* Uncomment the line below to enable DEBUG message */
- /* fsp_upd->serial_dbgport_type = 1; */
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
- /* Examples on how to initialize the pointers in UPD region */
- /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */
+ /* Override any UPD setting if required */
}
#endif
/* Set up global data */
mov %esp, %eax
- call board_init_f_mem
+ call board_init_f_alloc_reserve
mov %eax, %esp
+ call board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
call debug_uart_init
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x8>;
+intel,date-code = <0x5182011>;
+intel,processor-signature = <0x306a2>;
+intel,checksum = <0xa0e51feb>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x08000000 0x11201805 0xa2060300
+ 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000
+ 0x00200000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x08000000
+ 0x00000000 0x00000000 0x17051120 0xd1070000
+ 0x01000000 0xa2060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e
+ 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x72873db0 0x0f41a6d6 0x609f17c3
+ 0x1b1349d0 0xe1950c52 0xdbc8e4fc 0xebc212b5
+ 0x77697371 0x7b156982 0xe71e5ccf 0x78bd638c
+ 0x1b196322 0x8b7ebfbf 0xc2e2588f 0xf139b826
+ 0x98ac3169 0xaa9131b0 0x2d7563f8 0xa1300b39
+ 0x5bd4675f 0x25a4b079 0xe006afb1 0x2bd60828
+ 0x453a0abb 0x3b944679 0x33fd63fd 0xd26ff3c9
+ 0x23c0a581 0xf3beb03a 0xc07109cb 0x2e4c27d9
+ 0xc857a22e 0x470c5b1d 0x5b990a43 0x9f6999e6
+ 0xb5d88f30 0x48c6a95c 0x3756bdc5 0xdc7011d2
+ 0x705d8ef2 0xa657f56c 0xa0b168a4 0x219a3d73
+ 0xb761630a 0x3fa1fb9a 0xe82b74c6 0x037911be
+ 0x5104f10d 0xb4b9e04c 0x4db05893 0x86feb635
+ 0x7391fed4 0x5a690081 0x05797a02 0xce30465e
+ 0x989cdec2 0xa478a8c8 0xa406b02b 0x4ac6e170
+ 0x54ceef3f 0xbbe5e10f 0x7e60e8e1 0x32a015cf
+ 0xaf6491a8 0xef6c1c39 0x38d54b81 0xbca9aa3f
+ 0x7be47871 0x1af28407 0x07fde04d 0x56d82648
+ 0x9f91a24f 0xa71eb768 0x263f176d 0x324196dd
+ 0xa31a37a9 0x3f14178c 0xb3fbb89e 0x18d29b03
+ 0x95c2e349 0xbf559bbe 0xa011c68a 0x0be59ecf
+ 0x644217f4 0x330a8356 0x89f5956e 0xb7103120
+ 0x7d0d2203 0x9d40fc96 0xa9279679 0x81d22306
+ 0x1bc7b5fa 0x679e3a28 0x511a7129 0x81a006a4
+ 0x9791dd09 0xed9dd69a 0xe28904ab 0x90621a2e
+ 0x22efe24d 0x215fd043 0x833f7214 0xf4603491
+ 0x38147d32 0xb4a8fadf 0x306947c3 0xf0998693
+ 0x42fc3ed8 0xe04820c4 0x377e0027 0xd9ed3c92
+ 0xcd166b69 0x1d43b6b7 0x16efc18a 0x5890992a
+ 0xae281f65 0x94b09325 0x6129dee5 0x60ccec89
+ 0xae1b35bb 0xdbe389b3 0xd140a7cf 0xccfe2e86
+ 0x72eff1e3 0x625e92d5 0x7e85420e 0x857f43db
+ 0x22c8784b 0x614e4fff 0x02e87cf8 0x2cb6de43
+ 0xd0bc235d 0xcd19968c 0xcce91f04 0xf36b1f2b
+ 0x8552a638 0x8c3b66fa 0x6fce17b0 0xa1a44384
+ 0x141c8798 0xa8981b4d 0x5d62efa2 0x2b9c0cdd
+ 0x985db4b2 0xbdcb9557 0xd46a70e4 0x90353762
+ 0xdb088ed9 0xcb410eb4 0x7d6bb4b1 0x9b451d22
+ 0xd96dca73 0xec56e8fc 0xa450a765 0x327ca511
+ 0x8d498359 0x1c9ec3a8 0x1986a9a5 0x42c679d5
+ 0xbfbe6164 0xde72b0ba 0xec2c6e93 0x97079604
+ 0x11657c6b 0xf82e6bbe 0x98cddc0b 0xb3168682
+ 0xc22896e3 0x33885964 0xc4791283 0x50553998
+ 0x21976704 0x167c459a 0xb083168c 0x77f08c0f
+ 0x31bbef07 0xff142fda 0xca69c3aa 0x56b2c97c
+ 0x4ba16716 0x7c0688a8 0x8a975497 0x5b7d39f6
+ 0x92815873 0x83bba85a 0x561a8fe1 0xd8b1a419
+ 0x092b76af 0xa708fdcc 0x49986eb3 0xd6ff3b26
+ 0x7bc162a2 0xe1d164fb 0x008705e0 0x825bf6b2
+ 0x5f14e5be 0x69a27ff8 0xd8803cea 0x813c89d2
+ 0xd0558aee 0x88dfdd34 0xb959a0e2 0x948e4309
+ 0xd11e40fa 0x12e739ee 0x453a6b84 0xb85174b9
+ 0x433b0d8c 0x44a8a145 0xe904b21b 0x6a824691
+ 0xf9a191ff 0xe930a249 0x54cc511b 0x76860260
+ 0x268756d3 0x6c535556 0xa89514ea 0x553d3792
+ 0xcb004a7b 0xa2f0234b 0x044d0f13 0x92fa800e
+ 0x5c3ff9d0 0x58dbc14d 0xe305c4da 0xa8af0443
+ 0x88efda5c 0xdeba05ec 0xb128acf7 0x8246648d
+ 0x1ff6d432 0xe919faec 0xd7593779 0xbf4f4ffa
+ 0x26ff3f67 0xe385e75c 0xece43afa 0xd18361ac
+ 0x6f1ff0fd 0x34930c03 0x21c3bb52 0x18508c5a
+ 0x5fac5947 0x93bf46c5 0x0093135f 0x976eee2b
+ 0x0d151deb 0x4b80987a 0x172ce7ac 0x3858dca0
+ 0xf97070db 0x2ac62f48 0xb4a51e8a 0x419c1d35
+ 0xdd9e5157 0xdb21aaea 0xb81f9985 0x19ad9859
+ 0x2074a3fb 0x6f15f27d 0xef3f652b 0x9896582e
+ 0x6787efe9 0xcd8c63a6 0xb94fa052 0xe20b59c5
+ 0x1ae5c0b4 0x46c3b1cc 0xe47ae0a2 0x979ceb01
+ 0x8281c594 0x87d430bc 0x8e6942f1 0x73f40077
+ 0x201415c5 0x46f3e2ea 0x2804b307 0xfa897dc7
+ 0xb79c8456 0x9a7f1b68 0x21f77388 0x0a40a857
+ 0xfa9f096e 0x097fec4b 0xb59a8326 0x25825192
+ 0x68c6b0a0 0xd2757f43 0xd09b408f 0x725ee748
+ 0x4391e4eb 0x8147e982 0x2f153b18 0x6251b500
+ 0x69963d11 0xdd3d67f7 0x67efacc9 0xface6418
+ 0xf4d9b154 0x3e6a6c27 0x95ab29e6 0x75d11283
+ 0xe5377709 0x08831cbb 0x9151f9ee 0x23e3dd5e
+ 0x8b7c87d1 0x71e2550f 0x85943522 0x4486916b
+ 0x8c253c1f 0x197c271c 0xda897e03 0x0ba0b957
+ 0xfefb65f3 0x53e500f3 0xcc52630b 0x008ec579
+ 0x225da363 0xfb129d9f 0x7069493e 0x4657e2d2
+ 0xc1d73c79 0xd292191b 0x26314c0f 0x8a20f248
+ 0x76a162b3 0x5b55dd77 0xa03e9e9b 0xca6b073d
+ 0x813cbaa7 0x7078a94e 0x7d14ed49 0xd86e4ddc
+ 0xe2038ab7 0x75e3ca49 0xd65dfae1 0x340125b8
+ 0x815bb509 0xe7270f14 0xd9f5770c 0x9aca22c5
+ 0x0c48deca 0x3c2ff24f 0x2afdbc05 0x1dafce0a
+ 0x3cbe90b4 0xb37b8faf 0xb83cc372 0xe0468ba6
+ 0x32dca511 0x3c026766 0xceb30b38 0x4cfe6196
+ 0x98bbba31 0xe6322e2c 0x7bcd465a 0x9825fc05
+ 0xe9a469ad 0x94e517ec 0x49318a22 0xbee03c9e
+ 0x85e37df3 0x44358a91 0x00c0490a 0xad1e4041
+ 0xef509388 0xf3194050 0xda5a0de5 0x849d1b1a
+ 0xad5c5ce7 0x624cadd7 0xef00b2c8 0x5c423950
+ 0x8ecbf150 0x98314268 0xe7188ca4 0x4c7ab52e
+ 0xe8bd4c4f 0xdd2360e4 0xf72623e8 0xed45c186
+ 0xf1271f39 0xf128076c 0x499fe644 0xc243460d
+ 0xb399912a 0x1894c1fc 0xcc5a12f5 0xb554e06c
+ 0xf7cf59fd 0xd09ce7ed 0x8f93995d 0xad38e480
+ 0x92cfa3cb 0xef29ce8c 0x1ca8efb2 0x4c390618
+ 0x33e36271 0x752074a0 0xda478d2d 0x10a52d8c
+ 0xd99a36a7 0x50d0db0d 0x728e2f68 0x2eaec798
+ 0x6f5ee097 0x965b0f08 0x0e15ab52 0xadcd83da
+ 0xc2a386bb 0x9ba0071f 0xac242740 0x362668f6
+ 0x01e0adea 0x6d1b2254 0xdbd0fa8d 0x2ef68fe9
+ 0x19742cda 0xa2522cd1 0xad6009c1 0x56374b42
+ 0xf77e7b87 0xf47d5152 0x34ef274c 0x6c8f69db
+ 0xe7c1cd2a 0x60ad1a6c 0x5f11b920 0xe4e903e2
+ 0x6d6d9227 0xcd1f2eb2 0x5c81902d 0x637840a0
+ 0x47f88b3c 0xfcc51034 0xad97af5c 0x14403d02
+ 0x9aae22d0 0x42c50b60 0xdf483d6e 0x5b123f8f
+ 0xb8567830 0x4552282d 0x67ecb54f 0xc5279a68
+ 0x47ca430f 0xf3b581cf 0x70084982 0x04e7a816
+ 0x339e2452 0x0ef1fb04 0x15e018cc 0xd2f83552
+ 0x25be4294 0x643a42a0 0x6ea8207e 0xfd01053a
+ 0xfb25050b 0x8f9d5a9b 0x97e55134 0xb338c705
+ 0xcd1fed07 0x21e5fea1 0xbefd892a 0xe870d3b7
+ 0x696555e9 0x02e80efb 0x91be36e5 0xe98e722a
+ 0x0984101b 0x5b7e344c 0x2c37b88d 0xd153be06
+ 0x58a02ee9 0xb74cde84 0xf2c74516 0x86e3e608
+ 0xf476e86e 0x08053489 0xd8eaa295 0x1042e1aa
+ 0xdc1f613a 0x87af7b7b 0x4bc87db1 0xa005aa8f
+ 0xf85e8566 0xeefb7891 0x6a71cdde 0xc897237c
+ 0xd08778ac 0xdb46f47e 0x87900844 0x19bf15ab
+ 0x0fac1b10 0xbca22485 0xf09a3374 0x222594b1
+ 0xbeac6e17 0x9751d50a 0xe57b78de 0x00c901d4
+ 0x6f8569b0 0x7d778d8e 0x146b7a5e 0x017752fe
+ 0xd2efab56 0x92b6414b 0x796c0dac 0xf2c9ba15
+ 0xffaaf707 0x9e1e0c82 0x22410900 0x703caaf1
+ 0x3ba1fbb8 0x6e330a79 0xe8e3416d 0x19f96d99
+ 0xaad45f95 0x8c23afce 0x79ee1c03 0xf9926e38
+ 0x4552598e 0x2a1ab185 0x9614a74f 0x3ee75de8
+ 0xcfd5e9bf 0xfa7c8c10 0xec727ddd 0x596c2a3a
+ 0x2602a577 0xc8701cc0 0x90670ca5 0x6fd2074a
+ 0x237729e5 0xf94389fe 0x56294aca 0xf0e25fcb
+ 0x92d8755e 0xc9ebab69 0x0056c4bf 0x0802b4bd
+ 0xdca506fb 0x8af71ac1 0x5664ee70 0xc0cc9b12
+ 0x1f2b957c 0x86d75b65 0x0356f061 0xb2a7df2d
+ 0xeebcaed9 0x82240f86 0xd442e66e 0x1c90f7a0
+ 0x340ffd46 0x6665830d 0x92d79070 0x5b84b23b
+ 0x73652140 0x9cc4ba89 0x7a5e361b 0x889de8a4
+ 0xf767445b 0x9c6e7316 0x35e07fc4 0x762678c9
+ 0x8a3e23a1 0x8cf392c6 0xbb9bba49 0xb212b538
+ 0x786d11be 0xc04b989b 0xd286c664 0x9e666e96
+ 0x28987d62 0x5620e31f 0x09284b40 0x2c655487
+ 0xce2d6072 0x1f253329 0xffdc93fe 0x7945e700
+ 0x3e063409 0x6b24a76c 0xdc165d13 0x3f1924ad
+ 0x9a20aec4 0xabbd3741 0xa9242541 0x9c2e780b
+ 0xc8369a55 0x285bee8f 0x34564d35 0x36e55913
+ 0x3e64991f 0x17d9e58c 0x8dd1fb64 0x4d8358d3
+ 0x87a80361 0xa4d61dc4 0xf6dfa482 0x81d24c35
+ 0xaf27cba3 0x5e332395 0xfad6e5a3 0x9cabf33a
+ 0xdcf0921d 0xd893c3a9 0xee8cd5a4 0x4803a801
+ 0x4083023b 0x23272921 0xbe63102a 0x6b62f4fc
+ 0xd1358925 0x4c87470c 0xed7e0c37 0x789f86b5
+ 0x48312d14 0xb50547c3 0x310318b3 0xad0e876b
+ 0x3a2b377d 0xed05829b 0x652ded97 0x316081ba
+ 0xd2d2e21c 0xfc3ca2b5 0x1d480f5b 0x854ae0b9
+ 0x1cb9edae 0x1e8f5f6c 0x0b1cac90 0xd02474f8
+ 0xb6cb0359 0x991a241f 0x961dfdd4 0xf4f8a95b
+ 0xa67e5206 0xbe5efa25 0xdc619c64 0xf350e2b2
+ 0x8244d7a0 0x95ff2840 0x1c8b0751 0x001daf7b
+ 0xb4690af6 0x8ada4365 0xebae8afb 0xa9899cc7
+ 0x651b4e76 0xd42501d5 0xbb5a2d30 0x6b0b4fe7
+ 0xb66d5241 0xe4793b34 0x18e98006 0x2f6217e4
+ 0x9dd33721 0xfdd14fb3 0x03e82ad0 0xd5e2dfaa
+ 0xa248461b 0xa309bef3 0x47472de0 0x0ce6c4c7
+ 0xd9c0bf01 0x5c54a2ca 0x9e55fa97 0x992a4b89
+ 0xc75b9782 0xb02d7a3d 0xd948fab4 0x1b6501d6
+ 0x2674a8ad 0xb1ca0d48 0xcfb534c8 0x729864bb
+ 0x047b2178 0xd88ea657 0x863cf450 0xf0fb6923
+ 0x8399574f 0x2bc03d5c 0xb0f7d334 0xfddf7c72
+ 0x462f1132 0x0640ff38 0x03b426be 0x6af7f1f8
+ 0x474d955c 0xd8174573 0x9975e719 0x4956644c
+ 0x38702613 0xa5ca4cdd 0xc55e5234 0xcd7f3532
+ 0x5696e34e 0xbe5a5c3a 0x1faa53bc 0xba0b5b0a
+ 0xc02b0e33 0xa13f7ec5 0x424cbc5c 0x5aa097cf
+ 0x8e8d1c22 0xab66e427 0x9c1053f7 0x7e62751d
+ 0xd4b094a1 0x57d4766f 0xd023b33a 0xbe020296
+ 0x8102755f 0x6bda667c 0x98f6ea76 0x6deaffb3
+ 0x151caa3c 0x0a1040da 0xf125ebd5 0x929de719
+ 0x6618f307 0x30725caa 0x43a034bf 0x3c576c26
+ 0x77fcf426 0xc360ce49 0x11bc4948 0x2e6dcbf3
+ 0x8b97bf44 0x6eb13c10 0x00cd36ab 0x96b6882c
+ 0x0b312e25 0x534ce45f 0xa6989601 0x6c6c7cdf
+ 0x55fcf9b5 0xea942bc0 0x8252c5ce 0xfd09785c
+ 0x229c3b7d 0xe7129a97 0x9f8db8fb 0xcf692362
+ 0xec8bd49b 0x5b8af7c5 0x020d4843 0xb93cf2c8
+ 0xedcd4fa7 0xf2a9574a 0xa90f2c74 0x5e07cf79
+ 0x0eec3c4c 0x7072b5f5 0x510792d6 0x903a8ca6
+ 0x0952d985 0xa48b5979 0xc6f1cfc7 0xbac813be
+ 0x736163ef 0x6c8e44e9 0x06d2bd0a 0x3fc587d5
+ 0x286e1d65 0x5b6555f6 0x275f8dcc 0x5edb3403
+ 0x412474ed 0x4e41ec00 0xb715c278 0x2777a192
+ 0x40ded494 0x319ec8a6 0xb39c0eef 0xfe4dafca
+ 0xa708b162 0x11d2111f 0xc2806d8e 0x2b631990
+ 0xfc59bb27 0x440667ec 0xc1c43799 0x4aa51bc7
+ 0x08ce990d 0x2425580c 0x9645de2a 0xe7196d6c
+ 0x08d4d524 0xcf4e772a 0x21c18347 0x5bd72d56
+ 0x883bf90b 0xbc262ff0 0x10cfdc55 0x18022197
+ 0x5f0ab36f 0xd689e2b8 0x1c69f462 0x48bba7d6
+ 0x0ab172cd 0xdf060504 0xf8973c1b 0x3206adfe
+ 0xb2cb1735 0xcd9a2237 0xa5fb46de 0x9ffccb44
+ 0xf10d190e 0x587966c0 0xc51151f6 0xadf04413
+ 0x3d06c31b 0x04ee4955 0xc8e0c658 0xc18cf4b3
+ 0xb8819010 0xca4f5220 0xe344f060 0x570b4cda
+ 0x012d0bbc 0xddd75842 0xa6785823 0x03817bbe
+ 0x0a36b9c3 0xa63ce601 0xb400ed89 0x54269ffd
+ 0x932e8525 0xe2e69e40 0xe58b54cc 0x719413e6
+ 0x7d4f6793 0x646d4539 0x697134ac 0x5e748699
+ 0x9c139a59 0x70481219 0x5dde0274 0x6360523a
+ 0xdbb51cc7 0xba4b4e11 0x963acf63 0x023187de
+ 0x7cafba20 0x720a2328 0xdfde4451 0x3f316592
+ 0x90a1cd0b 0x1efcf177 0x2670f653 0x5dc15d80
+ 0xf3f6b6ae 0x0a99dbc7 0x42fa199c 0xd007fb9a
+ 0x20fddba0 0x6a405776 0x729727cc 0xd241beb5
+ 0x68157d9b 0xe4757002 0x17213665 0x75a6352a
+ 0xf501fc00 0x1b3c2485 0x26b32b05 0x134c5648
+ 0x02a9493d 0xd09b71a2 0x37c03496 0x93cc61cc
+ 0xb540cb5e 0x97621e22 0x100e80eb 0xa1c6a6dd
+ 0x697d0e7c 0x50983ef1 0x94ade415 0x594c996d
+ 0x83adaaf7 0xcddebdbb 0x15d5084d 0x7f553445
+ 0xaa9b4988 0x7d2d6485 0x747505ce 0xcfce8f7a
+ 0x2460e3b1 0x8a9bae7b 0xef9577b1 0x9bd8aa4d
+ 0x0b39d25b 0x7ee75813 0x354d25f0 0xb3230a99
+ 0x4099e76f 0xef5294dc 0x749229d7 0x4a3628ba
+ 0xf3bc338c 0x27fdd85d 0x88710bdc 0x8019ae20
+ 0x03d2ba10 0x357d2071 0xa632494d 0x2b72e5dd
+ 0x66dc090d 0x7b4e6d16 0x5b8d04c4 0xa7188afe
+ 0x436cbfc4 0x6b06bb33 0x4ed3b64a 0x1f19f9a6
+ 0xb74c124d 0x035aa538 0x204e90a2 0x07f4a34e
+ 0x244c6e48 0x6df56192 0x98f6efda 0xf5ebfe38
+ 0xa2508e2b 0x41a8ba61 0x19076be1 0x265caeca
+ 0x5ae8330a 0x72cb54b9 0x01423f2e 0xbd26ddc0
+ 0x5cfffbcd 0x23a8a126 0x070d1b98 0x7849ee2f
+ 0x39809bf9 0xc2da255d 0xc13469cd 0xf6286206
+ 0x04077eba 0x201b7a33 0xe33b328c 0x15c3f97f
+ 0xb39eacf4 0x5d17c15f 0x206f29dc 0xa298d441
+ 0x0bc3d7d3 0x056b38e7 0x6dba2ddd 0x9215e8e2
+ 0xddb6a59e 0x82e17b35 0x58c5d983 0x7d71a528
+ 0xd9b3d554 0x4437e4c0 0x24752e5f 0x342dab09
+ 0x07976a7e 0x28aa6c17 0xfcad822e 0xda81303b
+ 0x47707d1c 0x94cb1a79 0xca4a5585 0x82db40d3
+ 0x418fab17 0x9f07d457 0x5fbf0969 0x3f6a9267
+ 0x10d09946 0x79fdb96a 0x02e3cf5b 0xcc1d33c8
+ 0x8d8b4306 0x4ea1f4e4 0xa1d6bd16 0x052652bd
+ 0xfdf0c3fd 0xd3c81915 0x31a728c0 0x713109fa
+ 0x75ade7d9 0x17f501f1 0x6a9ffc21 0xcbae22a7
+ 0x17b58e47 0x2df71e53 0x8fd029c7 0x8a14431b
+ 0xd017e657 0xe5227432 0xd60aa2b7 0x5ccf5cc2
+ 0x3637b99b 0x2fabd50a 0x253f3516 0x4c73647e
+ 0xf1c1a7c1 0xff49d9f8 0x9472bc31 0xd7ecbdfc
+ 0x13584a3b 0x935aa0ff 0xe8f1568b 0x6f2e93f1
+ 0xd0848d18 0xeaac770b 0x068d836b 0xd7cb7f30
+ 0x82557503 0xb2cc8fdd 0xb16524be 0xbee1c84c
+ 0x913f67a7 0x2cef225d 0x905c4bf3 0xeffa55a0
+ 0x17205823 0x7b33ad42 0x5eda3922 0x28764451
+ 0x6be1d259 0xdec153d8 0xdb9bd4ff 0x174833bc
+ 0x9b8bd1b2 0x752369c8 0x451085fa 0x0bcfe982
+ 0x5f9477e3 0x287b2a94 0xda780fc0 0xc0da6ca2
+ 0x41fc527b 0xa2ac493b 0xcab2f3ea 0x9a84c661
+ 0x4dc2d3a8 0x550fd8c0 0xd9d1774c 0x13777ae0
+ 0x5ba5ce24 0x729283f7 0x882e7a83 0x1c0ea2b6
+ 0xd6a25b38 0x0f14165d 0x1e0255f7 0x7086589d
+ 0x30e2c981 0x0e94cef8 0x92b2f0e8 0xb2e75616
+ 0x8c5b34a3 0xf6481b65 0x2ad413ba 0xe769ff51
+ 0xdfa4ebce 0x2b1b5d7c 0x8ce41a20 0x226d6e1f
+ 0x2892a50f 0xad3f3a07 0x65796c47 0x622bb66c
+ 0x990d85ca 0x3d229d65 0x7fd00f34 0xceda262c
+ 0x1d440bfd 0x3ca0dc2d 0x0f873c0c 0x7e58f266
+ 0x54ccb060 0x4fff4fe6 0x7b430464 0xbb021813
+ 0xc8f5afbd 0xd8c51583 0x17bfa087 0x3ab67c6f
+ 0x8a565d95 0xaf406a6b 0x512e9093 0xda8e4a62
+ 0x99e157a4 0x2f9b4633 0x9cd0dd79 0x18d48107
+ 0x4d288586 0x027c2541 0xc8e11802 0x9853a6b8
+ 0x174e39e2 0xb7661927 0x6edcde3c 0xe7d5b097
+ 0xbc01e85a 0x37f13dd2 0x8acca432 0x785467fa
+ 0xcb0a7227 0x13aa06fd 0xce63951a 0x63aeddb9
+ 0x60f5e939 0xeac8b8dc 0xad7c32ec 0x29bc00ad
+ 0x4a208a62 0xa5cd0c01 0xb7e6e14a 0x74b93978
+ 0x0cb98aed 0x1acf90d1 0x30a12963 0xe2faa3bf
+ 0x8a38e084 0xb506d79c 0xe9f5a398 0x49a1dc43
+ 0x649fe466 0x71fb0bd7 0xd37054ea 0x99eb2046
+ 0xf98bb913 0xa66dd966 0x3bf533d8 0xb90c0d94
+ 0xf10a44bb 0x4e24b124 0xab972198 0xb1c067e6
+ 0x51b5b660 0x25599615 0x7fb78acd 0x1186fb6f
+ 0x2e298a6c 0x64759710 0xea6346f4 0xd95be20f
+ 0x9dfacc80 0x54840473 0x20e25fd8 0xf477b617
+ 0x95108065 0x6853d6d5 0x934059ef 0x98ed024f
+ 0x2b9ab13c 0xebabf08c 0x455f3ccb 0xe16795ec
+ 0xee4f37ac 0x58c23de8 0x605bf91a 0x820606af
+ 0x49780126 0x3de6f2b2 0xd7163a54 0xe37fbd12
+ 0x42dc4ac8 0xa9dba6a8 0x2a52e044 0x6a3cd755
+ 0x0a50bd7e 0x7381e5ec 0x6113300b 0xca9ef1c4
+ 0xfcbf9fb1 0x02f2fe14 0x14ef8d92 0xaf3479f5
+ 0x5476e6ad 0x60f8a51c 0x9a48294e 0x6374a21a
+ 0x3aa905cd 0x0b7dfd0f 0x8c732396 0x32feb8e9
+ 0xa6f6b561 0x53b12131 0x3c33d3ab 0x9d21a63c
+ 0x47f0bf5e 0x2724a54a 0xaf9e8b13 0xdefa0851
+ 0x4642ee69 0xd1c53770 0x96ae6df2 0xcdec381d
+ 0x66cda20a 0x3118ab96 0xb976b2b7 0x26edfc39
+ 0x55935013 0x9fad6ed7 0x45828ac9 0x226cff75
+ 0x0fed2634 0xa1d814ba 0x072b1f47 0x8fffb2ce
+ 0xa09a6843 0x530673e4 0x4859b9bf 0x8187a24a
+ 0xe27981e0 0xe8f391d9 0x32589e20 0x37da379e
+ 0xad59afdb 0x183cd4d3 0xf7469108 0xbc628572
+ 0x7551944c 0xfee39d3a 0xde1cd9ea 0x7ef53855
+ 0x5d2b7e29 0xa62cdacf 0x1adb5a78 0xa40b54f7
+ 0x9668c5e1 0x191e0c4c 0x93a121eb 0x09531f1f
+ 0x96ba49f4 0x2d1e896c 0xba78f90a 0xece1583e
+ 0x6c15bc44 0xcf8f520a 0x9a9e83ad 0x9b6b6c7c
+ 0xbff862a2 0xf17c48ed 0xcc40b386 0x75379aa0
+ 0x6fcc78f9 0x5ee6d91d 0x60e2881b 0xc5a50f2b
+ 0xb0e21c76 0x77293b3f 0x4dc3c125 0x71e5e326
+ 0x752180b6 0xf6966af7 0x96b13f47 0x842f1470
+ 0xd3cebc0a 0x23931ca2 0x9fa82e41 0x1569625a
+ 0xab11f0fd 0x0dabfc2f 0x4f499d06 0xdf2f551f
+ 0x1d59c866 0x228b7c5a 0xcb5c338c 0xf779d337
+ 0x5661e179 0x57ee6674 0x92c67b12 0x2ab20094
+ 0x86443609 0x96c11603 0x52150c42 0xbe7a1a0c
+ 0x417323c5 0x8f535a20 0x0ee45abc 0xd831b3ab
+ 0x4b56c35e 0xadfca903 0xdb953e87 0x06c100be
+ 0xccd4e5a1 0x84b1eb7a 0x740cce47 0x61e9a67f
+ 0x873b3e77 0x7dbb260e 0x2837cadc 0x2f253b42
+ 0x7afe427a 0xe8ec3710 0x5900dbbc 0x2174e514
+ 0x84ea376a 0xdd3e79a3 0xa567abf1 0xdff5891f
+ 0x4b88082f 0x70d28e4e 0xb265f970 0x8fa57c8c
+ 0x6fb84267 0x1ffed689 0xc8dfaf03 0x593d6750
+ 0x5c96ee39 0x0199636c 0x415fb6c2 0x77ab0c5a
+ 0x7f3d0014 0xb51ef843 0xdcc02ceb 0x75cf2a1a
+ 0x675e057e 0x6fd4b8e0 0xc35c810a 0x0263e828
+ 0xb3b38e6a 0xeb6f1904 0x38e0e3d5 0xe56c97cb
+ 0xb9ab05fe 0x7d00aae0 0xc3e2f290 0xd17b0539
+ 0xab6b0d3c 0x01949b89 0xbde6d45a 0x3ea48534
+ 0x2585b3ae 0x20eaec0a 0x12165161 0x81eb9e23
+ 0xbf087042 0x769a37d3 0xbee94e4b 0xd82d0346
+ 0x95284516 0x9cdd530b 0x610188a3 0xe1cb1a84
+ 0x201023e8 0xa2b51aa1 0x5f793de7 0x7822f6b7
+ 0x3415fd61 0x80d0dbd2 0xeaa0b1d0 0x0647a151
+ 0x37a04153 0x64dd9b5b 0xbea43949 0x7ffc6b1d
+ 0x3ec171d9 0x16399842 0x0d539e5b 0x168772af
+ 0x50528a24 0x1ba46948 0x4d1c7622 0x7eabb87b
+ 0xe1f28f53 0xedfe9f50 0x0882e6f4 0x0b0e858c
+ 0x53202809 0xdd40481c 0x98f9548c 0xd305e7f4
+ 0xaa3a3b82 0xf5dfbd5a 0x7f3f0103 0x68d7e48a
+ 0xf9cbe6ec 0x0aaa6ce6 0x983430db 0xa93473f0
+ 0xab4a9fe8 0x5967af5f 0x2e4a1aad 0x0eb753b9
+ 0x5252c78f 0x20cc9e56 0x6d7d06b4 0x01ed2c54
+ 0x7458f014 0xc472083b 0x5ebc4b2d 0x11938115
+ 0x5609a0d3 0xcfccc47c 0x44c7215c 0xf87411c1
+ 0x22a92265 0xd2b00607 0x033ba680 0xb4ed58ed
+ 0xc58e4a87 0x60836e06 0x9eaff4fc 0xa0528e78
+ 0xfd20b0d3 0x02356e10 0xa047e404 0xa9283593
+ 0x54cdff7d 0x3eb1403e 0x9f4a7f56 0x670a19e4
+ 0x497d4c90 0x7d4b5b52 0x240ad44f 0xa8d2f730
+ 0xae53e947 0x566c963f 0x109b6ca8 0x27dd1a3f
+ 0x2c1c5ef0 0x796228e6 0x24220a88 0x008e2bcb
+ 0x74d45ba5 0xce0484fb 0x8160be45 0xdc3b4bb5
+ 0xc1cc6e3d 0x1f692d98 0xd4387a6d 0x6efc2aab
+ 0xdcad07eb 0x95be0966 0x58b6c364 0xc23613b5
+ 0xe911e2c4 0xd323a52d 0xba9a0937 0x026db7a6
+ 0xdcb5253e 0xc4d75876 0xfe7c5882 0x70cb8faa
+ 0x8fd4396f 0x71f19b8a 0x5c6d8137 0xaf3c55e2
+ 0xe4fa5eaf 0xb489bc28 0xe4059d20 0x7f776f27
+ 0x418d7e67 0x0560dd23 0xddc8a9f2 0x5d24cfc9
+ 0x9e0e807d 0x1baeba2b 0xd4085729 0x95604427
+ 0xa1b82a01 0x9ebf78b3 0x7da9a0bb 0xebad0bcc
+ 0x876ac5f0 0x50f5e56d 0x35bd1ac5 0x33ce5e78
+ 0xd0796806 0x28523eb0 0xe0e25542 0xd89e9c2f
+ 0xf6aa4a94 0xd9843f54 0xde1c58f0 0xa43b7439
+ 0x438c402a 0xb29e8468 0x2d8b8b39 0x3ac583c5
+ 0xad2624a0 0x2e57fd2d 0xbf4fd6b8 0x8f86a6ad
+ 0xee7b10ce 0xd6a0ff5c 0x796cc316 0xe9592c97
+ 0x78fb0448 0xeb7142a7 0xc23de330 0x510681d9
+ 0x34034a90 0x535cc5d7 0xbaafd38c 0x5d11e611
+ 0x58c99b2c 0x2eb95f00 0x8db62076 0xf49d8396
+ 0xae6f906e 0x7ac672ff 0xc82f6f2f 0xe04071c7
+ 0xc60fb70b 0x2d0065b4 0xc7dc4d8e 0xe5386450
+ 0x45de7648 0x4d9d9ed5 0x1ea63c26 0x7e65c525
+ 0x5a3aa43d 0x68d8ad03 0x125edc7f 0xe444712f
+ 0x04f20274 0x8e892ae5 0x790c0141 0x3589a296
+ 0x6615472c 0x923399e6 0xb796db99 0x36b70376
+ 0xfa59ef8e 0x580ed43f 0x770c41c8 0x0760ac46
+ 0x76755f0a 0x55272e71 0x64778d44 0xcc8e527a
+ 0x0863f548 0x2b42f2c5 0x20756bcb 0xf1753f6a
+ 0xaab7bc8d 0x8d58c65a 0xc2292ed5 0x92f5f173
+ 0x0ff9fbe6 0x805f2512 0x617a5b90 0x92532577
+ 0x152d0a3b 0x51c6273a 0xb467eb12 0x973aa5fc
+ 0xffd5fe17 0x9def8fb4 0xe5f9ee6f 0x3050215b
+ 0xa6c512c4 0x95fc2825 0x56b9c86a 0x296ff9f7
+ 0xd5bbd16f 0xfdd6408f 0xcab0ce03 0xa3a37242
+ 0x6fbc45d8 0x528f4f44 0x195c3aa5 0x3df1ddfe
+ 0xd705871a 0x6d525fdb 0xf2f0177b 0xe856b5f9
+ 0x5a62fb0e 0xa10c6b11 0x76c4de6a 0x620929d3
+ 0xc74465cd 0x70d6eb66 0xc789cff7 0x9b40ec8c
+ 0xf8d44b90 0x89467100 0xbf5de474 0xd93ffb76
+ 0xa77e0fd6 0x9a6dedf2 0x7a4b5bff 0x4353cc95
+ 0x19ad6141 0xe93efcc1 0x63716258 0x5dcb90e0
+ 0x216ed316 0x38e053f7 0xb2d11a29 0x401fb696
+ 0x0f60ff0a 0x59c96ce3 0x41ae78bf 0x11293802
+ 0xe2140131 0x06b3aaed 0x945a8a4d 0xbdc051cc
+ 0x12a396f8 0x86c84c40 0x2398465d 0x90831319
+ 0x4d8b474e 0x31edf74a 0x68605ffb 0xdbd5aab4
+ 0x03a20ef4 0xcb578309 0x55cf8de4 0xeb63cc3e
+ 0x77b6e657 0x9064c204 0x7e508ca7 0x51f9cc07
+ 0x2034a87f 0x9e8d6363 0x2347348b 0xb33811f8
+ 0x61059c50 0x6644040c 0xbb47186a 0x0b39b8a5
+ 0x719a5cb0 0xf6039950 0x890dc3a5 0xb2c3e909
+ 0x843ba28a 0xeeb824c6 0x0b0fd3c8 0xa0ae5b58
+ 0x5fc0fbad 0x869e0f43 0x8157a6ce 0x012ff9e2
+ 0x7aa0588e 0xcea70c7e 0xdbeb31a2 0x1cdc813c
+ 0x58772a19 0xd6ef8b39 0x211d0c2b 0x521336f3
+ 0x0748e0d6 0x31180d54 0x17f2e391 0x7b200851
+ 0x12a76efa 0x93584a83 0x59a26d00 0xf443aff8
+ 0x3a6c1c64 0xab949fb1 0x54bb06a5 0x818d1d12
+ 0xc69783c8 0x6effa0a8 0xd61c0c05 0xd76d617a
+ 0xf89c3b36 0xbbf2c9e4 0xefd5e16a 0xf239e70b
+ 0xe124dcf9 0x0ce35a7e 0x4e5de898 0xe898bb85
+ 0x0eda9543 0x189bb85e 0x3237d51e 0xa81afba4
+ 0x50e5417c 0xadfe8513 0xd00a97c3 0x7942e79c
+ 0x45a3f95d 0x38c92d7f 0x66b0fa65 0x88f34b2e
+ 0x945e83de 0x6fd718fa 0x09988ebc 0x185afb1a
+ 0xa4bc09ab 0x763ee195 0xd565b562 0x513d30cc
+ 0x4eca27db 0xab95cb61 0x797f0ba2 0xd1d17c13
+ 0x7fbdcbc0 0xf2680538 0x8b7d8039 0x545a92be
+ 0xf7e5dc0b 0x17ff40cb 0x91b1aaf5 0xa65cfaec
+ 0xe4b88f59 0x5d4a3d52 0xf649b8a7 0xe2d5240a
+ 0x5e4090d8 0xe8ceb64c 0x5e7604a0 0x87e50b84
+ 0x78baa4b7 0x8a134528 0xc130aa24 0xbadf6b92
+ 0x3996d321 0x13d44664 0x6c30618f 0x9546bc58
+ 0x440b2d80 0x4ab82baf 0xe605672c 0xda1e84c7
+ 0x0436c4e8 0xf1726cd4 0x380df7f4 0x76cff6ea
+ 0xec52b439 0xbd0acfa6 0x4a66c6c1 0xee77b3c8
+ 0x305e5ad1 0xe3df7a5f 0x6d3ca452 0xe2f0bb6a
+ 0x20aca9dc 0xff5f2785 0xaf1d85e8 0xd4c55653
+ 0x52bb24e1 0x54d928ac 0x07cd70ee 0x39274492
+ 0xf7baebc4 0x65071bbc 0xb73a6304 0x2a18402c
+ 0x04e85d51 0x0eb01c76 0x6f73e255 0xd392e3ab
+ 0x31ab0616 0x9ab8ba65 0xab2a2eb9 0x34934a78
+ 0xf8561348 0x2f6642b1 0x30261a32 0xb2a6c09a
+ 0x4a420e88 0x33557453 0x19bda003 0xaf4e76ba
+ 0xed9dc685 0x604c61a9 0x9725b972 0x329201c2
+ 0xa9b4b087 0x5e06c74d 0x9628fdb1 0xe6dc0d04
+ 0xb18577fa 0xa989c3cc 0x5b299fb7 0x36aaa3cb
+ 0x6b39a761 0x25bdf05f 0x7b7c71ba 0x8265ae16
+ 0x403fe456 0x96ec45f1 0x087b5470 0x217e734d
+ 0xe65c9541 0x688d43f3 0x5bcec90f 0x80e971c0
+ 0x62f76d35 0x5f9030d0 0xacefa05f 0x64ac9810
+ 0xd6667793 0x35f8565f 0xf7247bcb 0xc34e0feb
+ 0xcae60e22 0x728fffe8 0xcf6a16ce 0x8d4fac73
+ 0x8ad230fc 0x987257c0 0x8c7a1da5 0xa7dbda8d
+ 0x3c09c385 0x647f2867 0xf0b3b5dc 0x781eb0e9
+ 0x6244d05d 0x337bd6a2 0x77dd9e28 0xc48c5512
+ 0x883e4cfe 0x66ad74fd 0x1f659c37 0xd65bfb11
+ 0xb2389cda 0xdfdd6141 0x28888c3d 0x2e76ac3f
+ 0x7b21a7f9 0x5ceb1f5b 0x97f62545 0xaefe190f
+ 0x16fd077d 0xd558d127 0x1fe8a8a7 0xaab0dc71
+ 0x8ea4576c 0x17a8b8ef 0x7476364f 0x229b0ca9
+ 0x236b1e56 0x5c1bd152 0x20002652 0x8c0805cd
+ 0x4c122c4d 0x6cbd72db 0xa9d9d258 0x4817fa88
+ 0xc805adb3 0x227416db 0xd58adbb5 0x11cdd037
+ 0xc06e6c92 0x1c548525 0x8cbfab9f 0xa4b1c180
+ 0xffab2b24 0x186068bb 0x8983f63b 0x982997b0
+ 0x5abc10e6 0xdfd139c5 0x11c9b6e9 0x86cdfc81
+ 0x4f8010c7 0x1e1646b6 0x9d66a0d2 0x37c4239d
+ 0x8066847b 0xaadad61e 0x3eaf7caf 0x957e015c
+ 0x4d78bfc3 0x15c3fe27 0x6c2d2fc5 0x84af2a8b
+ 0x59a66a0b 0x3e13f346 0xe9874a62 0xa7446843
+ 0xdecfe92c 0x120cf098 0x1d188cb6 0xa4938e5f
+ 0x9023d7e1 0x8bbdb7db 0xaf452ce8 0x6854d9e8
+ 0x0604f218 0xd39c3237 0x3754ebaf 0x4ae59d90
+ 0x3913e367 0x99b1902a 0x78c06ff6 0xc177a4a5
+ 0x218159ad 0x01ec7cd6 0x5a6bda31 0x9a753f92
+ 0xecad36d9 0xa2216cdb 0x4fc8328e 0x879ac7be
+ 0x23f3f907 0x5b59fad8 0x122a1644 0x16e63209
+ 0xcfc827a1 0xfe332476 0x2b72bb15 0xd478caf1
+ 0x21deb5e0 0x3c1a561e 0xb59be4e8 0x4598f63e
+ 0x20194b01 0xb4d76ed5 0xb58e06d8 0xb1219a36
+ 0xdefe3946 0x0731248f 0xcfa09f93 0xe420d6e6
+ 0x8a0518ba 0x013d8f80 0xd32a05ed 0x7d9d8209
+ 0x548cb1d4 0x69457a2c 0x668a0a70 0x8cc2b661
+ 0xb72d4ad3 0x19b388c7 0xb844dd6f 0x4dc39493
+ 0x7e96565c 0x53959236 0x1dd4a349 0xe50914a5
+ 0x319844c0 0xddbb2abd 0x2f126ba4 0xa46c6d63
+ 0xd6829c4d 0x8f178677 0x8ae6291d 0xb5660702
+ >;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9082011>;
+intel,processor-signature = <0x306a4>;
+intel,checksum = <0x7e23e5af>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200809 0xa4060300
+ 0xafe5237e 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x07091120 0xd1080000
+ 0x01000000 0xa4060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d
+ 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x71f0ab19 0x85635e57 0xfecdeb36
+ 0x7c93f457 0x13e3fb92 0xa512551d 0x6ac10509
+ 0x423fe38d 0x778481b6 0xff413c23 0x534d1d6c
+ 0xade61b9c 0x8cc43e62 0x0a8e5091 0x47382579
+ 0x8ee1d885 0x370915dc 0x8d8274f9 0xff11ba81
+ 0xb0919d7d 0xac434821 0x46d13494 0xe7fcc12e
+ 0x37876ec1 0x67a67b02 0x8d80b952 0xa2bdb26e
+ 0xf19c0c77 0x7b1f5296 0x544fbc2f 0xa8a3b1de
+ 0x8285fcfb 0xcab6dcc3 0x2a63f8de 0xab28edcf
+ 0x86e0e1cf 0xc21e5137 0x04616818 0x3172cc2e
+ 0x4a472e10 0xea8d7f3d 0x7e225494 0x7df2be43
+ 0x8a86b11c 0xf6894a26 0x81b6df9a 0x967c4076
+ 0x8c3e7b47 0xf81709e7 0x8bc622d9 0x4ed8aeae
+ 0x7cc696b5 0x45fb131d 0x77f322fb 0x4801173e
+ 0x056db13d 0x9a64fc3a 0x1508afa7 0xbb357cd3
+ 0xb863aa72 0xe57b932d 0x30892535 0x56a5e167
+ 0x842d402f 0x3113bd4c 0x04016ae3 0x7d81c983
+ 0xdeb79060 0x950e14e6 0xab7833c9 0x297e8abe
+ 0x49252831 0x489acc6f 0x9ed63fab 0x3166416d
+ 0x97319343 0x28ad40d7 0x3fbb9b52 0x203c7460
+ 0xe03bf6a8 0xbe288f65 0x8183b5d7 0x3752814b
+ 0x57405958 0xb4b3ab8d 0x235ba207 0x20bf3240
+ 0x9ea6da77 0xb8f77bf6 0x83d7ce90 0x5575d3de
+ 0x21f46a2d 0xaba56e91 0xb5657416 0x6ed3bce3
+ 0x1cf28b50 0x7e3f8573 0x76ed8028 0x8c785c22
+ 0x5a0fec15 0xbec7ac15 0x3763a0c6 0xd0fcfcdb
+ 0x39581ba2 0x386e0e74 0x4336b4a8 0x4bcc5176
+ 0x314b2da1 0x2ec76c38 0x2a517be5 0x17ce6f78
+ 0x7f124d6b 0xc68ce86a 0xac7d29f3 0x7ea7cbd0
+ 0x053169e4 0x4c0d5e6c 0xe39aa81a 0x083a39bd
+ 0x6d71ce68 0x7c50cc9b 0x10aa72b9 0xdd11c952
+ 0x43bea88d 0x9c1ddab6 0x41b013af 0x1e98de66
+ 0x554b92a3 0x86bac233 0x50fae8f6 0x358742c8
+ 0xa80c50d9 0xdfe9302d 0xc9b4c715 0xdb4b1c66
+ 0x78b7d75b 0xadde8aa8 0x59c09d74 0xa46b87d0
+ 0x548cc5b2 0xf9b8b729 0xa738e8c3 0x1c5a00e1
+ 0xd9c2d59a 0x8d1cc5de 0x05bae2e5 0x0ecdfd2e
+ 0xab3a984e 0xcf53db57 0x3ebc3c88 0x6b60e477
+ 0xa112a3b0 0x827400c9 0x9e7d8495 0xea378c48
+ 0xb19eaf60 0xdfe2da05 0x796b70f0 0x6c595e5c
+ 0xc0600c02 0x9e038536 0xea914072 0xa53e20b8
+ 0x30ab9653 0xb0bb4beb 0xce3d842c 0xb2a5cc91
+ 0xaa6f847f 0xe2aa1414 0xeede8231 0x067d99da
+ 0xa5638b21 0x27ac1f32 0x2231ada1 0x5ca081e4
+ 0x8e30a578 0x21f9f43d 0xc3b5ea88 0x1f1a9d74
+ 0xf7faba90 0x8163a801 0x09b1dcd6 0x3419385a
+ 0xd4ecb2e1 0x33e9df04 0xd5659af7 0x9eea6e2e
+ 0xf6ae859e 0x7c268181 0xaa07ea78 0x892c1c42
+ 0xe66a5fe0 0x9e7f5446 0xf18c42cb 0x49c7296a
+ 0x671484a0 0x3bdf31e2 0xed31d1d1 0xc2e8900b
+ 0x1175996c 0x70a0c04f 0x0394f2c4 0x070d9ca3
+ 0xc67229d1 0xcf29d228 0x4fd61fc4 0x92aa5df4
+ 0xa88afb58 0xb683a2c7 0x16239fe4 0x84bb685b
+ 0xb09cdc69 0x58be548c 0x99f0c940 0xa54bae2d
+ 0x108d7ccf 0x08773f13 0x4ba953c8 0xd290c27c
+ 0x9913f3be 0x8338ab76 0x4a51ca62 0xeb00862c
+ 0x03320962 0xd9bfb225 0x7e90e28e 0x7a86a4ae
+ 0x3a919994 0x91afec57 0xaef1a380 0x30ee8b2c
+ 0xb3dca7a3 0x26bb0fb1 0x36a18ed7 0xe0f1e5bc
+ 0xcd3c7b7b 0x6a3e7546 0x11fbb8ef 0x45800497
+ 0xd18d2714 0x5b2205e1 0x88903c77 0xb04c3c71
+ 0x8f52ca2c 0x3410f445 0x47847239 0x519adc73
+ 0x5e0b948c 0x0d8399f7 0x095d1fd0 0x001a43d5
+ 0xe806d835 0x199ff3d8 0x615fb809 0xa6d8aa7f
+ 0x64f3fdf1 0x6d048b33 0x69967629 0x2036eaf5
+ 0xd2514a6d 0x1719f81a 0x8030c9aa 0x3b1623af
+ 0xc8990859 0xea7d5f87 0x925fddd1 0x3470f55e
+ 0xcc4c6a72 0x4e94dba8 0x51861bfd 0xfc3aa50e
+ 0x65570977 0x615bbb67 0xd1cd8c1c 0xe8c52c28
+ 0xa4b1b599 0xef092f99 0x38c67c4b 0xa48b1fb0
+ 0x34bbdfee 0x162a0308 0x0118df20 0x839c54dd
+ 0x30c28bc9 0xd195aab6 0x14eecbfa 0x5292e262
+ 0xc4d26048 0xc8a7f725 0xb5be922b 0x540c734a
+ 0x12c53607 0x84a598b9 0x7c8418f2 0xe70c82dc
+ 0xa5f9f219 0x7023a821 0x7223e7ef 0xd63c008e
+ 0x29ddf8f4 0x586ac4ea 0x8f734809 0xbf22ff2d
+ 0x1c9b1aef 0x4249d5db 0xc4140c09 0xc927aae3
+ 0xf6c17d0d 0x822bd729 0x1ea56fbc 0x941240f4
+ 0x93a2e220 0x8596eba8 0xb9dc285a 0x58343237
+ 0x649f47b3 0xc214fb8a 0x1aceb84c 0x8a311f8a
+ 0x408e4b98 0xd0401a07 0x99fe7a30 0xdba70218
+ 0x6eabcecb 0x963f4937 0x4c980ab1 0xb1700cb8
+ 0x8762c553 0xed8d7267 0x96ef21bd 0x851452e1
+ 0x0cacc88c 0xb6320bf9 0x2c99e72e 0x98acaadf
+ 0x19c2f27d 0xe6a43a58 0x3b516fcf 0x643305c1
+ 0x28a991c1 0xcf0b9c6f 0x061e8030 0xcf1faf5c
+ 0xf5b441ce 0x0d00231e 0xab56cb21 0x28b7f4a0
+ 0x4fc8e58c 0x4860d87c 0x4b96bbdc 0x73f35c76
+ 0x81cb09f8 0xd80735f0 0x3dd494f2 0xce4517e4
+ 0x4c314ae2 0x4233cb18 0xf737b84b 0x1c745c08
+ 0xe0645e41 0xe716ddb8 0xec3c7c0f 0xa3667da4
+ 0x63533172 0x46598306 0xd34def1a 0xdf443342
+ 0x517cb001 0x917ed9ae 0x0d3070ab 0xf3d0431b
+ 0xc76ab146 0x7967163d 0x3f645862 0xa98a3610
+ 0xb17ec8b9 0x8809d7a3 0xbf98ab84 0x6addf0b7
+ 0x4a6ba3a0 0x4d377e62 0x5c13c16d 0x0657b882
+ 0x24bec841 0x639f476d 0x497db8cb 0x973ac543
+ 0x34ca0aa7 0x2033f4a1 0xf055d2ac 0x4f1e0605
+ 0xa06d020d 0x7e9d7b25 0x24dcf595 0x088c88f3
+ 0xcda1d4e5 0x2b9f9f21 0x4cebb038 0x4bfbaea5
+ 0xd51e9298 0x26dfd44d 0x419d2259 0x6b90a88b
+ 0x698ab356 0x78e59c8d 0xc9587560 0xe89547c6
+ 0xc92b0c0e 0x77a364ca 0xa7fb6e72 0x9e5f2f9c
+ 0xa825edb8 0x75d8d49d 0x227c61d7 0xbe75e877
+ 0x992628bf 0xcb5d570f 0xd55cb2a0 0x6b8ed5d0
+ 0x196f54bb 0x17d433ff 0xb089401a 0x89206c8c
+ 0xd2c5daef 0xafff07d3 0x07d1adf5 0x49b27ca9
+ 0x2e39157a 0x9bd214a3 0xe2409115 0xcefa1c6b
+ 0xdcb07810 0x41261e2e 0x665dfff2 0xbb315742
+ 0x65ef7d13 0x70b21c29 0x74507dd9 0x129c0ed9
+ 0x0ae1742a 0xd73c61ce 0x1e190eda 0xf74e3d06
+ 0x038fe01d 0x556d513a 0x3fcdaef6 0x6586fa4d
+ 0xd2d7e6ca 0x7e2e933b 0x120fa46a 0x894987a4
+ 0x4d5799f5 0x317bed63 0xeb8b2be3 0xcc927633
+ 0xff655d06 0x7535f440 0xb3281970 0x0f792db6
+ 0x53cde6cf 0x0db39a6f 0xef9eb25a 0x5e39ff58
+ 0x116b6c76 0x6faa29b8 0x9636bac1 0x42b9db6a
+ 0x5e1087f0 0x50cb3c88 0xbeae0ba8 0x5e2c536a
+ 0xf7817f0e 0x68a23d7d 0x4e5f95b0 0xb0c8d3be
+ 0xe765577a 0xe7f14c38 0x5cb0e2ea 0x6c760e04
+ 0xd4f00923 0x761dadca 0x26b3b752 0xfddd725a
+ 0x7a2d788f 0xd8895f45 0x26e4bf89 0x65f14803
+ 0x0d2e9b48 0xc3f70c99 0xf2c361bb 0x0623ca36
+ 0x1da1dc4c 0x5cf46bbe 0x5936d951 0xf3c7f826
+ 0x9fecfbaf 0x7461ab85 0x0d544474 0xe4120a8f
+ 0x569d033b 0x948b12e3 0xdb41b453 0xe9762a09
+ 0x7f2ded9f 0x6c25dc18 0xd2acdbbf 0x23ed04a8
+ 0x3b56bc43 0xbfc5d268 0x2fd5c405 0xc7b2ea06
+ 0x5a546023 0x30e9040a 0xe3c7722d 0xcf4ca6f4
+ 0x5f32c333 0x32f07d3d 0x45b9d4d6 0x9c41af5f
+ 0x5ee9a9c8 0xc3e280fa 0xee575013 0x04e0607a
+ 0xdd94800f 0x8292d93a 0xff10e469 0xcb706918
+ 0xdaa9276a 0x4d91add9 0x8e1ebb82 0x67452108
+ 0x49b22b5d 0x70b810a6 0x4497d9b4 0x86cd0335
+ 0xa691d65e 0x824db77d 0xeb09d413 0x9b723ebc
+ 0x896dc436 0x64780810 0xc5e34ef7 0x4f108f18
+ 0x8b55065e 0x4ef522ae 0x2c781bd0 0x32088deb
+ 0x2e052408 0x9b78cbec 0x4aed1bc3 0x31db2739
+ 0x89eb6695 0xf3df3627 0x576645df 0x123cff77
+ 0x1acb1522 0x246e719e 0x8baa34cb 0x6ba43aea
+ 0xfb057ac3 0xc87040a4 0x3d3ab58c 0xe9442e38
+ 0x89ce6ecf 0x3fa669c7 0x58919e44 0xa08a2e58
+ 0x8fd1fa50 0xc087b003 0xbfe787e3 0x5678b75a
+ 0x911fb37b 0x9942a375 0xcffeac92 0x24388c2b
+ 0xfe481ed2 0xf6e322dc 0x48cc215f 0xafdcd948
+ 0xbcd97425 0x655694bb 0x970a5b10 0xef8c398e
+ 0xb8171bbe 0x99e739c6 0xe169b100 0xe56c5c42
+ 0x8190cd45 0xf8d2b2dd 0xe1e981a6 0xc0c2aaf0
+ 0xc5c0baa1 0x6ce19d37 0x839d230a 0xfb84b2af
+ 0xf52b9069 0x903c39b2 0x97c52d92 0x71d78be4
+ 0x9bbb12c5 0xaff3990d 0x575fdc6d 0x7e4317d7
+ 0xdd1f9b49 0x24903168 0x2007fa4f 0x4abe4f6d
+ 0x263e39fa 0xb7e24055 0x93265f6c 0xe183e382
+ 0x2b19046c 0x185632e5 0xa024df44 0xdc7b6a40
+ 0x31c97b5a 0xd1db7afb 0x7ff27636 0xbdf79391
+ 0x5148a6c2 0x9fcf91f6 0x814f4f72 0x5a60d42e
+ 0xed3f9a1c 0xbcc0fafb 0x262ffcc6 0x041f2aa2
+ 0xa9bcdfac 0xc5897711 0xf39b154b 0xe8bb2687
+ 0x68c411aa 0x67e3cbc1 0x544ddb04 0xd248c866
+ 0x9b107e9b 0xff6b8cd8 0x94dd2262 0x1a7dd15c
+ 0xea03e879 0xf534244f 0x84485354 0x35225d96
+ 0xb58c8b19 0xc64cf0e5 0x7305411b 0x80770715
+ 0xbfc71f00 0xb962ccc0 0x21bdf0e2 0x048bda12
+ 0x2102ac9e 0x64e889d5 0xbc30eb49 0x03eab004
+ 0xabe124a3 0x58a41ae7 0xd945ba34 0x7d485b3b
+ 0x013ccf7f 0x487df444 0xae74b9de 0x4828972a
+ 0x97bd1ca2 0x28c64e58 0xbee11d3f 0x347652c7
+ 0x37814af4 0x99b7adc4 0xf6ebab70 0x07aa21ff
+ 0x64174862 0x467de331 0xb6a88187 0xde63b3c2
+ 0xcaec36c8 0xbf4f3de8 0x9bd70e15 0xdf4b907c
+ 0x640f2594 0xfaee60f6 0x9480c381 0xcb4e0996
+ 0x03b30491 0x055c512e 0x512e5b67 0x3c0c5209
+ 0x84c9c0be 0x069907cf 0x49d4a871 0xe5fd978a
+ 0xbd7ffb3a 0xfaf9643b 0x119bd155 0x4eebc032
+ 0xf12cfed1 0xae23dc3d 0xbf9472dc 0x0c9f240e
+ 0xa376c5b3 0xbc168e61 0x715ee9c8 0xf0d3bf95
+ 0x951f938c 0x17a1b2f2 0x998b2c63 0x5f6bef20
+ 0xc364fb8b 0x90d9863f 0xbb65674f 0x9cf94066
+ 0xf4a43b1f 0x9e5f0a13 0xae62623c 0xf445c858
+ 0x4021ed28 0xf1562704 0x0e1c1596 0xe9cd23ee
+ 0x28131eac 0x5406abd2 0x7f599eb8 0xaf471f70
+ 0xd275f6dc 0x5ff75a54 0xa82c13b9 0xa2b0a583
+ 0xbfaffd3c 0xac5342f4 0xf0e1963c 0x993dbaae
+ 0x3d0cd111 0xe9ee6ce3 0xd85f5004 0xec8f711a
+ 0xafcfb6f2 0x6926e1c1 0x0f1a5e40 0xc002ec74
+ 0x83344203 0xffdacd7f 0x1f2efcc1 0x8b511582
+ 0x013cb6f8 0x7781d777 0x4aaaab9f 0xa2223fd6
+ 0x07c2557e 0x27ca061b 0xbe94f543 0xfa94ff76
+ 0x03ab13b7 0x69bf8a84 0xbcb641eb 0x5e89208b
+ 0xc4e51876 0xd58dd9be 0x4ebdf2ac 0x14b79754
+ 0x8cc79438 0xb6d37437 0x6b843097 0x0d11bde4
+ 0x2ef0fd04 0x788b3007 0x6feca051 0xe147b98e
+ 0xa6b9139c 0x9446b26d 0x4920adab 0x7cb94980
+ 0x5ff17b2b 0xa22b81ea 0xce5e999f 0x7d4173ac
+ 0xd99aa4fc 0xebec0bf5 0xf10d6c52 0x5d97f82c
+ 0x0738353b 0x208e43a6 0xcec8ddb3 0x999847e8
+ 0x10d94541 0x68d5c5a2 0xee34f623 0x86536280
+ 0x4f4e5bc0 0x4e569e0e 0x4c7d1738 0x427d42c3
+ 0xaa94a27f 0x8bfff36b 0x036d1073 0x2ebe67f1
+ 0x85f8e9d5 0x6b7c5425 0x4ef72dc2 0x8b89450d
+ 0x20011c1f 0xebd91d71 0x16c0ba50 0xd7c10f19
+ 0x46c9ca67 0x23787788 0xe8175e53 0xebe05e52
+ 0x3303af3f 0x6b058a55 0x3f960abd 0x8d362407
+ 0x33415c6f 0xdbad54d0 0xfd473812 0x9394e4c2
+ 0xac3c803a 0x489113cd 0xeb749070 0x4f813729
+ 0x1f83102e 0xda39d44d 0x2f995892 0x178549e4
+ 0xaa04838d 0xc08bc6f2 0x8e965361 0xe5633efb
+ 0x39927e9f 0x5c7d5014 0x783f5048 0x1c872f55
+ 0xe41ba625 0xeacfc296 0x1e1202d9 0xde9fa0a6
+ 0x1dac6dd6 0x6eaa865d 0x09f40fd9 0x9c8d9647
+ 0xfc8e6645 0x77626236 0xc61d1276 0x59948fa3
+ 0x0296fd66 0xcf07611f 0xc27022bd 0x34aaa9c9
+ 0x0ad7b71d 0xb13ec602 0xabd244cc 0x3d3387f0
+ 0x5a9f9fbe 0x11e4971d 0x38f0a9b2 0x44bc7933
+ 0xaee55dfd 0x9a5c2137 0x8d3a85e0 0xf748d910
+ 0xe25eb57f 0xb3dbafe4 0x386b0f20 0x767872b5
+ 0xfd675769 0x34ba841f 0xf7604e1a 0x99572947
+ 0x72fcc0ed 0x8f914e81 0xebd404de 0x29c263bd
+ 0x10978d02 0xea57338e 0xe7aa0d47 0xbd4a124d
+ 0x4fd7185a 0xcbf7f9c2 0x567f4318 0x96b1858b
+ 0x0f24fc24 0x7ac200f4 0x688ad1fc 0x8bc3b74d
+ 0x275ae45a 0xd4dcd957 0x4898351d 0xedd41253
+ 0xce413d09 0x11df9297 0x4ee35a8a 0xb3e506c5
+ 0x6f43f262 0xf7cf6cb4 0x7c87a2c3 0xcf4b7cb4
+ 0xb7f72f04 0xc21d35bb 0x570fa807 0x4a500ff0
+ 0xd157fa61 0xace9ab6c 0x66b98d3f 0xdd59c459
+ 0x5a8022fe 0x72122376 0x507806be 0x73e4b7be
+ 0x4a88e7eb 0xef72d6fb 0x57ead7d1 0xb7a2eb21
+ 0x327830ab 0x874e0b86 0x17c27b5e 0xdf7fe64d
+ 0xc07f158e 0x506a5a1c 0x8e2ef0ad 0xeaeddcfb
+ 0x76d5d48d 0xf20a01de 0x62454d95 0xc5ee387b
+ 0xc3b17190 0x00136ccc 0x988abbd8 0x57c6ad77
+ 0xde70f835 0x01fbc472 0x99b4822f 0x00fbf0bf
+ 0x6e919c0b 0xc5fe1ed5 0x5ff3ae66 0x5d42c098
+ 0x59bd5712 0xb06fc973 0xb6093014 0x5461dac8
+ 0x3139ddce 0x55f239e6 0x55541931 0xf184d3f8
+ 0x1127627c 0x7e1b4676 0x3ab1d112 0xad8c4549
+ 0x01170df7 0x62e25822 0x551824ab 0xb2f82a7e
+ 0x15544a0f 0x24fbab9f 0xe3675302 0x89dde28e
+ 0x6dce0a37 0x3dd7b171 0x8d04e91b 0xdd8d2640
+ 0xab0db01b 0x166f8408 0x3a4dd9b1 0x0f6e0e71
+ 0x4f322f5c 0x39343841 0xe07bca48 0xaa135ce5
+ 0xb12211f2 0xabfccdf5 0xebf7f510 0x6773c043
+ 0x763601cc 0x0a49fa28 0x9a7f8f6c 0x8e1b8ef6
+ 0x41f434c9 0xc673a8d3 0xdb67ca50 0x784cc5bc
+ 0xb4339d90 0x1b331afb 0x0419b04a 0x76983ccd
+ 0x2f4d56cc 0xbd1b0920 0x605f7579 0x95b26082
+ 0x5d1af353 0x9aa19300 0xacbbfd43 0x71d1e615
+ 0xf9037ea7 0xa14464f4 0xac987389 0x113ad6f6
+ 0x9ca375fc 0x98fd00a9 0x7707ddd0 0x5678ab5c
+ 0x1c6ad080 0xd8c1e89e 0x2c71d71c 0x074f1a5b
+ 0x759a03b7 0x96534362 0xbb944132 0xb55e5eae
+ 0x4bfccb91 0xa24def46 0x591d5740 0x94c6b99d
+ 0xfb2074f0 0x494e6f1e 0x52ae5274 0xe1d49c1a
+ 0x92f03134 0x1759bf52 0xc392bce2 0xe6c2c774
+ 0x521055c3 0x18329921 0x83308d98 0xba7b3f54
+ 0x704d6822 0x24e562f1 0x494a8992 0x3183e726
+ 0xef86b2d8 0x79b3fc8c 0x56eab200 0x8602ae41
+ 0x900a3613 0x5100f884 0xe216a6eb 0xe227a887
+ 0xfe9fd01b 0xf3ba709b 0x5ea4d2f3 0xfec8ee3c
+ 0xeddf6d69 0x0d6bc870 0x94c1b0d2 0x21686063
+ 0x375dba2f 0x0865ab2f 0x01628907 0x170ab107
+ 0xe909ef36 0xe9c260dd 0x2522609c 0x9a5956c5
+ 0x1e494cec 0xbf0e6c6b 0xf8868417 0xd664e19a
+ 0x524733db 0xfb9c9b70 0xb98bbbb6 0x08083c38
+ 0xe5d80347 0xee79b62d 0x01387fac 0xd26d87c4
+ 0x5fe568b5 0x96a82fda 0xca66e58f 0x2579768c
+ 0x63116536 0xe959d2e7 0x0f854cf9 0x4eabe9b6
+ 0x5ece1cd3 0xd14b79d5 0x16d43031 0xc3eee230
+ 0xe5f8dce9 0xc435d411 0x66c30e0d 0x78815b84
+ 0xae738a85 0xfcb680dd 0x1158c848 0xf83499e3
+ 0x2427441b 0xb5de1525 0x908ffd2e 0xd0c325ab
+ 0x6972ce23 0xe14dde3f 0x9d6a5c5a 0xc81ae057
+ 0xe775239e 0x80d9d083 0xb758aed7 0x4b0a960f
+ 0x95d421b1 0x8457d800 0x7fdf0f33 0x6a8da972
+ 0x5a1e43a6 0x7075b383 0x1a56e8df 0x6881ef0d
+ 0x927e4a53 0x2b229988 0xbf955c6b 0xddb168e9
+ 0xf4c3a41b 0x7f5aaeb2 0x3703df12 0x82fefc6d
+ 0x9072a83a 0x15912eb3 0xc3b709b7 0xf2688911
+ 0xff761108 0xa9bc129e 0xa8b7185c 0x3e18a6bb
+ 0x9ad22d22 0xd89c2d61 0x8a77f5f5 0xdc62e278
+ 0xf9225008 0x3af51072 0xcfe039cd 0x443d7dea
+ 0xf11280f2 0xd537ef15 0x8a563c9b 0x977ea6a9
+ 0x5ae7791b 0x8767d5ec 0xbc1c4c2f 0xb0fad47b
+ 0x056607ee 0xe3064364 0x67d8a4b0 0x14c60ef1
+ 0xcd5881f0 0x115caf21 0x2f85528f 0xe002c620
+ 0xb6c7063f 0x97ecc4fe 0xf1767731 0x04e5ff88
+ 0x8a4ae2de 0x61908c05 0xc5eafb5f 0x160554d5
+ 0x10f4891a 0x346f5021 0xbbcfa5f6 0x0def8165
+ 0xb2dec581 0x79e35980 0x6f2837f5 0x3db025c2
+ 0xde12696a 0x33f0d559 0xb7666011 0x1ddf70d8
+ 0x95116e31 0xc283742f 0xf7c090a9 0xd6c35acd
+ 0x1b59fa95 0x40d6a440 0xf5124a8e 0x851b2eb5
+ 0xe23f909e 0x51e7d43e 0xe8448ad2 0xecebb43a
+ 0xba214d3f 0x8668acf0 0x3af07c0f 0x5d522cb7
+ 0x18e1e776 0x13d1c118 0x8eae9d53 0x9abb258d
+ 0x4b5d4b48 0x4395da72 0xb8b3e620 0xaf1be0db
+ 0x5dc55eba 0x1bd22e25 0x557a72d0 0x163e00f7
+ 0x61188e81 0x258a2c1e 0x0c4276ee 0xd7c0f6cf
+ 0xcae90383 0x6b9a226d 0x130005a9 0xde508db5
+ 0xaa834c3c 0xe07538bf 0x5d5c9640 0x09e5e3a6
+ 0x925b2f59 0xfc0c262c 0xb3fe8482 0xd55f9dd2
+ 0x18824ddd 0xcca0e20a 0x58f5e91e 0xbe9bfc6b
+ 0xed8fb482 0x06272330 0x58049c9c 0x746c2ec4
+ 0xb3f7560c 0x28cafafc 0x537795d3 0x74198ba2
+ 0xe74e67f4 0x77294fca 0x3af10e99 0x8e19bc12
+ 0x6518d98d 0xf770119c 0x30dfee06 0x171175c1
+ 0x2834cada 0x38dc4780 0xb1a8873e 0x47a626f2
+ 0x790e757c 0x71d5196b 0xded342ff 0x4fce9787
+ 0xae6c198a 0xb26100e3 0x758992a3 0xc9021e08
+ 0x54de129a 0x793b2e40 0x78d5e95c 0x6f433a46
+ 0x49264de9 0xe155bf0e 0x3bd4788b 0x7b9291ec
+ 0xf80b3c50 0x5ada3b87 0xd1a7b055 0x4cb0eb44
+ 0x4f712378 0x36bc14b4 0x7bd0b6b9 0x62920554
+ 0x780ea525 0x1c74f629 0xe1431d38 0x4ea1ff33
+ 0xba9ad4ab 0x6b8113fe 0x0022a139 0x835303e0
+ 0xfa39cff6 0xe45918a5 0x844484a2 0x55b42e18
+ 0xf14cd964 0xb65c5efa 0xd04e9cbb 0xcba8edf6
+ 0x2dd6a76e 0x1d5da1ec 0x9329bd8b 0x527d6e4c
+ 0x956956fa 0xeaba1ade 0x9125ddfd 0xd6f09a18
+ 0x4d2db260 0x8c8b9e8d 0xca95ab0a 0x5bbe0573
+ 0x7310a64b 0x4d5c4c73 0x0a2f0b12 0xaf9bf6c7
+ 0xc9687aa8 0xe5a2a604 0x54ec3dbe 0xf4256cc1
+ 0x405fc417 0xa19ca399 0x93531bda 0x595298c7
+ 0xa28dfa52 0x7385a266 0x027dc36c 0xcdb82903
+ 0x5ce4b82c 0x98977244 0x0d4cf474 0x99236465
+ 0xb67a8672 0x1e1fee2b 0x38a75771 0xfb017ac3
+ 0xc04889d4 0x93753894 0xa9603439 0xb37a2ca7
+ 0x8491a2b3 0xdf1cad03 0x6717cc79 0x9f8bacae
+ 0xa053641e 0x8383fb3b 0x0229b112 0xf9d2a0f0
+ 0xb578ff0e 0x79a48f10 0x33a2f133 0x8d9a77ae
+ 0xd931bc20 0x6629f839 0xeb0e4ada 0x2b8c1290
+ 0x2c3aee9b 0x324eef42 0x13b50a02 0x059aa872
+ 0x8ac20f06 0xd2d8eb70 0xf575298c 0xca65765b
+ 0xf7a92001 0x9bb5dec8 0x49b44f85 0xa3f93611
+ 0xf2d51bfd 0xf8e42618 0x03d9a8dd 0x34526d3b
+ 0xa3b9112a 0x385ff261 0xae991c2f 0xdd990afb
+ 0xf10471f1 0x842b7feb 0xc959bba6 0x51db24ca
+ 0x7af01558 0x1abc2242 0x8adea69a 0x77140ced
+ 0xd7fa451f 0x46c48f08 0xf19545c7 0xc571c2a0
+ 0xd24188c2 0x2da3f8c2 0x035b1847 0xcfbccf6c
+ 0xe4e6123e 0x56967bb0 0xb0187725 0x1e98dd1f
+ 0x2c5f8b17 0x42ad6c44 0x7dc0cdaf 0xbdbc7762
+ 0xf926a4fb 0xac0b9ea6 0x7108af88 0x335f4e85
+ 0x174ff319 0x08263330 0x9ab6c830 0x2dca63a5
+ 0x479bf730 0xc8187fd6 0x97daf5aa 0x66f9147c
+ 0x448b62b1 0x9db3dfaa 0x4c0abeec 0x3eb5e03b
+ 0x726606d9 0xe2c3faf8 0x8bf2f174 0x6395c1fb
+ 0x1e84bf32 0xfb452586 0xee550d69 0x40858cdd
+ 0xf454cd26 0xefb81d50 0x3c879cfc 0x41a58812
+ 0x30338aea 0x42288f92 0x4a4980a6 0x40556e1f
+ 0x3d14bcdb 0xd6509d13 0x494d8e13 0x05ae949d
+ 0x1d8528cb 0x40c73cb9 0x24e60bba 0xbdd52ae9
+ 0x4aa0fc29 0x5f01792b 0xd0d13875 0x7c3553dd
+ 0x41a52955 0x0325f0f0 0x49ba411c 0x05d30bd1
+ 0x2af8ea4b 0xf91e6a39 0x17054898 0x33516ff4
+ 0xc62cf75c 0x301a0459 0xc18857e3 0x78f05585
+ 0x07eee4db 0x014c9d2d 0x5e67a82e 0x9babf458
+ 0xb7ada3a8 0xb4c978ea 0x0ac14e64 0x6c47ff91
+ 0x9900eea4 0x1ba7c285 0x51c7f0e4 0x64d8f725
+ 0x0f0cdc9c 0x69cd6c3a 0x37589cc1 0xe9bcd133
+ 0x23b39134 0x205ba564 0xc00dbffb 0xf01c3680
+ 0xada1dfc4 0x3494c547 0x34f95b08 0xfaff44b5
+ 0x8a2b6e4a 0x579f3f04 0x7cedfc17 0x41ef4344
+ 0xe786cd57 0x5ddfbc7b 0xecd5c628 0xfe55a66e
+ 0xa68bcf08 0xd69384d9 0x9cfe6968 0xa98b01b1
+ 0xf569ba00 0xdbb51d1c 0x3df4a346 0xf913cbfc
+ 0x8b156a28 0xf95684bc 0x5bc070cd 0xf6b27548
+ 0xe7f9c2ae 0x9233351d 0xa9ba9381 0x632c9197
+ 0x6dbd7022 0x67b448df 0xbb62f843 0x6a712209
+ 0x03867759 0xd7baeeb4 0x5104c12a 0x11f9e0c8
+ 0x9fae9186 0x46c17ca4 0x33b16593 0x20308078
+ 0xdfebe428 0xac27d933 0x59cff948 0x60eae57f
+ 0xec308135 0x2a2b3da3 0x47c74c7e 0x24dd1bac
+ 0x11f67090 0xd2b37df5 0x2367170b 0x08b3ce06
+ 0xfeef940d 0x46cd6519 0x6685cee3 0x23244876
+ 0x5929c779 0xf8fd52b5 0x7520251b 0xbe64ea34
+ 0x594ba72e 0x8a522818 0x3a563759 0x448dfe58
+ 0x28b8193a 0x8b898a6d 0x26b1864f 0x94b9a512
+ 0x58c57299 0x326b3c96 0x3073f0c2 0x5c9623f5
+ 0x69e2d14d 0x06c69b27 0xbae70a29 0x77120eff
+ 0xbd57a135 0x3182e024 0xc48ce0fc 0x889476f2
+ 0x9c5c428e 0x18243a48 0xf226e200 0xa434bc0a
+ 0xc31975ba 0x7a7ff48c 0x6e459a3b 0x171057cc
+ 0x7e4cacae 0x6e2d9566 0x4a253a89 0xb26b3cab
+ 0x342ba69c 0x03c13ba4 0xce667e63 0x32250c84
+ 0xb15f105a 0x436c5c66 0xdbfd79b1 0x090ca274
+ 0xa3f5ece3 0x4b3b4650 0xa41a96b2 0xe527bc5d
+ 0xada0de6d 0x87e5a944 0x5d99e654 0x3cc3d95c
+ 0x67c2e1fe 0xa05b8205 0x5fe902ef 0xcef05b37
+ 0x1081e4f5 0xe381012c 0xd4953b82 0xacb344b4
+ 0x278b5104 0x9e8f6f53 0x539cc1cd 0x55a16099
+ 0x235f5ac5 0xcaed439c 0xad386728 0x5d2656fd
+ 0x50e1622b 0x76422754 0x88c2a109 0x6c5faaa8
+ 0x413faaa4 0x8e64eca2 0x1c900d41 0xab89b33c
+ 0xec9e418a 0xcd7d4db8 0x65a17ab1 0xbf52c694
+ 0xeecff735 0xa540d8c3 0xaa45a930 0xc0070502
+ 0x18f8e76c 0x0d0958bc 0xf5c2aa4d 0x1deb8b87
+ 0xb06edbcb 0x50228379 0x600947b3 0x99f01bc6
+ 0x9290adf1 0x3353fa5f 0x5256cbef 0x19c196fb
+ 0x822b7e48 0x5400d0c3 0x12fe150f 0x5ada541a
+ 0x410eea57 0xc34b0ac3 0x3a7ea361 0x3dfdbc15
+ 0x3d2ae574 0xd3f41956 0x79bcebc8 0x85681660
+ 0x27855dc6 0xe61bd8a2 0x47eee402 0x7e6e74c9
+ 0x0e1fd6bf 0x6ff32cb5 0x40da8747 0x85e02a6b
+ 0x9f7d9a5c 0xaa512efd 0xc6673d19 0x8218c318
+ 0x0fde8712 0x612ec9c8 0xbd40745c 0x2daf88a0
+ 0xad6e44c6 0x2e087d9e 0x1652702a 0x4fd9afe1
+ 0xabe830ef 0x08dd3913 0xce99af5e 0x2ad29258
+ 0x2d2bb1fc 0x4cd05f07 0x86c1d313 0xc121df89
+ 0xdc34b9d7 0xcf66a60b 0xf4be35c7 0xaea67507
+ 0x0905d5b2 0x6e6aec02 0xa4ed411f 0xeaada4ec
+ 0xf548fe2b 0x4a2e9a7f 0x8884168d 0x7b3cd8f9
+ 0xe380c72e 0x6332531d 0x96228e28 0x0d019478
+ 0x38b0bba7 0x3b35de12 0xbd8cf061 0xc40be0db
+ 0x308f624f 0x014dce9c 0xdc9d4c1c 0xe7cf4845
+ 0xd3c3cb56 0xd273eca6 0xd4574a88 0x47df611f
+ 0xeea7b70e 0xdc4b81b8 0x1f3adf2e 0x695634c6
+ 0x249ef15f 0x7b2b6dfa 0xa39a7367 0xf3cc99dc
+ 0xe0743236 0x6e00ecef 0x4bc24c6b 0x557ca804
+ 0xbe759d03 0x0eb2c5c4 0x366a6da4 0xa40acf07
+ 0xcaaa7952 0x63dd5b89 0x6f09f54d 0xc598a3b8
+ 0x818270a9 0xe85e2b53 0x6d437ced 0x3301c4ff
+ 0x8950ff23 0x88e3303d 0xf3b7c745 0xd823996d
+ 0x2a4caebc 0xa1eb7e2c 0x960fa785 0xa5d9192d
+ 0xb771a75f 0x6c17bda4 0xa4c62290 0x01f559c4
+ 0x5b6bcb90 0xbdf4e260 0x37d24146 0xe9f7c113
+ 0x224c8d1e 0x944f0d14 0xb7a446db 0x470e1bd8
+ 0x5b4553b1 0x9713ed1f 0x3bb0621f 0x5d13ccd2
+ 0xd1512876 0x92172e03 0x80d4f34e 0xfd03a89e
+ 0x82de677a 0xe72e0a3b 0x593b0502 0x7825be45
+ 0xa765c6c7 0xddef9369 0xd449c6a6 0xe4440203
+ 0x8be34a5c 0x22617938 0x6eaacd0b 0xd0b47183
+ 0xd39589f4 0x3159c597 0x76a0a4ec 0xf434b1c5
+ 0xf3a26de7 0xe9b69e3c 0xceb232f8 0x7bc91c43
+ 0x225cfa3a 0xdbabb166 0x04d4782f 0xd573884a
+ 0x351f5f88 0x4acda1e6 0x2cb93b68 0xed4b0663
+ 0x1dd147b0 0x4b64aa81 0x9baaddd3 0xdb305d03
+ 0xe44403aa 0xd52140b8 0x442e2197 0xfb8f8aa2
+ 0xa1d2b054 0x30ac7b0e 0x535ff138 0xa34c29fb
+ 0x4dcff8e5 0x4d4b5af7 0x75846d8b 0x29060275
+ 0x154f0dbc 0xf506c696 0x18706d08 0xbe1cddfe
+ 0xc972edf3 0x070f4aae 0xe5055290 0x12ff9063
+ 0xe4b81a09 0x11ad8348 0x184faea6 0xfe9b3674
+ 0xd8a68c8c 0x28366da2 0xd0729297 0x8c07e77b
+ 0xe85cb507 0x54d582d1 0x0e10aa56 0x5f79aff3
+ 0xb5c2f58c 0x0976ca59 0xd43bed61 0x9e76951d
+ 0x4bc2542e 0x7a1870fc 0x2cd01266 0xcc717daa
+ 0x045e2757 0xa5b943c8 0xbbb21e51 0xa19b070c
+ 0x985e3e58 0xb0f22523 0x1dfac693 0xe2491946
+ 0x649791b6 0x54d4f8fc 0x2920c0c0 0x45af983c
+ 0xd400878f 0xbf94ce47 0x00dacb15 0x8f79afc0
+ 0x96d4d1f6 0xdacc4fee 0x3eac2a87 0x89f808a3
+ 0xa8963eb3 0x3bfbf9fc 0x16970a5b 0xdc925ecb
+ 0xfa5e4920 0x219ffbea 0xfb442d8f 0x32a5d657
+ 0x7db7483a 0xfb330167 0xe75f7f87 0xea1de0e1
+ 0x764b080a 0xed1eab80 0x6b75f59a 0x8dceba7f
+ 0x735a7fce 0x68128837 0x7243057b 0x4da7a027
+ 0xc1c502ca 0xa5f2bcc4 0xf2c6209c 0xb675c45d
+ 0xa5aef423 0x362b5df4 0x7840609c 0x714209ea
+ 0x3919be09 0xc67c360b 0x6ffe8d84 0x3dcc0e10
+ 0x558ec8dd 0xa2285d7b 0x9eb86078 0xb4685e77
+ 0x3840ab30 0x2ac2fdb1 0xc6b795c0 0x834c15c0
+ 0xaa0ff942 0x74fdc7e3 0x87ab3565 0xa9d3f71c
+ 0x53ad4955 0xad5191de 0x3e30a79e 0xee227702
+ 0x5910cbaa 0xce926dbc 0x629937d9 0x271e98ea
+ 0x29ac6f12 0x09248669 0x74d8fbb5 0x435a83c3
+ 0x93dd39a3 0x7bcab8ab 0xf86858ac 0x403823a8
+ 0xd9fb5669 0xddfdc2b6 0x9b7e771a 0xf7a6a574
+ 0x1bdc0062 0x54c621be 0x45a49ac5 0xf4b5c38c
+ 0xe7916b1f 0x4ea7f121 0xd5457986 0x6bb57a6f
+ 0x1bc4d42b 0x2ab0ee84 0x5b8e508e 0x6adf0b60
+ 0x1c39dc48 0x25d58fce 0x54327b32 0x93718903
+ 0x991e452b 0x627cc0d3 0x15233871 0xf921f79a
+ 0xea6475d1 0x9b155143 0x5914ee94 0xbbeb43cf
+ 0xbd590426 0x8aaaa0c4 0x50b174a1 0x51aa1955
+ 0xea349dfc 0x005a2de4 0x4603a63a 0x971af0b8
+ 0xbcd89a17 0x1d49e631 0x63d3a40c 0x63b0f1eb
+ 0x975757fe 0x706e086e 0x161d0cad 0x5b5f4fe0
+ 0x4a82f4de 0x34800a89 0xdcfeeb96 0xae9c0bb8
+ 0xa6422c15 0x8ee1b10d 0xa454ec0b 0x1a51e7eb
+ 0xd2767564 0x8541c726 0x7e0a8cb8 0xbd6f58ef
+ 0x7325c5fd 0x5f8b8144 0xb18853e2 0xd6ac3e90
+ 0xeccfdfaa 0x8bed8778 0x7d65f220 0x86502ddb
+ 0x272d7bbd 0x9546beb4 0x2fdbc971 0x8f86c26d
+ 0x317131ee 0x06a2d84b 0xcfaeb274 0xbdc64496
+ 0x842eee16 0xc5596e5e 0x3fc8d83e 0x60ce3e3d
+ 0x233ff26f 0x8e7eea69 0x3dfb8b62 0x0bd1271f
+ 0x3276add3 0xdce0f322 0x272f2fed 0x310b01b9
+ 0xec13dbff 0x44ecef5f 0x716a95b1 0x8e2ed760
+ 0xfc1cdbf3 0x363ab021 0x529c749c 0xb8361787
+ 0xb576b8dd 0x05ba72be 0xbd94ddca 0x995823cd
+ 0x4bf10e99 0x6350d475 0x6fab0d5d 0xa3fb7ef0
+ 0xa755d719 0xefeb5c22 0x8369b60e 0xa190b7b2
+ 0xf1ca5eba 0x406fbd8f 0x0b858d59 0x9f4f3a99
+ 0x600706c0 0x8efb77fd 0x8ebd23fe 0xa82b4e93
+ 0x44d50e4f 0x92a2b5a1 0xde8229a0 0xa9128ba4
+ 0x6dc829bb 0x5d63bac1 0x8948d416 0xbb85eebc
+ 0x4b280f18 0x6156e24b 0x5271526e 0x3a550970
+ 0x7212c942 0x09040eba 0x0c199ae0 0x3f41b3f9
+ 0x8d439401 0x83319b2d 0xf3deffb4 0xfd813e2a
+ 0xa8ac6a50 0x72858022 0x5650a6ea 0x8b9e18a3
+ 0x7dc2d48e 0xabf0c35c 0xe9d93f5c 0x228412d4
+ 0xa7b07016 0x0babb01b 0x36faa524 0x3157fe90
+ 0x4cf0fd08 0x1272a76a 0x8e701e54 0xd1ed3067
+ 0xe92bc6ac 0xea2fcc5d 0xdae1a6c7 0x4ec3465f
+ 0x97556141 0xda282893 0x2bdf77f3 0x458abb7b
+ 0x8c98d27e 0x9f2ddc8e 0x4bf66134 0x7ef33d1d
+ 0xe7bfef39 0xa9b37d3e 0x2272b785 0x41bc32d3
+ 0x16790e7a 0xfcd172a9 0x4dcbdb4f 0xadc6cea4
+ 0xe72aab79 0xd3a530cd 0x153171ea 0x60d6122e
+ 0x1b00ebde 0x366861f2 0x6781fc14 0xe6d6189c
+ 0x3b9beebb 0x5c239e07 0x51999573 0x5b900c94
+ 0x52a14fae 0xc7c0bdfb 0x5bebb646 0xaaebca2f
+ 0x360c6d2f 0xc8b43453 0x16ae683d 0x11248d2a
+ 0x08fa3017 0x2bfc636f 0x7360ae91 0x793ad23c
+ 0x7d2bc4bc 0x2d505664 0xee449c94 0xbd0beb6a
+ 0xa9b818e7 0x251354ca 0x119825e5 0xae8b8d2c
+ 0xeea15a2f 0x8b3c47ad 0x2af74ac7 0xaedb8156
+ 0x9b96ee47 0x05034a2f 0x752f8722 0x0f1ee372
+ 0xff55b4b5 0xd12d4ead 0x554c31c4 0xc167849a
+ 0x118d9c61 0x9825a5b5 0xd1941592 0xa21440d6
+ 0x0c8fa874 0xd23ff93c 0xf592f75b 0x6d171131
+ 0xe1cc848b 0xe73fe5cf 0x38677f4a 0xddbbd004
+ 0x6af79754 0xa666b38e 0xf5afba55 0x036b1f0b
+ 0xd55860f2 0x1efdbe6f 0xafc557a4 0x3b24c27d
+ 0x68f319ef 0xf863285e 0x80e88563 0xbe2af6a4
+ 0x81360909 0xcfbaac9a 0xa0a07505 0x8c653634
+ 0xf630bc25 0xdea1640f 0x51445022 0x8bd02194
+ 0x593185c9 0xc23f98f1 0x06b6d384 0x432278ed
+ 0x9c422519 0x0664dc91 0x733e7075 0x9e05a4c2
+ 0x1b014110 0xc4787233 0x4aad488b 0x756f0d47
+ 0x9e29a6df 0xabde4b5d 0x23727bdb 0xf1e3a05d
+ 0xa1f22c40 0x2d290090 0x62d3b212 0xcc247195
+ 0xcd5c84a1 0xf277c61f 0x4f9f213a 0xa69e7391
+ 0xf09f4162 0x44771471 0x6be202f9 0xf27e05bd
+ 0xef27ffc6 0xb94d8b95 0xcc124e11 0x6d22e955
+ 0x8c572ef0 0xc59727f0 0xa68aa858 0x034de5f4
+ 0x242700ae 0xcad4225a 0xb5e792ea 0xf791ab32
+ 0x8f75a863 0xd078bb02 0xec889a62 0xbae59fa8
+ 0xd0e96b37 0x7127e3a9 0x69283a7c 0x7fe26fca
+ 0x3b33f97f 0xef3bfad2 0x0a33c011 0x060e0e58
+ 0x27de1402 0x55f0b8c9 0xf48de31c 0xacbc1c7e
+ 0x228459e6 0x9119a04c 0xeae173ef 0x50347a6c
+ 0x6da1ae72 0xcea1256b 0xc328fe6a 0x85a48b53
+ 0xd8bdb49b 0x857cd611 0x2218a975 0x4893fbe3
+ 0xbd0b7590 0xdc35b430 0x0b37d8a4 0xc1938a77
+ 0x78423be3 0xbb14bb91 0x0c900fe5 0x82037d1e
+ 0x1fc0a8c5 0x5b83cd7a 0xf1a7ff8d 0x36cb83e6
+ >;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9092011>;
+intel,processor-signature = <0x306a5>;
+intel,checksum = <0x8e38731>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200909 0xa5060300
+ 0x3187e308 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x08091120 0x71080000
+ 0x01000000 0xa5060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631
+ 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xb290ba8e 0x6671b099 0x7834fb60
+ 0xe02e439f 0x55712161 0x5dca20ba 0xb62c06df
+ 0x83d86103 0x35cbe438 0xeb7841c9 0xded7ad9a
+ 0xda76b9f2 0xa39233f5 0x11377a10 0x6928a0e1
+ 0xf6164be1 0xab9cb400 0x0ac5e864 0x978e6cdc
+ 0x51d9070c 0x3786d896 0xa6b103d0 0x288c8c83
+ 0x9c644099 0xf9a8a7ad 0xd2a96566 0x2e985d7e
+ 0x3531b0b8 0x3906909b 0xce3878c3 0x30b950a6
+ 0x536b312c 0xb9f07473 0x29366b16 0x7a515f52
+ 0xce7d21ff 0xfe5aef73 0x69b91f78 0xd50b9686
+ 0xa384ac5c 0x6e90981b 0xc37028fa 0xc448c695
+ 0x3c5275e0 0x2ea780c0 0x5fe9aeb5 0xa733e8e1
+ 0x2a04c422 0x68243f2e 0x5311d43b 0x93c27dfc
+ 0xc78b431f 0x9a7bd54e 0x7731f225 0x0f71db56
+ 0xf89a8f8c 0xc5eb2d2a 0x45f973ec 0xbb0635b3
+ 0x5b825acf 0x8744ccef 0xceb1dfca 0x5e5b882f
+ 0x356cfd00 0x68e42c02 0xf0ea6e97 0xa0c1327c
+ 0x5fb06338 0x3e7df893 0x5c3eb0ec 0xac7cc79f
+ 0x3dee3b4b 0x313a2915 0x4002db54 0xe8a96a04
+ 0xb79c367e 0x6d53a3a8 0x9b2720c7 0xf5e7dee4
+ 0x357fc3d7 0xcfc9b54e 0x72f9732e 0x3ccbe991
+ 0xe0486033 0xabeab549 0x032089b2 0xeb1467b3
+ 0x3898e23d 0x4f25f3d4 0xe2f64597 0x3e7facd4
+ 0x455514e6 0x99dea4e4 0xc1201200 0x72d68181
+ 0x25046d7e 0xd3b6ada4 0xd3f358b2 0xb6a0dcf5
+ 0xfbf43626 0xd9cafa7a 0x27ec8d4a 0x84d60c14
+ 0x35e79275 0x413169be 0xbc9847c4 0x0ddcad0f
+ 0x5e098c03 0x03187763 0xed64abff 0x8eaada0c
+ 0xdf378018 0xf394b0fa 0xd4abca64 0x3ad203b6
+ 0x1347cdf9 0xffaf1040 0x078c6baf 0xf2e7d31f
+ 0xdfc334c5 0x061d2348 0x85877503 0x561b6cef
+ 0xfc9aa2ed 0x6057d0b6 0x288df59a 0xda7c47f2
+ 0x727a8584 0x58f74d64 0x8afa48dc 0xf50d3582
+ 0x9f42eec8 0x776d1b6a 0x35f42768 0xbdb7f7bb
+ 0xa239bc05 0x1d26bcce 0x025568ca 0xa2ef8189
+ 0x0054417e 0xf9aff2b5 0x56cc33be 0xed695186
+ 0x58b21d0d 0xea2215c7 0xa565b724 0x2931c422
+ 0xe20b2043 0xa85a082d 0xd7760789 0x58c317cd
+ 0x8c500d70 0xecd22975 0x79542e54 0x790b048f
+ 0xcbbc98fb 0x125b81f9 0xe3e74009 0xc6f4ebc8
+ 0x1e22f4b7 0x0485cac9 0xeb4dc6c9 0xab9076a3
+ 0x9feccd38 0x733e57dc 0xe250d25c 0xf0eb5a8f
+ 0x3db33c3c 0x36c52b3b 0xfe5f92fa 0x0ddc38bf
+ 0x003c6542 0x154abb1d 0x4feb8d85 0x6aae78dd
+ 0x59282b12 0x04fec81c 0xf6f117c7 0x7123b56e
+ 0xd8c53d48 0xff2eeac6 0x09716dee 0x5d24cb13
+ 0xae7c77ef 0xf0213c38 0xd7290320 0xfe3ce627
+ 0x9402607f 0x42ebf5c3 0x4b25a536 0x7167f997
+ 0xe456ed20 0x5a8ed54c 0x8f774e9c 0xa9f1bf83
+ 0x2322ca10 0x3bd6021f 0x2ad0affb 0x0a727ca8
+ 0x228cf77f 0x19f54f70 0x2b7cc811 0xa7193b61
+ 0xcc097688 0x395a8700 0x073e2b6b 0x8e90c718
+ 0x0855f8c6 0x7de3d62b 0x2f582aee 0xeb8667b7
+ 0x6a09f600 0x119a656a 0x7502100c 0x36d51cb0
+ 0xb398a2fe 0xce1a11fe 0xa75b725b 0xf8d69c5a
+ 0x69b6a07f 0x3b5e712b 0x07d647d0 0x80bbe6af
+ 0x80cdefb0 0x03ae17e9 0xda7da860 0x39610997
+ 0x67afea64 0x2d141230 0xd845efe5 0x346b9c22
+ 0xf03d45ce 0xa7f96ffd 0x21bbd7fd 0x035297c4
+ 0x27b88b33 0x8ff80f90 0xa41161cc 0xe38a33d1
+ 0x3d12c73c 0xc81ca705 0x55bb79a9 0xc80037b2
+ 0x2b1b7c7d 0x47ccc91e 0x440370f4 0xb754bfe2
+ 0xf9774b91 0xa8d2fa85 0xb7db3a31 0x102a7131
+ 0x61a200b0 0xea8bf0f9 0x826ca613 0xd3842856
+ 0x27fa5f1b 0xdc6f7aa8 0xc4351ff1 0x13e8d56c
+ 0x3b81f6fb 0x444bb6a0 0xb5fadf26 0xf1e0fd81
+ 0x5c75fa49 0x1e66f533 0x74f83da7 0x749327f5
+ 0x1f41d35d 0xabb10c2c 0x15ff553f 0xbb5ad732
+ 0x904b2bde 0x6eb6c5d7 0xc38cef3e 0x5b62a4c7
+ 0x4c1d0297 0xeb0d88e3 0xe147c6c8 0x726bde4d
+ 0x2cce53ca 0x2e0ad784 0xb5ce9c2e 0x04fa3a1c
+ 0x85fdc1ba 0x87a73107 0x3b1a12db 0x84f7c886
+ 0xbb9c65d3 0xf319fa80 0x8684ad1a 0x8b675754
+ 0xcefe8be8 0x19fb7f42 0x9fbc80de 0xea169c83
+ 0x7aeb705a 0xee25f4ee 0x2f51d222 0xe553b558
+ 0x3bbc3526 0x9b99ac52 0x97b7fa61 0x997ff0fd
+ 0x1d90099d 0x611d8fdf 0x180e1256 0x02436dd8
+ 0xf5c0088b 0x977ce145 0x3e22559a 0xa7434bbc
+ 0xbc0af767 0x61f2adbd 0x6b414aa5 0x23256487
+ 0xcd90a1de 0xa212e85f 0x5a8cbfda 0x901ce98d
+ 0x58784538 0x3a02ddb2 0xd388d8fe 0x18e21114
+ 0xc0ce52ac 0x10eb99b3 0x434dbf0d 0x9fc25de8
+ 0xf4166b7d 0xf520d339 0x80889748 0x36c5122f
+ 0xb0f53d62 0x78f18c2b 0x10b7e0ec 0xb515926e
+ 0x70065726 0xd83b26cb 0x284b191e 0x33c4a3f7
+ 0x97998f96 0xd7458672 0x5e23c14e 0x78a584f9
+ 0xa334e7d1 0x8fcf2992 0x0d7748be 0x3d5e9309
+ 0xa4a46124 0x536108b4 0x57af0c09 0x7ec11806
+ 0xd6b8c03b 0x8618900f 0x6c1c60bb 0x9650af3b
+ 0x83b8c109 0xfbe91320 0x681cc792 0x76fb441f
+ 0x69eace4a 0x66563862 0x86a7a909 0x59815c86
+ 0x604c949f 0xba39a0a4 0x51a1322d 0xaff2a150
+ 0xcba82656 0xc82a79cb 0x9eaa5989 0x5602a25b
+ 0x91917c30 0x46e610b4 0xcb698616 0x571cacc8
+ 0x642c25fd 0xc61a5c96 0x5c0d7b2b 0xb22e2868
+ 0xc5697ac3 0xf69795be 0x9aa5f24f 0xbd4c0815
+ 0x61e63957 0x9a2c3a0c 0x452bd662 0x06ce51e9
+ 0x849769c2 0xe7d1ece0 0x53fbe99a 0x1f8c3976
+ 0x04bbf199 0xa11ebe8b 0xcf862106 0x75f9410f
+ 0x4e573a0f 0xd37b1822 0x45e821b5 0xa72f103e
+ 0x87d41b9a 0x751c1360 0xa3d9bf04 0x38817c3b
+ 0xa1243092 0xeaffa979 0x315d68ea 0xdf4544d4
+ 0xd7bc8ed8 0x4200e14f 0x46cb8d5d 0xe53e695a
+ 0x20fdcc05 0x7bc91fc1 0x21a08c38 0x70377159
+ 0xf000b852 0x010b2051 0x64f27dae 0xa5d40c9f
+ 0x0d2d05db 0x035026b4 0x4dfd9dc6 0xe1ba51b6
+ 0x182921b3 0x3a14fd50 0xfd822b9f 0x1c475677
+ 0xa23ca2d4 0xa4471500 0xb0a3425d 0xc384422e
+ 0x1791bb5e 0x300db057 0x015cdb9b 0xa9254782
+ 0x850a6ed2 0x939270a4 0x6173f301 0x59c678bd
+ 0x8dc33d87 0x8ea24bbe 0x8ffaf807 0xd132392a
+ 0xeb824b6c 0x6dc0e254 0xba2588ea 0x83c5b65b
+ 0xed46fa12 0xc9932295 0x6feb2198 0x74cef43c
+ 0xda34147d 0x338e8acd 0xb6bc8ae3 0x62eeeb57
+ 0xcfd703ec 0x0fa51fb7 0xe6dedfc6 0x06e05089
+ 0x0cd711f6 0x43f73969 0xf43b945e 0x1a63c878
+ 0x366aa911 0x946e06d0 0x8ff0d6f5 0x99e7a128
+ 0x96bf8c82 0x93ffc377 0x9e7d65a8 0x6ef2f639
+ 0x57ac2e72 0xd0d643e2 0x228bc4cd 0x76f8d2a3
+ 0x2c845f50 0x830d3729 0x58d7485d 0x0024caa6
+ 0xac3a5590 0xf18e17a6 0x684dc526 0x6c727c92
+ 0x9abaaa66 0xbd78b8b8 0xac5a3426 0x15c1111b
+ 0x0ee1a7c1 0x665f4531 0x617e891f 0x3285e4d5
+ 0x4cf347dd 0x7b66024a 0x081de006 0x1005600a
+ 0xf124826a 0x2fcb5728 0xc1ddc0de 0xbd7c76d8
+ 0xed4d9ef0 0xaeb0472a 0x2b07a2b0 0x3737ffed
+ 0xd40ef124 0xd1c577fc 0x58076c85 0xb88a0dc0
+ 0x87a5020d 0x062dc1d0 0xb7c62806 0x9aa2c8cf
+ 0xca896ae8 0x40ff25d1 0xe97e160f 0x9f55451b
+ 0x9ba07423 0x6c93a22f 0x55f124cf 0x39ef755e
+ 0x04dac73b 0xa8e8c97c 0xf97d7be2 0xd6200b18
+ 0xf9299b79 0x86abae89 0x661f5e34 0x7317dfda
+ 0x38dff8e7 0x9cea93ba 0x503971a0 0x2837691c
+ 0xbf4eb209 0xa20ce894 0x255c4fff 0x74180a05
+ 0x3c5715da 0x017ec40b 0x6f580634 0xaab316b4
+ 0xcaf9fe94 0x3ca6b65e 0x74015cee 0x4a3ca213
+ 0xa7db4345 0x5a2bb90c 0x2bc01b3e 0x8949fab9
+ 0x548cbb0d 0xf8fda387 0x6e833630 0x786ab073
+ 0xe6fa5787 0x0a659d86 0xe75b17ce 0xf2d07498
+ 0x2ab3ef78 0x74b31ba9 0x623e7ee5 0x1dd7ac63
+ 0xf30617ca 0x34385e0c 0x5cffcadd 0x97bb21b4
+ 0x0aa7cae5 0x679e83e2 0xd15be3a7 0x35a68299
+ 0x7bb0a530 0x33f4793d 0x098b4d9e 0x10123f64
+ 0x39dfe4c1 0xc826ca0c 0xc0f0959a 0x8ab66a8d
+ 0x537e4273 0x93a9c3ac 0xd8d04d5a 0xec511096
+ 0xe14318ca 0x2933223b 0xf89e7a44 0x8fe3680d
+ 0x0ac46c4f 0x87bfbc2e 0xaf4161d7 0x80a1d020
+ 0x91b7b729 0x212b7294 0x6cf14779 0x89faf74a
+ 0x7c5ebbfa 0x6dc0b4a0 0xd3617c72 0x08525097
+ 0x102bb960 0xcfc6c0ca 0x65a604bd 0xd39affdb
+ 0xcab7df61 0x2fb9080d 0x48175e89 0x25133092
+ 0x4a0229e5 0xf88ec53d 0xac24abe7 0xb84598f8
+ 0x1bab71db 0x3c6fa6cd 0x2c4dfd2e 0x22dbc3ef
+ 0x5ac3e6cb 0x66234a29 0x2c26aacb 0xfcb4bb99
+ 0x204c226c 0xc20561ac 0x1e5bffaf 0xaacafe8c
+ 0xf03bfa31 0x0dbe0396 0xd7561d7f 0xb53794dc
+ 0xfe641d5e 0x54e48453 0x611700e5 0x0639b5cf
+ 0x7028a7ef 0x6f3be4b7 0xda5b1755 0xc988199a
+ 0x48497e7a 0x4e3cf3fe 0x99d212e3 0xbd2b89e6
+ 0x98b4ef8a 0xeef8e602 0xef153f89 0x143151c2
+ 0x90557d9b 0xe6a8ef65 0x2e380066 0xe54ac324
+ 0x8e8fc6dc 0xc23f7add 0xaf1fb336 0x3e60c29a
+ 0xe1d56ba3 0x8f654c53 0xf30e755d 0x3b4fa485
+ 0xf8ab5ed0 0x77336bd7 0x56489149 0xc284403e
+ 0x86801f98 0x5a4230ca 0x3af70662 0xfd8ce85b
+ 0xf6adfca8 0xe8cd1021 0x203bbbd2 0xdbb3c8c1
+ 0xe08a736a 0x29a9b3fa 0x3ac18aa0 0xa109b619
+ 0xc7fdbc67 0x161ef5b0 0x6efe8dc1 0x3b9214dc
+ 0xda2ef14b 0x4beec8ac 0x587806a1 0xe796b93a
+ 0xcd1efc91 0x3402e472 0x77150586 0xf8b4381e
+ 0x9d8bfae1 0xfb07a3e9 0xe84d8f52 0x97b0ea6e
+ 0x3e082a35 0xf4b05402 0xd29d4891 0x7da3c1d2
+ 0x3ea5fb56 0x78785f7f 0x6b09f74e 0xd4055e3e
+ 0xeede0d53 0x5b8b354b 0xb5132dfa 0xc5682461
+ 0x78971da4 0x290869a1 0x972e7460 0x91e2ff0a
+ 0x6c0b11c3 0xe91a471c 0x6e0eac24 0x320f7064
+ 0x017e0db4 0x7787cb8f 0xaeee8791 0x1845374f
+ 0x96affa9d 0x26b1a81e 0x9d303406 0x87ea47b9
+ 0xfb91e077 0x9b6f5e58 0xc03cfae2 0x494c55f8
+ 0x3080c429 0xe001b48a 0x3819f103 0x13cd3b86
+ 0xc8bdc304 0x1694671d 0x37217270 0xfa15992e
+ 0xf3448fa1 0x70567b60 0x75e6b3db 0x9e411eba
+ 0xeeac50ca 0x5d5a067a 0x1f555a8e 0xa5dae7ef
+ 0x6205551b 0x1f886ad7 0xb980337a 0xb20cf87c
+ 0xf2ed482c 0x787c6e0e 0x180a809f 0x723eefb1
+ 0xb4ba42a9 0x617a054b 0xed5cd307 0x3aee8414
+ 0x03db3a2e 0x7b17b0d3 0x15b6cf15 0x07fdc220
+ 0x172f174a 0x3420f66f 0x731294c1 0x2f4f40bd
+ 0xc5077559 0xe224c0d0 0x481e0614 0x52fa9a86
+ 0x2de9ebfc 0x568cda73 0x30e3e521 0x4d74db41
+ 0xe6bba3bd 0x15dcf205 0x684c95bb 0xc700dc76
+ 0x09b2ba8a 0x44fab1c4 0x0cc69cb5 0x30647b12
+ 0x1d6027e5 0x3e41cea5 0xebac90c8 0x0faaceb5
+ 0x0da396a0 0x7ba7dbb7 0x6383f0b2 0x2ab79b0e
+ 0x2609b0c8 0x9483a4dc 0x15b518bd 0x8ef64ab3
+ 0x04525707 0x2e7508a5 0x6345f48c 0x4c91d9b5
+ 0x0cac5beb 0x2608fc0e 0xf2e856f2 0x98cd968d
+ 0x1d3d91f5 0x176604ea 0x0a2d2dfc 0xb3434c9e
+ 0x39310c4c 0x03023246 0xf35ce087 0x1687dcd9
+ 0x42a7c9b1 0x7cb216e1 0x42eae528 0x9f412af7
+ 0x774f7224 0x67810c12 0x65a5f218 0x61e4a7b5
+ 0xe7545f4a 0x99173997 0xbec075a4 0x652039b4
+ 0x780fe7b2 0x0984ddf1 0xbadc6857 0xdee86ac8
+ 0x3d327811 0x1b425172 0x55d337d1 0xb44177b8
+ 0xf79e7837 0xf8da74f5 0xb5c10868 0xb9cecb56
+ 0xd61b6202 0x5982d5e1 0xeb940541 0x0b761afe
+ 0xe65acc8f 0x5494b48e 0xc5fd1459 0x1829484d
+ 0x94bcce9b 0xa2b0dff8 0xaf7f8a70 0x238bc2ea
+ 0xad4dbb94 0x783054fb 0x0d8cc536 0x3703a186
+ 0x40c6562f 0xeaee25e1 0xe2909809 0xa9846735
+ 0xd8ad895a 0x37615e99 0x9c95d6e0 0x047c5b36
+ 0x6496bb81 0x19d885c0 0xe291b192 0xc8b17833
+ 0xd55a539c 0xc68172ac 0xc63ec8eb 0xd12415cc
+ 0x862b22b9 0x2943b1ea 0x8ed7a4b1 0xfe052a43
+ 0x258ea403 0x0ca78dd7 0x8f586047 0xbbfe7fb6
+ 0xa3380f8a 0x10569198 0x597f88a6 0xa0ae9fda
+ 0x66dd24cb 0x1c832157 0x399e1973 0xcf9dd548
+ 0x88ee7f20 0x100ff596 0xd9be3e56 0xdef236c1
+ 0x2f0e99af 0x32a752d9 0xc9668712 0x7f6c5480
+ 0xc15a44f2 0x98f9d8d4 0xafadbcbc 0x3743a44d
+ 0xf03d4b88 0x55ca6a18 0xb0dbc9e6 0x71212e48
+ 0xd3be7163 0x4fd4549f 0x61669de9 0x8d9ad4bc
+ 0xf686b563 0xfa360d43 0x53add021 0xbe326f90
+ 0x89818483 0xa7a511d7 0x2d46a2e1 0x8101f8f1
+ 0xb2d2f30a 0x2c5e3a4a 0x742439a2 0x6a005d30
+ 0x78567846 0x05b04ef5 0x9a182c4a 0x221e446e
+ 0xd018da8d 0x119e2e6c 0xad5ca7f9 0x50d38b69
+ 0x99dbbb87 0x12e356d6 0xc3791592 0x300da550
+ 0xad8a6c81 0xa0db19f0 0x8cb34461 0x83707ea9
+ 0xbcdcd577 0x673e75db 0xbc35ac61 0x16e9ee67
+ 0xd9dccf93 0x57caf1e2 0xeccf5499 0xfdc12d0f
+ 0x97da0037 0x961585b9 0xccc672e8 0xd62192f5
+ 0x439ca19a 0xd918c5d3 0xd2c0f5bf 0xf8dba053
+ 0x434b8aaa 0x5e9e7f7f 0xdba2d664 0x090f789d
+ 0xda704e2a 0x3bf49b6b 0x9a56e688 0x464a6c03
+ 0x072450b3 0x9bf0955a 0xa56bad97 0xba999dcb
+ 0x04807d22 0x486db7a7 0xe6311414 0x068ebf6c
+ 0xbb69fabe 0x1abfc72a 0x4b839860 0x67feb6db
+ 0xe996518f 0xf6b67f21 0x8b5b917f 0x133090f6
+ 0x2e3524ed 0xa6fdbb3d 0x6e7f1c2d 0x4994765a
+ 0x3544fbf5 0x7e66e6d4 0x6d6d5fb6 0x1ce9e2ca
+ 0xff985901 0x8e0dbef4 0x7b388a2d 0xe9149dc5
+ 0xa3c84368 0x8d8dc7b3 0xdaa7659f 0x868a91c2
+ 0x2c6b23d0 0xcedec4dc 0xe03122cb 0xba43941f
+ 0x7b883e9c 0x6c4178e8 0xda6b3f3e 0x4055ac09
+ 0xe7c51544 0xe5764724 0x97a7f9c2 0x78954b06
+ 0xc6e49901 0xb7d3abcd 0x150df345 0x491fd23a
+ 0x0e676438 0xe6d5dce1 0x02b6275c 0x53758880
+ 0x4486b54d 0xfcbb2570 0x4b7df2e5 0x532df181
+ 0x8df5b498 0xf84cf259 0xce3069ad 0x3c3cd864
+ 0x6c845f46 0xc1efba88 0x9d6a9a81 0x065e312f
+ 0xc8c6b470 0x25c4a3bb 0x273e75c5 0xa1c5ea74
+ 0x61ecb8e9 0x526053d3 0xda33ce24 0xe4ad247a
+ 0x6efa242e 0x1b55024f 0x03c1e447 0x4bc3331d
+ 0x9b3b4820 0x9b7f31c8 0xedfaa865 0x487ac0d5
+ 0x733064a1 0x3a5ddb5d 0xfd5a13c2 0xd00a809d
+ 0x6801afaf 0x837306d6 0x5230ebdd 0x07fc0210
+ 0x49b251da 0x4aca0425 0x9948ff5d 0xceebe8a5
+ 0x9c90b8ba 0x1b97a25c 0x0e04afb0 0x7fff9d2f
+ 0xa0538fe5 0x4fbaa822 0x7c6ab622 0xa3d9519a
+ 0x09cdde4e 0x02646d7e 0x676df07c 0x15aa2fca
+ 0x50e42757 0xfdfb8dbb 0x60b113ef 0xa5311754
+ 0x99b676a1 0xb5d67a33 0xe718e7af 0x7347ea31
+ 0x94cd5918 0xc4704c50 0x5adaf5d0 0x77b2bae0
+ 0x952aa975 0x372223cb 0x4a9a140b 0x61a13149
+ 0xffd77681 0x6f3de7a8 0xb03f76e6 0x929b509a
+ 0xbf3e5471 0xb6fb2aaf 0x982e8ffa 0xe199b2d6
+ 0xd3eda942 0xdb70c9e9 0x68762bb5 0xcc69f70d
+ 0x17cefdf5 0x9f911741 0xdbe7ab10 0xb7270fff
+ 0x7014244d 0x6287ee89 0x1846bcac 0x446813d8
+ 0x3161e3f0 0x18dec6aa 0xfcb8ebe0 0x9eab2a12
+ 0x499a5a82 0x3e2efa16 0xa07c3ae7 0x078f0c81
+ 0x18ad16e1 0x4c033a21 0x0b9f9a7c 0xc25a5eea
+ 0xe52e2175 0x94f75591 0x2e644f41 0x0818c4cc
+ 0x97d45921 0xe126045d 0xd077bc13 0x6d666b78
+ 0xbc44ea8d 0xc68554cf 0x60aa6bc6 0xa7c15918
+ 0x62c7abc4 0x27e20ba8 0x9ee6b287 0x8cf00a2f
+ 0xdee0d40a 0x587a1962 0x6232c094 0x713bd4da
+ 0x9fd6632d 0x079eaf81 0x053b65f0 0x4ebe2754
+ 0xcbd4c6a3 0x77387931 0x2503876b 0xc152ed21
+ 0x17d8e3dd 0x165a3cd4 0x8feaf21d 0xcd9df543
+ 0x8d3c36a3 0x7fdbae42 0xcc14a09a 0x9936d605
+ 0x7e5735fc 0xf3b53490 0xc1f0beb5 0x96dddf0b
+ 0xbfba3a6a 0xf599f44f 0x00849851 0x6c95dcfc
+ 0x494fad8c 0x8e4de300 0x1346d588 0x416ffd74
+ 0x6aa7502d 0x3d59f56f 0x8e005a45 0xd599d254
+ 0x2e1856e1 0xad7f0c79 0x6db65cab 0x2c19bbf5
+ 0xaeb2ef91 0xffde8ba5 0x96253f98 0xd22fc961
+ 0xc6a904cb 0xac69581c 0x0c694b05 0x3a855fd7
+ 0xbf1b2938 0xff4b9701 0x74861e73 0xdb03cf5e
+ 0x4b068efd 0x7ce2de33 0x764351f4 0x16e09496
+ 0x16c9f496 0xa69eedab 0x381d3423 0x2b2248b2
+ 0x1bd08597 0xb438a9fe 0x447ed05d 0xaf0a2f10
+ 0xd432e993 0xe1bfef94 0x971fe56b 0x1ad94ce9
+ 0x96ea6461 0x20c56baa 0x13260948 0x665e47cc
+ 0x5b34ae5b 0xa7f8ecc5 0xb132a486 0xbf496717
+ 0x8affae18 0x6602dcbe 0xc76411ff 0x422fa77d
+ 0x53f83f03 0xc292e30e 0x96614278 0xd75b6cff
+ 0xe0c71f76 0xec1808cc 0xaca18846 0x4905d1e5
+ 0x20648c39 0x4b1b17d6 0x76c7b664 0xfbdfd23c
+ 0x506e0094 0x6994606d 0x2f319375 0x2fbf93ae
+ 0xff1b4086 0x88f60348 0x7a103381 0x1473c242
+ 0x388b1273 0x9da1be0b 0x13bc7b81 0x2b595ba3
+ 0x5e43f7f3 0x06452d3d 0x23a1a2a2 0x29fc9962
+ 0xf4b6d0c8 0x1043073e 0x01fe3f5a 0x598ff4a3
+ 0xddafe1c6 0x3ffa2b5e 0x689ed44d 0xd9586601
+ 0x0945cd48 0xa902e572 0x96d608c7 0x51db96ff
+ 0x10473fa0 0x6dc06b2b 0xb1d22ea1 0xcefef2f5
+ 0xe3443d0d 0x535537d8 0x225b6bd5 0x06aaf266
+ 0xeb766f57 0x04863c5a 0x3bc424c6 0x6560f13d
+ 0xf7ab627e 0x5b014dbf 0x63e064f5 0xcc19e54e
+ 0xac8a9334 0xfc35c060 0x8062720a 0x16151fe8
+ 0x56cfead6 0xf8dfdb84 0x4126eb0c 0x3d7cb05a
+ 0xe8ffc7e9 0xe0e02a01 0xfb0ba2b9 0x82aaf26e
+ 0x2f4bc387 0x045940b0 0x4590e30b 0xb950d57e
+ 0xfc9e095a 0xac94107e 0xbde59a0c 0x3a84808b
+ 0x5d3240e0 0x951c867b 0x9e695e32 0x998fe6ce
+ 0x513ea21d 0xa52e2c8b 0x19e811b9 0xf7b8404f
+ 0x9e70972b 0x913a6bba 0x48e10b9a 0x7e011ed3
+ 0x734c76f4 0xe1599757 0xaaae937b 0x51100d47
+ 0x7d17124e 0x35ecfd95 0x2e953315 0xf5ff688b
+ 0xed16901e 0x90428937 0x9e2070af 0xe4ef8897
+ 0xc443333f 0xeec2c3ff 0xd194031d 0xff460594
+ 0xd1e9cd6a 0xb1d70ef3 0x341500c0 0x9e90b9cb
+ 0x469a4773 0x8de2477c 0x117fc666 0x4f9054ff
+ 0xc927dbed 0x67c74937 0x3baf30ea 0x40936d14
+ 0x0c9ac739 0x041137e0 0x3d059009 0xb7f5421a
+ 0xbb0126af 0xce177510 0xf6de21c9 0xb5f3c076
+ 0x0f2fff63 0x86eafd85 0x802188eb 0x0f7bbf4d
+ 0xcbd9c89e 0xfd9a22f3 0xedd2c250 0x6c58a749
+ 0xa14f1a77 0x4d530eee 0xacf5122f 0x5ec73aa7
+ 0x6fafb960 0xa183fff7 0x3c70bbe2 0x02633064
+ 0xe58b5614 0x1134d39d 0xf8f881d2 0x69d59940
+ 0x868185e9 0x9d0890fa 0x7d9bf165 0x5bb8db70
+ 0xa8945b39 0xa7d9feef 0x1407353f 0x43d1617e
+ 0x120d0afe 0xaac34195 0xa57168df 0xcb961fd5
+ 0xc3224007 0xf59e9967 0x8f15d16a 0xa1316dc9
+ 0xcb26f47f 0xc527ea60 0x926d3346 0x2c6b68de
+ 0x1b3006fb 0xb2756318 0xaca473af 0x272b57cb
+ 0xd60d2c46 0x4e95e451 0xa2f394f1 0x683214d2
+ 0xb9605bdc 0xa115d6e4 0xa6083a9c 0x68dc3d47
+ 0x5a8f50ce 0x169b2488 0x27208e8e 0xe58ad90b
+ 0x45d701e8 0x4112922f 0xb9aa2b3f 0xede2202a
+ 0xa392f747 0xb4bfa7ad 0xce1fd86f 0x70ef8742
+ 0x20953b5b 0x13ebd4ee 0xf595936b 0xc9e8dedd
+ 0x9500e2fd 0xb310d9f5 0x85a0bdde 0x61c15820
+ 0x1115f8d3 0x8785f7be 0x41c14891 0x7933dfc2
+ 0x71d1b4ba 0xa23b8102 0x5faeb285 0x8e57ea62
+ 0xcc850793 0xc87939d2 0x59e20f98 0xca1a3b98
+ 0x33b06934 0xee5a3331 0xbdd162f3 0xaeef3bbb
+ 0x78a32364 0x605fe058 0x46b26fdc 0x12837872
+ 0x16099e34 0x085f188c 0xfe5e4cc8 0xd93cd8a1
+ 0x6dc59005 0x28316a2e 0x9195e418 0x0e214d25
+ 0xfe0e5b53 0x6e9c76fe 0x1dcb3a92 0x9913d086
+ 0x645123e4 0xc908a92b 0x4b88bf41 0x2097f641
+ 0x80e244b8 0x5e003730 0x5a0f58d3 0x16088761
+ 0xd28591cf 0xce0fe936 0x045553a1 0x26c00405
+ 0x6e4bf3f0 0x64290de6 0xe9a19aff 0xd87bf684
+ 0xed4daf00 0x2810c0db 0x128cfee0 0x1e508c6d
+ 0x49467929 0xbbfb2b1d 0xd9c32057 0x6ece8a60
+ 0x22e2d5bc 0xd1abc452 0x1d6ad999 0x8a55d752
+ 0xbb1d05d3 0xfddd231d 0xd4015973 0x5622ec3b
+ 0x09dd64f1 0xa9d70f43 0x68e7297e 0x339d7030
+ 0x4e895dff 0xf4670d21 0x0936a426 0xd122a9df
+ 0xd216184f 0x387ba4a0 0xc8243d33 0x856697d0
+ 0xf6abcaef 0x84d7a4a4 0x4dbee515 0x93c9e8e5
+ 0xb29193a6 0x4f1f7d60 0x76155a55 0xdcac3a70
+ 0x8bfabc0d 0xf9a3e9f4 0x0394ae0e 0xf6f119cb
+ 0xabad1677 0x10acd369 0x978d5da0 0xcf002655
+ 0xe82fb631 0x0aa94bc1 0x722d2cd4 0xd719a922
+ 0xa757ba81 0x81fbd096 0xf9a551e2 0x76149e2d
+ 0x1ddc020a 0xd372ecdb 0xd9638c1a 0xa1e88b8a
+ 0x50078c91 0x214850fe 0x25d6b007 0x727de93e
+ 0xf03cc409 0x053795dc 0x1ef31bd4 0x2f5c10c9
+ 0xfccebcd1 0x44ac9ee9 0x80428302 0x4acef759
+ 0xd91b7495 0x31f152e1 0x72ed8eff 0x0085114e
+ 0x81bbaf96 0x84ecedff 0xbef7bb0c 0xb5c848db
+ 0x23b345ea 0xab388f25 0xd30f937c 0x71f79868
+ 0x0f525e32 0xdbfa767b 0xcf0de0b8 0x7af15903
+ 0xa11eee62 0x70cf63d5 0x4458af62 0x56d50908
+ 0x9da8403f 0x221da3cc 0xbd0aade5 0x183d267e
+ 0x3e156120 0x9b509a32 0x3b5ddce8 0xc11669fd
+ 0xa917981a 0x7da3cdc8 0x783babe8 0x51bf0088
+ 0x9c00c498 0x1e874f17 0x46deb849 0x0fbf988e
+ 0xa5446f28 0x7e6f0822 0x6cf41525 0x6c72bffc
+ 0x720c723d 0x2b55fe0c 0xf18768ef 0x5aab31f9
+ 0x789ced3a 0x96310d66 0xeffc13c8 0xf876eb4b
+ 0x3d873163 0x13fc946d 0xe8d8ddf0 0x210b9b69
+ 0xfc303435 0xc0445e72 0x0837fd7f 0xbae8ddf1
+ 0xc0e9c2bc 0x995280dc 0x46685fda 0xf3af75d4
+ 0xe7ded1be 0xdcafd05a 0x206ee6d7 0x8f6033be
+ 0x215b79ce 0xed907e16 0x5601af38 0x0973ac88
+ 0xd53350d2 0x9d16abdc 0x4d370a82 0x844bd339
+ 0xf794dd28 0x92d34b83 0x059613da 0xaad853c0
+ 0x0b58b92c 0xe930d280 0x3ae36754 0x49b1d72f
+ 0xa886613a 0x88d74d88 0x8f56701d 0xf1e818ee
+ 0xb2795931 0x48b661e2 0xa221d210 0x3bb81578
+ 0x418b80ff 0x3e86c6b9 0xaed36f80 0x4141343e
+ 0xad1ceaa3 0x3329cbdf 0x857da730 0x31d4a9a6
+ 0x277c5e78 0xb32c94da 0x674203b0 0x0c449415
+ 0x4677ae79 0x25abf896 0xa1091aab 0x2825835b
+ 0xe679b6e2 0x205d8da7 0xe4e1aac8 0x95830755
+ 0x40e6e4bb 0x610cfbdf 0xca1b1c44 0x3fe7308d
+ 0xb3e930fa 0x076bf0d8 0x354e1b7f 0xadf06e4d
+ 0x6db0643a 0x36d4bc97 0xeb22d83e 0x3099966f
+ 0xac073c10 0xd5e437e5 0xbbb909a3 0x4feb8b83
+ 0xedd7f264 0xbdcadef1 0xf3086990 0xece45074
+ 0xf952de8d 0x6292598b 0xbc80abbf 0x7393cb7b
+ 0xb5a2f4cd 0x1ca8c4c2 0xaf05b117 0x0672793f
+ 0xd0d075c0 0x48418531 0x8d011a01 0x15c51e9b
+ 0xc51e7e51 0xa974bab5 0x95109a8c 0x06eb3ca1
+ 0x87a097f0 0xad14a4d0 0x314191b1 0x5627955e
+ 0x458c6134 0xb10f0a92 0x96acaef3 0xd90457f1
+ 0x4de019ae 0xeba25c70 0xebe5c14b 0x158d3898
+ 0xf0691820 0x161df4bb 0x136e0c58 0x3af86045
+ 0x1bc6e724 0x23101c77 0x153431d4 0xd609b2c0
+ 0xaa1ae519 0x2be7a14b 0xe7bcc16c 0xc2dc8079
+ 0xb49905fb 0xd95e3f33 0xb92e63f4 0xd3cd2c98
+ 0x190354d7 0xa62dce06 0xfa600031 0xefc6efd3
+ 0x1d3b654c 0xb639ccd0 0x2b7b0983 0x63eae4b9
+ 0xd54b0d33 0x08aa5eea 0x99be4902 0xcc1078a1
+ 0x1c0c0341 0xc82720e1 0xdcd9417b 0x9fa87ac3
+ 0xa77356a3 0x9f35e75e 0xdc6b4248 0x1a146d1b
+ 0xa7fbb7d9 0x1e21490a 0x27b91430 0x594975c1
+ 0x54d33a1c 0x12096461 0x2427f1f5 0x110d0724
+ 0xa72c6e3d 0x6e09f629 0xbcacad98 0x9732276a
+ 0x749107e5 0xebf47d70 0x6b6c4c63 0xfb22cb3e
+ 0x3684453d 0x3dfc9181 0xc5bbe7eb 0x7d3464f3
+ 0x7db3db12 0x69f8d54a 0xc3cb57e9 0xa3a6c364
+ 0x5408adfb 0x260f2384 0x5baf6f43 0xd3791026
+ 0x2719238f 0x68d4f3cd 0xc67bcdbb 0xb23e47aa
+ 0x33c0e8ec 0x8eb2ed26 0xb45d0553 0xa0a51edf
+ 0x63d94bbe 0x3b7997e2 0xa8247af2 0x66af60ff
+ 0xa5cf96d5 0x357bfd57 0xea573081 0xd953943a
+ 0x4b70801a 0x5b18a19c 0x83547b44 0xd1225a31
+ 0xaaecdc1d 0xd9bc2dc5 0xdbab4697 0xe837c74b
+ 0xf3afdeb4 0xa4ae7b27 0x67f514d5 0x135d8d7f
+ 0x718cc961 0x3fa14697 0xd76b4e28 0x7377f49f
+ 0x0e1723b2 0xb2b34ca2 0xe5a713af 0xd0f2eef9
+ 0xd425d842 0x1bf685de 0xfc688084 0xe01d0db4
+ 0x2b33af87 0x523f542e 0x583949fb 0x716d5dcf
+ 0xf2b516b2 0xbbb40cb1 0x28a395af 0x416d8047
+ 0x3add469e 0x2bdda5d5 0x4a0bab2f 0xbb26bb5a
+ 0xa5c4458f 0x87aea38d 0x0d84fbbc 0xc91c5dee
+ 0x226d403f 0xa89803b1 0x362f6461 0xd327ccc3
+ 0x0d3172fe 0x5ee8f57a 0xed862a4e 0xc9e72fca
+ 0xaf37a7bb 0x0e823c62 0xc1f1d185 0x32e22081
+ 0x72427d25 0x9492c7ad 0xaed29771 0xdff35edf
+ 0xbdef0a5e 0x5d9d2f18 0xa0bc1ee9 0x0c397a65
+ 0xc911d530 0x481d294c 0x1a84ce5d 0xf5a5504b
+ 0x22cfca7e 0xaff7e8e9 0x0394d9b1 0x7832305b
+ 0xf853d344 0x89571b4e 0xd2e2bfdd 0x0c72e467
+ 0xb236aea0 0xde6cabce 0xfce515d5 0x0f8c4779
+ 0x3c74d971 0x81b0b3e3 0x2d4c4ecc 0xf4da0ae0
+ 0xa0947a82 0x47609cd3 0x6f81ad8f 0x2bf75b0c
+ 0x46cf40b8 0x344f9edf 0xbad2a5af 0x9e13f884
+ 0x205ea013 0xd54fcb5d 0x20a86658 0x739cfb67
+ 0x7971ea26 0x7841375b 0x649b81e7 0x31ab0179
+ 0xb0730487 0xdba21463 0xa5f6cb07 0xd4f92687
+ 0xca5fbcda 0xc8de464e 0xc7263f7b 0xb93678db
+ 0x1b3ca8dd 0x4636a901 0xd4a16614 0xf96c26e1
+ 0xc58c8da6 0x2965c74a 0x59ff32cd 0x4d77e88e
+ 0x23843ad3 0xa85b9246 0xfd2d5bef 0x1257bf58
+ 0x9c0aa762 0x9ec8ac35 0x77d9bc0a 0xa2bbdee5
+ 0x56d690cf 0x5cdc4461 0x3ef6afed 0xaeb51f80
+ 0x492d6fc9 0xfe4df4b1 0xce23606f 0x40eff82d
+ 0x715eaa41 0xa4e8b2ad 0x19c3e72f 0x9333d4f2
+ 0x9b902cf0 0x70c9bbd4 0x9901f889 0xc342ab6d
+ 0xd36492ae 0x38dc739c 0x0928ffce 0x8d724b2b
+ 0xd5b29bbc 0xa0ce992d 0x8856178b 0x026948bf
+ 0x08809e04 0x541c960d 0x210b71e0 0xf1b9e474
+ 0x85bca8cc 0x90ce42b7 0x6682b7d8 0xe0c50c48
+ 0x25a8075e 0x33dc1ab1 0xf0ff1627 0x89d6d8e9
+ 0x4790ebbb 0x7ba5cfb5 0xe97327bb 0xb06fa0d6
+ 0x7db34b48 0xdf96d115 0xce3fb871 0x03b1557c
+ 0x7eb6d43c 0xceaf3826 0x247e0851 0x840637d2
+ 0x9f979955 0x08f67a6a 0x525d8295 0xdee447c9
+ 0x91ed75bc 0xe4960419 0xb9700051 0x0344b46e
+ 0xbd6b6827 0xa38ab219 0x817e8ba0 0xe86dd20f
+ 0xb9240181 0x4765dd8c 0xc59d8325 0x9b8cfb61
+ 0x6632d86e 0xaf8c2a11 0xbc47dcfb 0x26544374
+ 0xe2beca9d 0xf6355863 0x4291bd11 0x94489a1c
+ 0xc52476f9 0x05fb6fda 0x4d315edb 0xa8e285d0
+ 0x0cd624e3 0x599b9d80 0xd21d8746 0x4d9f3528
+ 0x3a634276 0x9a1f1481 0xa5a015ee 0x6639f7bd
+ 0xd5d20e14 0xe90d52f1 0x3318a40d 0xf3f4f5db
+ 0xb92a7eb5 0x2d730844 0x8282ae9d 0x2f369ced
+ 0x5355d63d 0x984d651b 0x47041c38 0xd65d225b
+ 0xfc2c77a5 0x8822efe6 0x49087974 0xff3c04f0
+ 0xcba80501 0x7e6e1c68 0xa7b7421d 0x6b906771
+ 0x4b2b3b5e 0x233421e5 0x78d0d0d8 0x222dad37
+ 0x875b564f 0x336662fa 0x2bfae345 0x47ff9f91
+ 0xb3e7beee 0x3a7ae071 0x3bd0f29e 0xaee9af97
+ 0x6f0d58fd 0xb5147803 0x32a6ea49 0x70a0a245
+ 0x25b0ace0 0x281e4418 0xfcb5553f 0x1151518f
+ 0x50e67760 0x068c8b22 0xbed7234a 0x4120c5d6
+ 0xec22b6d5 0xc600bef1 0xfd9bd4a2 0xa29451b6
+ 0xcd51bac2 0xc1bd0e26 0xe8432d25 0x2deb06a0
+ 0x9ae54a7a 0x536799e4 0xef4fab62 0x4c9f3e5d
+ 0xeda219fb 0x5947eebd 0x2dec73ae 0x11da15cf
+ 0x94ddc24c 0x2c28b710 0xa5c3620c 0x0722dd36
+ 0xedd98464 0xafa8e23c 0xfd750c04 0x829dc6d6
+ 0x6ee56697 0x2cf2380f 0x3cfa8cd6 0xfa42971f
+ 0x415ad936 0x0b1fea9a 0x65c8b5d2 0x1a5828a6
+ 0x4295092a 0x54596d12 0xa419acef 0xefeddbf9
+ 0xcabda915 0x053abb3c 0xe4b38d10 0x141d9ebc
+ 0xcceb3e75 0xa4fdd9cf 0x9450f718 0xe2a7e7e0
+ 0xbf98f6a0 0x4885a7d5 0x53f871b3 0x0a57e4cf
+ 0x22b36b98 0xd705d611 0x12db0f11 0x546186e1
+ 0x2629257f 0x74587452 0x2659526c 0x2913ca70
+ 0xb3d5b27e 0x1040c827 0x18a192d1 0x2731ba8a
+ 0x5865a15d 0x12b9dce7 0xd0b05fea 0xe35d2de2
+ 0x0f1fc309 0x28df230d 0xcac0338a 0x724f0b25
+ 0x0a36bfeb 0x4c196443 0x392068ee 0x8cc1a2d9
+ 0xbc4f0871 0xea33986e 0x22e90aa1 0x2a43d9e3
+ 0x81214348 0x3745f469 0xaed24012 0x092a728f
+ 0x6b5bb659 0xb46d810d 0xc146cfa5 0xdd3e6954
+ 0x20d6283c 0x0a47baee 0x45aa3873 0xe2c0795b
+ 0xf1cb3519 0x566f951f 0x5e34314d 0xab31c4f1
+ 0x10e0b305 0xfa7d0a3c 0x9adc26fc 0x55fc8af5
+ 0x90314c7d 0xa54954f9 0x27cc0f21 0xbe30da42
+ 0xa04432b0 0x670e176c 0x904a4df4 0x4342618d
+ 0x8b43d3f8 0x086fbc28 0x54954d7a 0x73502d23
+ 0x2ebbaa2e 0x2549f553 0x06946ef5 0x61b621d4
+ 0xafde5d4c 0xbc0faabe 0x0e110c04 0x44ddda52
+ 0xad3883ba 0x1464c595 0x3c5d9f28 0x95573165
+ 0x3e92db93 0x41f19b03 0xb60a4c71 0xf519a623
+ 0x5dc2b562 0xa822e25d 0x09ba6793 0x5e3f5958
+ 0xb80ae32a 0x3f2a8120 0x50cab916 0x8a2664c7
+ 0xe9a0730e 0x74ef9c02 0xbe1b891b 0x8cdeb1cb
+ 0x8f05f87e 0xf4ebaee8 0x12fab9dd 0xfbc8ab3c
+ 0xe6d443b8 0xbaaf9253 0xa4b28356 0x3a105c02
+ 0xb3ceb634 0x26c2d231 0x1e509d45 0xb010dc16
+ 0xbaed93e6 0xffd995a5 0x2274c579 0x081c20f5
+ 0x0e890545 0x9bf20a67 0x534d1668 0xbe0d8a9e
+ 0xe6a3b6a6 0xa19826e8 0x8c369600 0x9b00d171
+ 0xdec22ff7 0x0de50b44 0x4ca2d735 0xe9142307
+ 0xb2d75e8f 0x74018651 0x8a93b3dc 0x679f8926
+ 0xf216f6dc 0xaebc58e5 0x820b6760 0x6e49feb6
+ 0x3ad58a8f 0x62ab576e 0x31829e46 0xb1a2bd35
+ 0xd3db9735 0x248c8e9a 0x8db52fa6 0x8b65b2de
+ 0xebfee08e 0x0d2bdaa1 0xb3d9a282 0xde361f30
+ 0xc121c45c 0x12cdcb27 0x8d7ab875 0xcefac8dc
+ 0x573f8424 0x783fb263 0xbc2d8f2f 0x04f05791
+ 0xa880912a 0x22042163 0xb7891d1d 0x27a3b82a
+ 0x70e35ee9 0xb0b74dc8 0x72b51ef4 0xc074941c
+ 0xeb765569 0x8fba1f5b 0x044aaefa 0xc0db48d0
+ 0x31bed72a 0x7f5ad220 0x132e1da0 0x4cc7e7b5
+ 0x145a80c6 0x39367173 0x0689d163 0x96822f9a
+ >;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x10>;
+intel,date-code = <0x2202012>;
+intel,processor-signature = <0x306a8>;
+intel,checksum = <0xe44a4ef2>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x10000000 0x12202002 0xa8060300
+ 0xf24e4ae4 0x01000000 0x12000000 0xd0270000
+ 0x00280000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x10000000
+ 0x00000000 0x00000000 0x17021220 0xe1090000
+ 0x01000000 0xa8060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6
+ 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xe5ffd18e 0x9c10c032 0xef097758
+ 0x5b44fb3b 0xabbc6973 0xb040312f 0x6267ab0a
+ 0x35ef3655 0x694c0da7 0x6eaf94db 0x293feb5f
+ 0x225a62bf 0x550edd27 0x8e4da670 0x9afcd29b
+ 0x62ad52f1 0xddcdc6fb 0x059e156b 0x9472a491
+ 0x20d8e6fb 0x7041822d 0x5af9c518 0x7e6c342f
+ 0xb113a311 0xdec46650 0x91c8a91c 0x157cde4d
+ 0xec563d5d 0x92470d0e 0x373c488c 0xf18a8f84
+ 0x757fa8ad 0xf8959ce7 0x95e1e3c9 0x47347f30
+ 0xfbd6e4a3 0x18c2f2e2 0xb6c6eb68 0xd2a81838
+ 0xa44964bb 0x36893d55 0x0b411d47 0x5addcf15
+ 0x47584269 0x972c08b3 0x0935b300 0xec7d36a7
+ 0x1c373823 0x487626be 0xacfecd64 0x6688c83c
+ 0xb96f01f9 0x2b6c9719 0x97e955da 0xc4f3b25a
+ 0xfcf12050 0x961bc5be 0x53ebb1e4 0xdc7deaa3
+ 0x3b86819a 0x7c498a21 0x129bc1b6 0x2aa5c324
+ 0x6fb58020 0x0c8e24a8 0xb7c1f0cf 0x37287581
+ 0xf417e311 0x5fd7b8cb 0xe615c56a 0x6a6c6aa7
+ 0x46c97d63 0xcc71adee 0x239b7483 0xea6750f7
+ 0x17bae7c2 0xbf4de5e1 0x6c37a1e0 0x314fc762
+ 0x68bffc94 0x4069875c 0x60d3a593 0x3a923495
+ 0x70f7a899 0xc959db6f 0xfd440374 0x0be4f668
+ 0xc15b74e9 0x9eb15fc7 0x04dc5939 0x1c2d0faf
+ 0x8ca378c9 0x15aaae90 0x2c53e471 0x2ada3977
+ 0x750d6d3b 0xd3e27cdd 0xf63ece4c 0xcbbf9463
+ 0xf0b26aad 0xacc9dc7e 0xcb2131eb 0xc2da14bc
+ 0x01b57719 0x901319e9 0x86b16d25 0x89fe5e27
+ 0xfa3135cd 0x51ebcf8e 0x91b36807 0x6efb87a1
+ 0xbe05489f 0x0461f6c7 0x4f1ddb59 0x007a7e35
+ 0xdde5c360 0xf137a520 0x153d9512 0xebe49940
+ 0xb81727b3 0xdff04ada 0x504811d5 0x6192a2a1
+ 0x418ad287 0x44278f0f 0xc8d70fcc 0x5d5953ca
+ 0xeca4ae03 0xb507f886 0x90a6726b 0xec2c60b6
+ 0xfe003923 0x8cd52bb2 0x87397bbb 0xec98c514
+ 0x28501352 0xd5518d70 0xf3258a19 0x15e4e0f4
+ 0xae272618 0x164ece6f 0x19b5449c 0x2717cf2a
+ 0xffee98cf 0xf18d6c04 0xffb6f744 0x5ed2cb50
+ 0x9421a65a 0x76150be7 0x9689d9eb 0xe6ce395b
+ 0xa5857737 0xe51b5a0f 0x5cc95766 0x365a6f04
+ 0xee8a6d1b 0x219da3e7 0x81004946 0xce4f00f9
+ 0x852eebd0 0x3a39b164 0x96863ddd 0x43b46d69
+ 0x064e138b 0x2ac312a3 0xe7eac082 0xb958803f
+ 0x3138940e 0x4c1d5d99 0x49e9ed02 0xeb3a904e
+ 0x14c2ce82 0x8449493e 0x3cdd6dbf 0xdddb592e
+ 0xaae39fca 0x163c6e65 0xee5a0e52 0xae8c2f8c
+ 0x07fd1416 0x406bd0dc 0x52811c06 0x18316363
+ 0xf954d2eb 0xa8ec83dc 0xe24996e9 0xc92af45f
+ 0x5a73f1d0 0xf5b9948f 0xa6960f5f 0xef3d1266
+ 0x97ac2b43 0x20ce72fe 0x0d774f96 0x29653967
+ 0xca765fe6 0x470ded7f 0x42a9b87e 0x3c9cfb36
+ 0xcd9354db 0x0f2fa889 0xb35e5c71 0xc3da1e0d
+ 0x85f9bfd0 0x1afc94a1 0xf05524d4 0x2b2138ef
+ 0x3c77b905 0x55d26a06 0xcc3a045d 0xad05a556
+ 0xef80f5b7 0x3ca6e8de 0xc40df9e4 0xdc5bdd8a
+ 0xdee9349d 0x258ecbc9 0xa29faf0e 0xf41daab4
+ 0x47af938b 0x6a6a1cf1 0x7a3d2f4a 0x11ede796
+ 0x61f25722 0x6864a35e 0xb4d96fae 0xcdc6a722
+ 0xce64615d 0xef56b252 0x0b89020b 0x2a1ac24c
+ 0x582c3283 0x124f274e 0xf6a58fdc 0x847c262d
+ 0x31517f9b 0x8cd34984 0xc60f7204 0xa94875c1
+ 0x12abf4e6 0xfbdd2b29 0xdb51a1c1 0xb10f9ec9
+ 0xc52b5d3c 0xfa5f75c4 0xb63c6fef 0x8ccd4fe0
+ 0x74b6cc11 0x013babd9 0x0bc30209 0xb1597dcf
+ 0xbda5ac76 0x0371d13a 0x67252505 0xf3081369
+ 0x0d7a4e53 0x25f89a9f 0xd0d9e53f 0xa25d897d
+ 0x822f83e0 0x3008eae6 0x428d3320 0x9890d235
+ 0xfec38910 0x56c87e21 0x7f7f594b 0xdf46866a
+ 0x34a34b40 0x0987267e 0xb47033d1 0x331f5d40
+ 0x935a4ec5 0xab480f95 0x1803d8e7 0x00e2e693
+ 0xab18b053 0x1cf706dd 0x7dda5849 0xb422e2e3
+ 0xba5fd0f3 0x3aee2ce1 0x33b21147 0x5fdec0d7
+ 0xd509d289 0x61187bf4 0xf7687684 0x48edbc90
+ 0x519dcd0b 0x77f026eb 0xc52eb470 0x1d4dd497
+ 0x2fa69c9c 0x8fcfef0d 0x1ed8a0b3 0x9312d199
+ 0x596b55be 0xc8c68e56 0x6aa8dc28 0x3100ec70
+ 0x737bfff7 0x40e51f14 0x695baf1f 0xad786740
+ 0x6278b108 0xcd066fb0 0x74f9d22c 0x9dd7d6f6
+ 0xc9d8d081 0xb82f32ae 0x797beeed 0xa34ce8dd
+ 0xd57ad56e 0xa4bec19f 0xe2cc7268 0xd2b85f64
+ 0x4faf835d 0xda6f3933 0x28397cd3 0x010b5a17
+ 0x6d904bfb 0x26fc2b26 0xdc7b440c 0x4e985f16
+ 0x92fb8abe 0xab8d7b77 0xb906004f 0xb0bdac98
+ 0xee64230b 0xe768ebf6 0x3c96a534 0x4e2aa084
+ 0x5f4c5c4a 0x7bff964e 0x4b4fdde3 0xfc36550b
+ 0xe90220be 0x0056c3d4 0x65599751 0x00c71265
+ 0x83011ea4 0x5bd8113f 0x616bc4ab 0xcdbbfdab
+ 0x187abde6 0xcb0b2059 0x24244c94 0xa05cac8b
+ 0x15e0e4eb 0xe93d7e1e 0xd4016e08 0x8144e1e9
+ 0x1c256625 0x841f4379 0x782edb54 0x6a70674d
+ 0x5de874f9 0x075b423b 0x71a8adc4 0x3f7c5ed1
+ 0xc045ffb0 0xd94e8bbf 0xf7ff3edc 0xb1d3aab5
+ 0x7e78f4b5 0x2e9f0c64 0x17efe45a 0x2a2dd14b
+ 0x9eda4e59 0x2c3689c7 0xe15e5efc 0xf4f11a2f
+ 0x0edb0000 0xf7afa169 0x05558b03 0x1ed6aa69
+ 0x8174d362 0x922814cc 0xcfb1c31c 0xe7cbaba6
+ 0x6aa77d7a 0xea48a37b 0x23b7a2af 0xc2b602da
+ 0x03076aeb 0xef659eb5 0x3c2833e6 0x7dd8521b
+ 0xe80a8ff3 0xe3af24d2 0x6d15f067 0x1c05b90b
+ 0x306e10ea 0xd45b1a99 0xc65a85ac 0xb4ddda13
+ 0x1f2b0bbe 0x716421c1 0x33c2f599 0x0deba688
+ 0xa44de1c2 0x1d33833e 0x3d454600 0x07cdb855
+ 0x57b42914 0x2b3015d8 0xf7893119 0xa754aa11
+ 0xfc8bab1c 0x6aabb3ff 0xeb9a35ba 0x9433e224
+ 0x88225f56 0xb3376d46 0x9203225d 0xfdd591f8
+ 0xb4452f63 0xeccbcf9c 0x60d07a28 0x021f7b69
+ 0xc355e1f5 0xdabc3f4b 0x3a3925e8 0xffc15e96
+ 0xd37cf717 0xbd580830 0x9527f96c 0x91b1119b
+ 0x527baf62 0xdcd8cb14 0xceff6ef8 0x7a64b27d
+ 0xc2bced42 0x62693867 0x171d7869 0x82a502af
+ 0x98c84c3e 0x8a0dd77e 0xcb01c7bb 0x91373992
+ 0xd28e7281 0x487d2036 0x1e98d48c 0x60f56b74
+ 0x3199129d 0xab6205ca 0x95c811b6 0xce78fbbb
+ 0x92f0b76a 0x2a448276 0x975d891a 0x5c945417
+ 0xc2ff2603 0x045c8a04 0xc8b41e0c 0x461623d6
+ 0x640bb5bd 0x386feb24 0x5ecc0bdc 0x1c56fd05
+ 0x3c6b32a1 0xde2d2b8a 0x1f76b23e 0xc78c9108
+ 0x5febf899 0x3c55d772 0x226aa903 0x4916231d
+ 0x44928c52 0x7dfe932a 0xb4420968 0x1997faaa
+ 0xb9a3dab1 0x5bec5d70 0xcb5dba0d 0xcc4052bb
+ 0xfc26b557 0xf04a044a 0x83ad1b1b 0x781935b0
+ 0xd3fe7102 0x210b7f15 0x0002e47f 0x95709de3
+ 0x7ccbab76 0x701f28b1 0xc2151880 0xb88778eb
+ 0x33bfeeb0 0x1498b52f 0x2694b5bb 0x85332e53
+ 0x103b6ddf 0xb410d999 0x3687d2fe 0x92fdecd7
+ 0x6c7d4179 0x89a2fc40 0xc8a2a4b0 0xc140a6a6
+ 0x36b20598 0x3c6e05b6 0x2d67b87b 0xc09b651c
+ 0x2cd528f0 0x2e2f38b7 0xee7fa2fb 0x84075fca
+ 0x98bacf32 0x2b965415 0xd019df29 0x83a5e980
+ 0xde8322b6 0xf592ef9d 0x22be4a4b 0x5568e883
+ 0xaf95393b 0x43b2f828 0xe44f0894 0x0c17a91a
+ 0x46271d4c 0x3ea308ba 0x757ab95f 0xeb841efb
+ 0x86def448 0x806b7e0a 0x704125ce 0xb103138d
+ 0xc70bdc0f 0x9b020964 0x8d5326c3 0x22265cf1
+ 0x07e9158e 0x1b77f0e7 0xc4249a77 0x0ec99717
+ 0x91f9860f 0xa22527bf 0x1c351901 0x8dd07723
+ 0x1b10062a 0x75db2a1b 0x300f48c7 0xe2b47dc5
+ 0xf9be873e 0xeb78cba6 0x48a02062 0xe57a4d34
+ 0x8d6d6093 0x0f3748af 0xea0fd86a 0xbb57cac5
+ 0x1aae31a2 0xc68f6732 0xfe6d09a2 0xa8ec7655
+ 0x15fb82e4 0x0fd62a02 0xde712cc6 0xa6983f8d
+ 0x0a511623 0x1802140c 0x8882d161 0x0639f7be
+ 0xca8fc8b1 0x87cc7eb0 0xaad2814b 0x53736976
+ 0xd6c2aad2 0x2ad078d6 0x8d098537 0x0d9e1f65
+ 0x060ed492 0x47fe55bd 0x56e2f9d9 0x7dafc9d5
+ 0x1f3b21fb 0xb781e9ee 0x3861d899 0x5e532398
+ 0x59813473 0xf0bae8c3 0x7b621c48 0xc6e42f38
+ 0xa779e75a 0x44fb061f 0x8e4d99dc 0x96139885
+ 0x520df1c4 0x166a3b5a 0x555f53c5 0x41f8e765
+ 0x7622012b 0x6d26b80c 0xec4292ee 0x8192e701
+ 0x6833ad36 0xa0ac765a 0x479ac6b6 0x3297deb0
+ 0x93190386 0xf349a9d8 0xff138d81 0xba18b630
+ 0xe8f5410b 0xbfe20c22 0xc233505c 0x40beb25e
+ 0xcae9866d 0x6eb2cad9 0xc2836a6e 0x66df20fe
+ 0x8faa6eb5 0xb8dfb4de 0x29e2391e 0x4e25fa37
+ 0x9b894dea 0x6210200d 0x7ebcfc1f 0x45e25079
+ 0x3a5caa11 0x45a740b0 0x3bafebb8 0x9e50294c
+ 0xa2503207 0x22f6a91d 0x04da4b6a 0xe89358d3
+ 0x5ac8cfcc 0x8b6f0821 0x85743e1c 0xf84b5389
+ 0x456ae17b 0xa51507ca 0x50cf0243 0x2701b851
+ 0x21060ad6 0x35b0d234 0x4ef230c0 0x8e8a8f08
+ 0x161949c0 0xff340399 0xdaafa36c 0xe333ae22
+ 0xeebe25ab 0xd8db6722 0x40a89344 0x9684d1ec
+ 0x357a81c5 0x6821d9d4 0xfac791fb 0x4f2dcb85
+ 0xb67017a6 0xd3234e88 0x279d5ca4 0x3f63ba99
+ 0x21622bbf 0x07caf2eb 0x8b7076ab 0x8e4ebcbd
+ 0xd10a0bfb 0xf55952f9 0xf488837a 0x8ffae6fb
+ 0x71d76515 0x44fb3730 0x7a7c61b7 0x1bd1e2de
+ 0x8a92eaaf 0xb21e7751 0xb28522e5 0xedd3b173
+ 0x03882afd 0xfab1fd71 0xf5b8d389 0x0073ba5b
+ 0x83c4bdde 0x0ae4303c 0x445ca8b9 0x6b757b77
+ 0xfeb103e9 0xccd485bc 0x0ad310c2 0xe2192e5c
+ 0x4dec1c82 0xee1986b7 0x352a80c8 0xa8151575
+ 0x6fe0d28f 0x771c3d8f 0x871e87e1 0xdacebc59
+ 0xe8ca49f6 0xb926a028 0xa6b3e515 0xefa223a5
+ 0x8a54e354 0x897e5a4d 0x21b8224d 0xd416f2ec
+ 0xcbe7f0bd 0xb2447fea 0x9e793f69 0x0fef54ad
+ 0xe8b59733 0xcf1f604a 0xb6fcca90 0x828ab637
+ 0x544d1f6a 0xd3f9bb08 0xd33e5002 0xf2bb0902
+ 0xbacb7493 0x8f49ee50 0xc8b026fd 0x548c5f6a
+ 0xa69ac56c 0x3048c9fe 0x2f4099be 0x5e2db858
+ 0x86af0440 0x63ad790c 0x2f21596a 0xa678770e
+ 0x6d35026b 0x60e5ffd7 0xd8c5ee84 0x0e8f4a5f
+ 0xb32368ab 0x06ce6d77 0xaff9a8a7 0x9b7bfe08
+ 0xf1c41bd9 0x5d97e65a 0xae3185d0 0x04a81ce0
+ 0x515afaf2 0xcc0bed19 0x7fa0ed19 0x29d747da
+ 0xb3be6d42 0xaea891fc 0x596327f6 0x169685d7
+ 0xaec527c3 0x58d7f4a5 0x1ec8f0fb 0x5121ab73
+ 0x77482d34 0xb9374023 0x593f2fb7 0x806bd03c
+ 0x0c3d2df9 0x48db6a6a 0x8d4e3bf0 0xf7c0b614
+ 0x4277692e 0x8bd2a7e8 0x2ced9478 0xd6d0958f
+ 0x1f11c590 0x64eea64e 0xfd0d9181 0xfe337731
+ 0xf2e4d68b 0x5f5c5e22 0xba1be116 0x01947bd2
+ 0x6e6f5cf0 0x99ed610b 0x1c9c6591 0xb5b9e932
+ 0x1881f045 0x4a07d22c 0x2534671a 0xf98db0e6
+ 0x3eecedcc 0x03d88a38 0x473f8803 0x0e964e29
+ 0xe7865109 0x067ce3a2 0xb67ea547 0xc9478d11
+ 0x77824680 0xe44e870b 0x26409f76 0xf56325e4
+ 0x83850a25 0x5778bde0 0xeccc9cbe 0x2b2a510c
+ 0x00fb4fe5 0xb1e44d88 0x25017b6f 0x6a07d28a
+ 0xc63259df 0x6138534e 0xb365098e 0x9063c5e5
+ 0x45457621 0x80a16d60 0xd8ace6a1 0xaf8e5612
+ 0x5a59035a 0x4a7ece35 0x2b54eda7 0x5bc3beb6
+ 0x87b79dfb 0x49145956 0xecab73c6 0x9d1929c5
+ 0x8d9a403e 0x62670b62 0x301612e1 0x55661d64
+ 0xfa4642cf 0xe995b648 0x678dfc40 0xd4ee70c9
+ 0x9b148b4a 0x26feeb0f 0x34e8c1a4 0x0eeeabf7
+ 0x3185cd83 0x17fd5de8 0x0eb47a60 0x8b390214
+ 0x813d2606 0xa98680cf 0xe1320b2c 0xb1cff298
+ 0x55954a20 0x2832306f 0x022e5c5a 0x248ace30
+ 0x12fdb8ef 0xa1ccd483 0x46722ba6 0x383957a3
+ 0x89d7daab 0x5bea5c37 0xeffde670 0x1bb5755c
+ 0xddb34251 0x97edd945 0x7538c562 0xd219d3a4
+ 0x7dd10fff 0xcd755fca 0xb6b74e08 0x953a094b
+ 0x6d5c8acc 0x17d6a577 0x5cf9cffa 0x6bef258f
+ 0x257f161c 0xefa3596d 0x2e55d01d 0x8accce49
+ 0x78637612 0xb709a740 0x9d40a46d 0xf1b76593
+ 0x941bb52f 0x72e8e334 0x731d55a9 0x28eb1126
+ 0x64488b68 0x1bc8609c 0x7ae731d3 0x6cd9e9d8
+ 0xe3f193b1 0x704102dc 0xc9c217ef 0x7334e9c6
+ 0x077bf32c 0x111e8651 0x0add1b81 0x50aa4ce6
+ 0x58931d65 0x70c12f8d 0xf958146c 0x313ec286
+ 0xb66ae984 0xeedfc1ed 0xdff5b926 0x7cd6767a
+ 0x909e1f2a 0x2e67ce4a 0x210d17a9 0x2407a7d6
+ 0xa9454c46 0x4ab7af23 0x674e4a24 0x5df3499f
+ 0x87fe9d85 0xd538b623 0xd715790a 0x5a3b6924
+ 0x98286489 0xd0e054fa 0xe0d52748 0x2cbd3b28
+ 0xed241d2b 0xf1522f35 0x2d3f6b3f 0x18adc4ba
+ 0xaed87ae4 0x8fe52079 0xde6f1284 0xbce2c970
+ 0xc3562e43 0x33707205 0x74af0b7c 0xa90d5bb6
+ 0xae850b5c 0xbba8bb6e 0x3805510b 0x78ccd517
+ 0x28139afa 0x9aa3a321 0x02577c39 0xd1339b37
+ 0xc73ab16a 0x6d219868 0xc47f0ed1 0x3d679319
+ 0xa6a0518d 0xbd8ef844 0x6c70a676 0x9f5e745c
+ 0xbbec38c8 0x085b1e7e 0x38c80048 0x73eb179f
+ 0x158edda6 0x086b980f 0xaef51250 0x4513fb22
+ 0xabb57e49 0x41d5ccde 0x47d8186e 0xc405fbba
+ 0x985881c8 0x4c20555c 0xd4719f4e 0xeb24d863
+ 0x163fce3d 0xc4083220 0x5cd27427 0xd21b3dbc
+ 0x97fd8af7 0xe936b66a 0x024e597f 0x83d45caa
+ 0xa16c668a 0xd869cff5 0x63b6d757 0xb780941a
+ 0xaa96f2d9 0xbc0661a8 0xe924336b 0x587a0117
+ 0x0dd9eba3 0x5908b928 0x336d386f 0x119dc036
+ 0x5e1ed561 0x4ad4f319 0xcf901dc1 0x154b5878
+ 0x16aec960 0xf13a5643 0xa755e201 0x9159b4ff
+ 0x983ef850 0x65d3e929 0xe310a2ed 0xd58bf035
+ 0xa2553613 0xc51f589b 0x68f3371c 0xca99ec10
+ 0xdbfc78c9 0x80c4c5dd 0x0fac0fd7 0x38a34baf
+ 0xb5a662b7 0x0be19a25 0xfae5d7ed 0xf1bfceb7
+ 0xc261e162 0xbe4990c3 0xb8911d6b 0x87738701
+ 0x9e8b4304 0x6cec1d55 0x273e2ee1 0x345a2f0e
+ 0xd5fc410f 0x25dc0844 0xff54749a 0x2a0a5364
+ 0xc8791715 0xe086fc97 0x5f757613 0x45e92b76
+ 0x87892ea6 0xe3b0e43a 0x7c648ab0 0xa3a8c54e
+ 0x5fe5a0ee 0xca7a4261 0x555ddb79 0x9d4f2a63
+ 0x74f06878 0xde200798 0xd37ae5f2 0x55d7a6c0
+ 0x5fb2dc4e 0x5b3ad326 0xb65765f5 0x63427670
+ 0x46f5c7d4 0x12307e35 0xe8a28a17 0x9db32fa6
+ 0x9adccbdd 0xc6184cae 0xfd78192b 0x926d5791
+ 0xe703b4e8 0xa5e69e45 0x88223b08 0x9e3b8a28
+ 0x0457a863 0x2a37db05 0x9153400a 0x3b8b14ac
+ 0x69bfe269 0x06f5e4bf 0xd464afa5 0x2d9a82f3
+ 0x602a92db 0x87338f91 0x67f209dd 0x5ce4b3e6
+ 0xe2809522 0xb7f94017 0xc9ece863 0xb6aeed89
+ 0x378f891f 0xcad6a973 0xb96c6cf1 0x46c60a01
+ 0xb88459d8 0xfe3e3779 0x0513a1ce 0xf400f2dd
+ 0x8f23cbec 0x2fb511e5 0xec80e04f 0xdb208487
+ 0xd314d381 0xed5d8b84 0x6da657b7 0xcb1bd0bd
+ 0xc4e9fc1e 0x2dae2765 0xa6d3b0a0 0xa1faa26b
+ 0x7cf2f561 0x4d52e032 0x1beef152 0x95950541
+ 0xf18c3dbe 0x495d0818 0x42c5a22c 0x59888e35
+ 0xeddd5cee 0xafd86b9e 0xaee47e02 0x23beeaed
+ 0xb9d6ceec 0xbeedec29 0xac32e51c 0x04c197e3
+ 0x20a135d1 0xb11448a5 0x3484ae14 0x0434b359
+ 0xef3ec2c8 0xcce90290 0xc695b789 0xd3a8b71f
+ 0x5872d621 0x722b6196 0xb616d479 0xab8a66d8
+ 0xd2e7e112 0x12349531 0xfc3e4ad3 0xb2ccdd87
+ 0x28a3bd51 0x3b16e2ed 0xf8ce78e8 0x20731a86
+ 0x5e719bfc 0x2d7ca49a 0xa3992d3f 0xe551f317
+ 0x6832634c 0x7deb4d22 0x7c0bc8f4 0x275a5782
+ 0x3fdd330f 0x138d4c4d 0xa4157e8d 0x34f2b9be
+ 0x1bf52bac 0xb9813b28 0x519dfa35 0x01e58ca5
+ 0xbc3677d8 0x939cc9d5 0x5915cfdd 0xb97cdefa
+ 0x1d15657f 0x1e72f016 0xfd2c4677 0xbc97145f
+ 0xab079f7d 0xed5e5972 0x1e190e78 0x9a1231ae
+ 0x1ed9090b 0x895ccde4 0xa937b0e6 0x60ff5871
+ 0x5847392b 0x785e17b2 0xd89b12fd 0xa0b5c7ea
+ 0x72d71263 0x9f11a27e 0x4e5409ae 0xb5f2edfa
+ 0x8798948a 0x452e74e3 0x68c95f07 0xc4f6430d
+ 0x6c46c2c4 0x2fafa74b 0x6a44c53c 0xdf7ce8c2
+ 0x51c96835 0x62970522 0x919cfe27 0x5849c94e
+ 0xbfb44809 0xb7dde12e 0x999f66cd 0x0c074754
+ 0x8f4ac0bc 0x652f9fd5 0x52b7613c 0xe04835c5
+ 0xf17a34a5 0xe2218efd 0x858ca16e 0x47eac06b
+ 0x54f66a40 0x7ea88066 0x83eb9445 0x13d13637
+ 0xfaeb75ff 0xc9a083c2 0x2cc0fd30 0xf513d44a
+ 0xf6b96811 0x4941a7a6 0xc1819a10 0x9639200a
+ 0x2cb196ad 0x8317352c 0xf10c2931 0xe713a326
+ 0x22aa792d 0xa1efb4cc 0x7c6b53d3 0xb6c87d92
+ 0x86216481 0x7f5a7163 0x2e46a131 0x70f18df8
+ 0x18964efd 0xb56cf7e8 0xe7341960 0xeec703e7
+ 0x921c12b3 0x3947abd7 0x81875a3a 0x74cce2a1
+ 0xa164461b 0x4c6dbfa3 0x8d918aa3 0xfef73a33
+ 0x66e39687 0xb464d9b4 0x42228636 0x88e403fb
+ 0xac22ae57 0xe017291b 0xf3a45b09 0xe35c2277
+ 0xe315a695 0x3f5d403a 0xed440354 0xf7b40fcf
+ 0xf539d67d 0x800f9254 0x254d971f 0x5a922b5a
+ 0x0b04d196 0x8861c8c4 0xf1066432 0x9365cca9
+ 0xcacd3a7c 0x58c10ddc 0xd411a203 0x3acda8b6
+ 0x7c3896d3 0x58c14180 0x4f17bb0a 0xcb535d3d
+ 0x00aee06a 0xa014e8e4 0x2370aebe 0x8db2890d
+ 0x32101f94 0x93e5364e 0x20947d1b 0xd14146ba
+ 0xc491e61c 0x53035a42 0x8d35e879 0x9a8b306b
+ 0xeee182bc 0x9123dcfd 0x0e077297 0x28e25da5
+ 0x165ff375 0xc95a7f9a 0xc32843c7 0xd224f615
+ 0x64ad8b3b 0x9da90396 0xa231630e 0x71806a0d
+ 0x4e2f45d6 0x21444bbe 0x986bf26a 0xd9090d2f
+ 0x0ee65758 0x54895661 0x072e3f23 0x07e350af
+ 0xe3953270 0xa7c0cfb9 0x02cecb83 0xc3f14f38
+ 0x90d6cb0b 0x16376fd3 0x359c1d26 0x86d946e7
+ 0x91dbf84d 0x81a9b349 0x9036f826 0x7932d603
+ 0x927edf94 0x18bc8d03 0x4d678541 0x17ade635
+ 0x19bb81f9 0x71f045f3 0xf4bd25ad 0xa5760638
+ 0xe756688e 0x38b29d3c 0xfb30460c 0xc68ac4d6
+ 0x06377294 0x5a327276 0x778b4a68 0x4ffa7472
+ 0x069c56e6 0xe933498a 0xef04089b 0x780a3303
+ 0x66b1e1b3 0x1c393723 0xa86b3411 0xec767268
+ 0xb97f8d53 0xccb0d910 0xb011bd4d 0xee12bfaa
+ 0x48eef80b 0x0a142e36 0x7f8f9f10 0xc78629de
+ 0x3efbf202 0x530716e3 0xd10ba525 0x54967e80
+ 0x4c6b7c05 0x9fb26e7a 0xa4a9d9c5 0xbba6cb3e
+ 0x858eb19c 0x0d944403 0x907b8c70 0xcb5f37d8
+ 0xe91b1536 0x6843e3f1 0xc8afabb4 0x8504d9e9
+ 0x1713f6c2 0x530febc2 0xb620862a 0x75e2ed50
+ 0x94163707 0x66ea0482 0xf1708bb7 0xf0677075
+ 0xeeaffe1f 0x686330a2 0xb8dfeae5 0xc6e58ec2
+ 0xcb0f62b5 0x7107d06f 0x1bce36af 0x9d99bf9f
+ 0xe79909a2 0x19a15e0a 0x82a563f5 0x5c98fb06
+ 0x594d5329 0x5e57fbe7 0xff9bbb06 0xabd6be40
+ 0x4eef225c 0x5f6062b6 0x2b61c656 0xb2f00977
+ 0x03f2993d 0x0b4f95c9 0x9ad27701 0x2e237d78
+ 0x3d0a0c21 0x81e74efd 0x7905da00 0x8853df61
+ 0x32691529 0x1e14d54a 0xcc04a569 0x4958dedb
+ 0x36482baa 0xc1ab8a83 0xca3a8c67 0xfc375fd0
+ 0xc4389c07 0x5331676a 0xdd7b2d25 0x3e524eaf
+ 0x0ed82c44 0x68dae84e 0xd141036b 0xa21d5e06
+ 0xf525fe25 0xb74132bf 0x4040013f 0x8e92884f
+ 0x97fdb7fe 0x4c0553c9 0x328a75f5 0xce5bd4a3
+ 0x4902450f 0x33469577 0x4e073acd 0xd6d93c91
+ 0xfdb7244d 0x8669429c 0x9b4c1690 0xaaccec1a
+ 0xcd1ce8e2 0x30b1b01d 0xde97ff08 0x5554be5c
+ 0xb76ae32c 0xe984e71e 0x6fb89f89 0x1d51899b
+ 0x73163e05 0x540721ff 0x39263d03 0xf51d365c
+ 0xd9957a33 0x80bb35d1 0xf3f8a2e5 0xd43952d3
+ 0x7c98bbcf 0xdb29fbdd 0x26ffef42 0x52fbe30c
+ 0x01c6cbaf 0x7bb65fa8 0x53015450 0xae920a47
+ 0x24bb2057 0x7c673ea9 0x602dbd7d 0xeb92994b
+ 0x821bc8c0 0x4fec8b18 0xf1361cf0 0xb5e99442
+ 0x7ea3b92c 0x843eb0c8 0x1631c6a5 0x38be4f7c
+ 0xaecb2505 0x96725799 0x0466b1d6 0xdbc36c3d
+ 0x15f6981d 0x2e52c8c5 0x3481eb3a 0x3384627d
+ 0xea53cf95 0xf77dec97 0x66897bc7 0x0154a1d1
+ 0x1ec26446 0x9a47eded 0x2cda2248 0x96bb98c1
+ 0xe3d4d28a 0x11533c0c 0x9bea583d 0xfe5180f5
+ 0x86180cdb 0xf067b1b2 0x581197de 0x36c2bf1d
+ 0x2d140238 0x646d3f89 0x4b4a1acb 0x35530ccd
+ 0xe87387d4 0xb2f29390 0xf9cdf459 0xae2d1802
+ 0x10d6781d 0x9a680a03 0x61f55f5c 0x6112cdde
+ 0x39aea13a 0x0986c57d 0x1274ee81 0xfc2902b0
+ 0x12035d41 0x4d3cbddf 0x2f1f6136 0x1114e937
+ 0x2b578520 0xdf9f5811 0x5545e0f9 0x3204025b
+ 0xd916ef5a 0xfb5e8c36 0x76a7b93e 0x40a881cc
+ 0xed314574 0x81fee9ca 0x5e664127 0x2567fedc
+ 0xccc24545 0x9bd63c33 0xdc875d2a 0xa991afcb
+ 0xcffb484c 0x8861201b 0x6a67fe7c 0xfcda7cba
+ 0x1f4a828e 0x7124de5b 0x93b7e81f 0x1fb316b6
+ 0xb3b7420b 0xe8dedede 0x5f2a3a0a 0xf89340ba
+ 0x4c155d52 0x7278d04d 0xa245f4a3 0x5dfcf0fb
+ 0x1adc4713 0xb85377fe 0x35138a96 0x5fac5600
+ 0xdecf8d38 0xdb4c1ffb 0xdb07469e 0x26af2008
+ 0x71531c05 0x4f269510 0x332a0060 0xcb08dff2
+ 0x48eab1db 0x88a86507 0xdf6d0501 0x36202cca
+ 0xef4cf30f 0x9abb662d 0x3ed7f0ed 0x43bcf26b
+ 0xfd9f88af 0x52b7abff 0x24d20402 0x8dbc246d
+ 0x530452a4 0x4b3714e2 0x91d99e62 0x4be86c83
+ 0xcfa73676 0x814cc9f1 0x49a05ec7 0xea75e853
+ 0xb2fae459 0xe049bf6d 0x95f9d78f 0xb512a76f
+ 0x763fb577 0x124d55c3 0x77080e28 0x89672472
+ 0xce578237 0xcf59d373 0x17a45e2d 0xaad3c482
+ 0x50161024 0xbdc8ade7 0xe9e474e0 0x30db1f08
+ 0x3e595fba 0x0bdae343 0x35fdbe82 0x03192612
+ 0x61ba73cc 0x40f41633 0xa9e1d9ca 0x4ab72299
+ 0x4e9bcaa8 0x87c09d3b 0xd5a2e624 0xfe31b004
+ 0xe080acaf 0xf52cb59f 0x0ed69789 0xbc7aae50
+ 0x097d0dc9 0xb250835a 0xac4d2b62 0x72d775ab
+ 0x29ed99ad 0xda94151f 0xd12aaa71 0xd5c01185
+ 0xb51d0b88 0x0c9d6f2d 0xa48394c5 0xdbb2d57e
+ 0x3ae4d70a 0xd6add3d7 0x4b3dc251 0xafd1be1f
+ 0x90687d0a 0x84a07d85 0xe78eca6b 0x68f66aa8
+ 0x6b64a3ee 0x44a0e334 0x8085791b 0xcc8b9893
+ 0x600ef53c 0xa4cb69a7 0x9d30e312 0x1128eb16
+ 0x4d51ce44 0xdc2d0736 0xdf605b7f 0x854b83b3
+ 0x2ee28ee7 0x16c889b3 0x2550ce0f 0x4cff4ea3
+ 0x42b5a123 0x36773c1c 0xde358d32 0x063a64a5
+ 0xca073150 0x8e55ad6d 0x358ee044 0x1afb0721
+ 0x9a3e1062 0x2bbaa6af 0x29679c34 0x7e073a7d
+ 0x3d8e6461 0x8146fcbe 0xbfc9ae45 0x893e8e8c
+ 0x06f5508c 0xad4dc27a 0x8eb524c1 0x089d6e8a
+ 0x06814420 0xf195e6a0 0x5b9651b1 0x7f55737a
+ 0xf23fb3b1 0x270a10c0 0xc6d1adf6 0x16ef7ed1
+ 0x463492b7 0xa71a7736 0xc8685ff2 0x46eebcad
+ 0x4489c299 0xc46ea5cd 0x0ba37c88 0x8e744be1
+ 0xeb2b315f 0xb3c180ee 0xab833e40 0x2223d8a2
+ 0x4e18ba02 0x830b5559 0xc100c3e5 0x89bca4cd
+ 0x43646b89 0xa94d0f31 0x517daa8f 0xf0633802
+ 0x5f2d9886 0x476f3e91 0x80a20ec9 0x65039697
+ 0x58c021c0 0x06adc086 0x9a7a6ddc 0xedd48be9
+ 0x85383dec 0xb5dea0f4 0xd3b438a3 0x20ef6788
+ 0x0334f429 0xc98fbe55 0x11a38f24 0x020f0f38
+ 0x1d6b4e0f 0x4a99af26 0x1af1d8ca 0x0f61b492
+ 0x2df039b8 0xc8db9dd9 0x978c1442 0xd43af75a
+ 0xaba9101a 0x47778b7d 0x58a36cad 0x2b062567
+ 0x1b68832e 0xe730afd3 0xd083acdf 0x4beec818
+ 0xe15e1338 0x134b9a6c 0xe5a65f74 0x82d64ded
+ 0x552ec9e0 0x36ff5ade 0x0eec84ce 0xdff77b21
+ 0xc2337bb4 0xb038c393 0x8661a487 0x1c47bd8e
+ 0x1664330e 0x4793df4e 0xba9c357b 0xbcecf2a9
+ 0xf8484a42 0x89e26341 0xdea84220 0x7173ff02
+ 0xf091e01b 0xd1789105 0x8876a7a3 0x249398c1
+ 0x35a96528 0x2c9cd555 0x8f9026bb 0x4683dfe7
+ 0x0d322c0e 0xcfdeadc2 0x2e6d657a 0x214f7fad
+ 0x1a6feb96 0x70f24984 0x1e2e919b 0x709a412c
+ 0x7c0820e0 0x4372a2e0 0x3a5fca7b 0x7e098692
+ 0xdcdadb6a 0x83bbaece 0xcf7b4ee7 0xa15deb5c
+ 0x0a5cd850 0x76432692 0xd633e87a 0x3b106b75
+ 0xfb1f675d 0xe2d75d53 0xe525819e 0x639ec794
+ 0xaf3fce1e 0x31f7c2fa 0xf62eed9a 0xa581cbe4
+ 0xdcfd3909 0x683b240a 0x5e609152 0xc011e52c
+ 0xe2b40996 0xd4a9c582 0x34f1b16e 0x67fcc219
+ 0x58554b65 0xee82ffee 0x574d2326 0xb3f72df1
+ 0xe75f740b 0x2081271b 0x21039cca 0x274f5ed9
+ 0xad0e16f1 0x92958ca8 0xbc9af36f 0xde0d81c0
+ 0x8e549069 0x7b675ff9 0xc469cd4a 0x7e9286fe
+ 0xad955974 0x5ddaf59f 0xb444e3c3 0x48c0da41
+ 0x08496091 0x13083e2e 0xd769c0e7 0x12c9c1ac
+ 0xad0eaf72 0x9fb4dc0e 0xba8dec9f 0x92ebb8b1
+ 0x17cfb953 0xbd1aa608 0xa7488be0 0x07020299
+ 0x680e40ed 0x8a1eb384 0x337e047e 0xa68e6188
+ 0x8063eb28 0xc3415333 0x4f744899 0x5c55f1d1
+ 0x8f71d1e3 0x06a02111 0x258ecec0 0x1fd1abc5
+ 0x11c9dd66 0xa4dad7d5 0xedaeecfc 0x1b172d78
+ 0x0f433cf3 0x43c8a18e 0x64af2f5a 0x08374214
+ 0x1bd2211e 0x42d44134 0xd45b7bb7 0x7f981a8e
+ 0x8ca78cbb 0xe2f1e4d6 0xb75e239a 0x43be0647
+ 0x374a4e0e 0xd9bb5925 0xcf158582 0xf229203f
+ 0x70b8fb27 0xa245b677 0xd2d8d526 0x192a9510
+ 0x83a24fed 0xdb806e4b 0xd667de62 0x79119c25
+ 0x28a26484 0x259f5647 0x38653837 0x27084263
+ 0x291da1ad 0x08629d2d 0xc645256f 0x5f5bfebc
+ 0x1c2c0a54 0xd29134d5 0xeb5f441c 0x4dcab922
+ 0x96bd0275 0x9ce7c4f4 0xe74c3ecf 0x4d7ebf4a
+ 0xccb98c87 0x4087533d 0x4bc9d551 0x1dd9b49f
+ 0x470182f8 0xe5764366 0x5cbcbbf4 0xa6e3cd20
+ 0x0beefab1 0x71e29729 0x023e9dad 0xc2816f30
+ 0x8c17209c 0xdb579ef7 0xc2f38a82 0x81219d22
+ 0xa7eaac3a 0x51b5e632 0x8cd23cfa 0x1c14a751
+ 0x4e942e65 0xa8c73ba0 0xf949b6d7 0xe78fc2f1
+ 0x89974a85 0xed5eb057 0xdee39bb6 0xed8c0cab
+ 0x2a526c09 0xcfe60940 0x0d610c5e 0x484899ee
+ 0x92d4c509 0x3d822950 0x9cc21bfc 0x8635bf03
+ 0xaca9721d 0x654adb87 0x9642ee22 0x292d68fd
+ 0x55542325 0x511bb3dd 0x0db3d7c3 0x219cfd34
+ 0x70b944ee 0x9a96b3bf 0x7c7dbd32 0x47237e37
+ 0x93236405 0xc16867a0 0x71709059 0x6a602b3c
+ 0xe0c44204 0x21c010ac 0x1114b7b2 0x994094dc
+ 0x66e3fa66 0x6abb8afa 0x3dd1c246 0x1f35d1c9
+ 0xd6386abd 0x5a1e92ef 0x8214e792 0x1742727b
+ 0xea5724b8 0xd117876c 0x8aeae636 0xc339960b
+ 0xb491151d 0x1cdc17a3 0xe583b556 0x3927556b
+ 0x56b62c9e 0xda90add3 0x2c40a08f 0xb062928a
+ 0x31b7fb6e 0xa031f67e 0x9ac90564 0x09a4791e
+ 0x8675a98c 0x14d0da71 0x9c0e13a7 0xfad7410d
+ 0xdfeab9b3 0x8f798c75 0x2359e65a 0x666c074e
+ 0x79a559b9 0x297a6cfc 0x9b80d725 0x231980df
+ 0x5aba4182 0x6b8930ed 0xfad6b3bf 0x03b99393
+ 0x2ce7b19b 0xd12071f4 0x4c2d0204 0x54833fe9
+ 0x1c8d0433 0xb32e9724 0x02a273bf 0xc52a9d5a
+ 0x62aa1fa6 0x68ca34ad 0x1ac94c91 0x1794e58d
+ 0xa74691ef 0x0e22c1d3 0x66be923f 0x6f6f2c45
+ 0x15ce79a4 0x3b8c9c40 0xa11ff2f9 0xb18f0e8a
+ 0x1e0763e8 0xab472e97 0xd011b9c7 0x7f4cd77e
+ 0x60291b08 0xfc4746db 0x1101cb2f 0x7127e03e
+ 0x39dd8454 0x9e18e09b 0x449c71ba 0xc1106522
+ 0xee38c53b 0x8e30f2a1 0x30a5c398 0xbde9c623
+ 0x49ff1078 0x36360091 0x2b797c99 0x553ff25a
+ 0x063174e2 0xcd5fb064 0xbaf1c003 0xbbbba060
+ 0x9e7bd54a 0xe3bb944c 0xa7586ca4 0x4586a706
+ 0x5bd43e12 0x9139b258 0x5962b23e 0xb20799b8
+ 0x23ef9a21 0xb505a156 0xed51d1ae 0x82dced20
+ 0xfed14015 0xe50de153 0xcb1de201 0x20407156
+ 0x6e6c8c9f 0x4e33f0f7 0xb61006ea 0x81bcca2d
+ 0x8fd94695 0x576fe5c7 0x074ff2db 0xd707ccf4
+ 0x581503ca 0xfcc1c71b 0xcfc21805 0xcb8251a8
+ 0x69361b9a 0x14ec2bbe 0x2df3d3f6 0xa5e66081
+ 0xc5c70b23 0x5dfa028b 0x22338ffa 0x1932168a
+ 0x11a0ed71 0xf676d717 0x823b48d7 0xe02bc37e
+ 0xfc624cac 0x03795ade 0x845ff149 0x5b657ed4
+ 0xbe434a2e 0x8a77afde 0x3615b39d 0xba7200d9
+ 0x674e4541 0x12f91c65 0x694cb6ab 0x22e78146
+ 0x8f574161 0x58f35068 0xce5b6f43 0xd1f0f21e
+ 0x1be73d35 0x7b2dd03f 0x39bf4987 0xd9a00a8b
+ 0xa1285004 0x64b6871e 0xee7377af 0x51d239c8
+ 0x54521a4e 0xcb661f19 0xf26dc3a8 0x8772cda3
+ 0x2c827fa9 0x16f8f76f 0x1de27a89 0xf8b4a070
+ 0xab4243b4 0x2c910203 0x1fc663ad 0xe310c2a3
+ 0x9476000d 0x11e66913 0x346d42a8 0xa513fd81
+ 0xfc260d0f 0x54c7995a 0x228585bc 0xefc0dbb0
+ 0xb9999ca4 0x7dfc9ec2 0x1556bde4 0x2749b83f
+ 0x753da831 0x5d415b40 0x763debe4 0x94a2d4df
+ 0xcc560707 0x08a3de8d 0x7d9f0997 0xe3ff555e
+ 0xa8d05131 0xc75a1e9c 0xd696df91 0x633551a7
+ 0x7ead2980 0x6c8b10b9 0x2b97f758 0xa785048f
+ 0x744ba0dc 0xd350342d 0x6dbdccaa 0x10a5e224
+ 0x0963176d 0x71a4325c 0xa9bfeca5 0x73c90b16
+ 0x5f486277 0xc897525a 0x57a8234d 0x78a73eeb
+ 0x2640604e 0x1598efd9 0x135cb408 0x486bd6d3
+ 0xef98ab1b 0x0ce2744c 0x6a690e5d 0xa65e3af1
+ 0x5263f69d 0x10feb14e 0xd857d93a 0x94d52946
+ 0x52162f56 0xe72a0b7d 0x3e7d7b23 0xdff4b663
+ 0xcbad0105 0x4886da29 0x7d5521d0 0xa37ad7b6
+ 0xe4e79a68 0x4c6cc715 0xbb746a87 0x0a222aa2
+ 0xcff26451 0xe5b51d1a 0xd786658d 0x0edc8ddc
+ 0x95a91b59 0x2b7b0dd7 0xc4003ca8 0xa90e574b
+ 0xf6d1b6c5 0x0880fcaa 0xda31fd31 0x5e2c3099
+ 0x9e9cf801 0x069347b4 0x66215bcc 0x8698d9cc
+ 0x5d53b7ce 0x3b0a3025 0x1765a598 0xba1f4f29
+ 0xa6017b4a 0x1db6bb22 0xd9b63caf 0x531e2601
+ 0x24fa819b 0x8ab091a2 0xbbc3b96a 0x6d4e061d
+ 0x5f7b1d3a 0x13fc2925 0x564b9a06 0x2b0d7a90
+ 0x933a10c7 0x8aa5e38a 0x9b79b254 0x9444c3c2
+ 0xd737212d 0xb13f74df 0x7193f8c1 0xa95f42de
+ 0x6c5a39de 0xf1263eb0 0x57c322ea 0x829cf7e7
+ 0xf8c58a2e 0x2408ad3a 0xe05fa2b7 0xf61c2132
+ 0x47bcb102 0x167f4eb3 0x6a9ca49a 0x03c76439
+ 0x69fa64cc 0xd715eab1 0x26b9ff58 0x65a0d362
+ 0x168ed37e 0x1c4f3752 0xd4e7d4de 0x26e7865d
+ 0xfbd25786 0x347be5c6 0xb610ff32 0xdae6720f
+ 0xa01ff608 0x4a093466 0x7dce182b 0x5eb3cc1e
+ 0xadd542b4 0xfff308b2 0x9deaf2fb 0xd6fa9bac
+ 0x7f1729b9 0x54ae192c 0x85e8e337 0x840f4bfc
+ 0x566993d1 0x2cf2af63 0xf86cbf7b 0xa78e4aa1
+ 0x11806adc 0x06070f3d 0xa833c724 0x3ffef088
+ 0x78febf93 0x2cf6ae38 0x8c4d8867 0x485a2845
+ 0x003a5def 0xe8d1b155 0xcb675ca8 0xcf4fec75
+ 0xb7fe3198 0xf5da0890 0x9f1599b4 0xb952a34e
+ 0x7f1bc151 0x362e7bbb 0x063507a0 0x99c65de4
+ 0xd5130eb3 0x8613ee0b 0xfd6a8987 0x01c85a32
+ 0xed25a8ce 0x3e81114d 0x3f96d0be 0xfa892912
+ 0xb8ab3d94 0x7f10a909 0xe20ebd7e 0x30e900b7
+ 0x05b0d117 0x423ee599 0xd09dacd3 0xd385eb38
+ 0xa0839eee 0x4f29f80c 0x7f253d6e 0xbc757a72
+ 0x326c615c 0x43e0c8e2 0x21771593 0xa71e6072
+ 0xf355b109 0xf2852219 0x9a6ab7b6 0x9b1c39ad
+ 0x2edb942f 0x51234e78 0xbbe44b02 0x9078446a
+ 0x1ff97b31 0xb2967297 0x5f1267ac 0xf8ccd029
+ 0x846ccba2 0x3a2a8297 0xf60c1eae 0xd8b7a467
+ 0x517e2f1f 0xe0087865 0x2a952fa4 0x75963d8d
+ 0x1bb14788 0x1375edb3 0x941303f7 0x6738a9c9
+ 0xe3c99502 0x5f42b5ec 0xb53339d3 0x65896cac
+ 0x8d992623 0x8b09fdc1 0x47e71464 0xc09733fb
+ 0xfa8cfbfe 0x898ba57d 0xe74ca247 0x4fc21f9f
+ 0xc880e39a 0x973ab5b7 0x78628ad6 0x8a6fe2a0
+ 0x92a5a189 0x7a6ff475 0x7db81d10 0x81deea09
+ 0xa4ff44fd 0x056e383e 0x7cd47b4c 0x2182a401
+ 0xd0c4ce01 0xeb313665 0x8bbb4e07 0xbb4d4a64
+ 0x15fe41cb 0x53a267ce 0x8ee4ae7c 0x01678630
+ 0xda477daf 0x7ee74db4 0xf6e9228b 0x06c57aef
+ 0x5b9c8e80 0x1e05611b 0x26682707 0x7111591a
+ 0x7646cb3b 0x20f2d117 0x4dae44a9 0x395871da
+ 0x54e6172c 0x4ab90f71 0x65209536 0xb3b57c85
+ 0x11d10b0b 0xc9e50256 0x47521f5a 0x4416012f
+ 0x6d8042b6 0x454542fa 0x77f0fea3 0xce983a27
+ 0x40f74a4e 0xabc2d476 0xcd6a647d 0xca633336
+ 0xeb7fa467 0x4b14425f 0xd7abae15 0xb9652306
+ 0x990b3a98 0x03e6f53a 0xa5f3ec3c 0xb40c953f
+ 0x5cd8470a 0xbf93da01 0x89a52e28 0x5984bd42
+ 0xe9d93e95 0xa3b67bbf 0x099ff7cf 0x07b80086
+ 0x20cdf1cb 0xcfbbdb2e 0xeb0da53d 0x33b82f36
+ 0x28fb9aca 0x013bb5b7 0xcfbfefea 0x7f4400d1
+ 0xd3ad108f 0xe32556f3 0xa9e77e41 0x92955338
+ 0x3d102663 0x63bde93f 0xbbb464c4 0xcc1ff27f
+ 0x7968d83b 0xca32b52d 0x1d4102ff 0x84cfd695
+ 0x8303a6d3 0xc6f8ba69 0xdd78d4ef 0x98b195af
+ 0x50f92a15 0x2066c503 0x61281597 0x5d0197b7
+ 0x59e6f0be 0x02423dd6 0x9b4d27af 0xb2a0755d
+ 0x72f2eb4e 0xdb5aa819 0xddb42e82 0x9688712a
+ 0xb430e384 0x6484e439 0x44f68d17 0x195c6382
+ 0xddee2db1 0xd9af2e18 0x7fbd30d6 0x2ac223db
+ 0x0d3bd809 0xec982530 0x1a41d13f 0xef2849a8
+ 0x9c233021 0xc074a29c 0xe7b8f28f 0xd0adf47f
+ 0x23cdf70d 0x6795e85d 0x1168d6ea 0x3c8bb4c7
+ 0xad1d00c9 0xf3eeb5d0 0x2f950982 0x9fbbde57
+ 0xdc733a93 0xb23e2beb 0x7dbb34af 0xf1323cff
+ 0xf6c9a9bc 0xf69900a6 0x9447ab0b 0xf03e55fa
+ 0x2816479b 0x487e507e 0x494087fb 0x0601d1ef
+ 0x27c86510 0x6a14691a 0xb78886de 0xe89e8c84
+ 0xf2cd073c 0x09144b70 0xa82227a5 0x82f88828
+ 0x71f7e10a 0x6c2b46b6 0xf813fe7d 0xf76d2602
+ 0x044d5543 0x9e1b6a76 0x967ad7b5 0xe803b0a7
+ 0x01e03dd9 0x6d5c94d8 0x112357c8 0x8e0bfe12
+ 0xcc8c7461 0xfbc1c562 0x9838886c 0xa16c46a7
+ 0x020631ad 0x70fb29ff 0x5f5f1795 0x07a762e8
+ 0x3467aa2b 0xd396d1d7 0xa12aaf4c 0xd3c13b6b
+ 0xf158d7dd 0x17b1317a 0xd847a91d 0x7612ab8e
+ >;
cpu@0 {
device_type = "cpu";
- compatible = "cpu-x86";
+ compatible = "cpu-qemu";
reg = <0>;
intel,apic-id = <0>;
};
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cpu-x86";
- reg = <1>;
- intel,apic-id = <1>;
- };
};
tsc-timer {
cpu@0 {
device_type = "cpu";
- compatible = "cpu-x86";
+ compatible = "cpu-qemu";
reg = <0>;
intel,apic-id = <0>;
};
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cpu-x86";
- reg = <1>;
- intel,apic-id = <1>;
- };
};
tsc-timer {
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __COREBOOT_TIMESTAMP_H__
#define GPIO_ROUT 0xb8
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
+#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
#define LPC_EN 0x82 /* LPC IF Enables Register */
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
+#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
+#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
+#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
+#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
+#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
+#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
+#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
#include <linux/linkage.h>
+/*
+ * FSP common configuration structure.
+ * This needs to be included in the platform-specific struct fsp_config_data.
+ */
+struct fsp_cfg_common {
+ struct fsp_header *fsp_hdr;
+ u32 stack_top;
+ u32 boot_mode;
+};
+
/*
* FspInit continuation function prototype.
* Control will be returned to this callback function after FspInit API call.
* Stack top pointer used by the bootloader. The new stack frame will be
* set up at this location after FspInit API call.
*/
- u32 *stack_top;
+ u32 stack_top;
u32 boot_mode; /* Current system boot mode */
void *upd_data; /* User platform configuraiton data region */
u32 reserved[7]; /* Reserved */
+++ /dev/null
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: Intel
- */
-
-#ifndef __FSP_PLATFORM_H__
-#define __FSP_PLATFORM_H__
-
-struct fspinit_rtbuf {
- struct common_buf common; /* FSP common runtime data structure */
-};
-
-#endif
#include "fsp_ffs.h"
#include "fsp_api.h"
#include "fsp_hob.h"
-#include "fsp_platform.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
#include <asm/arch/fsp/fsp_vpd.h>
-
-struct shared_data {
- struct fsp_header *fsp_hdr;
- u32 *stack_top;
- struct upd_region fsp_upd;
-};
+#include <asm/arch/fsp/fsp_configs.h>
#define FSP_LOWMEM_BASE 0x100000UL
#define FSP_HIGHMEM_BASE 0x100000000ULL
/**
* FSP Continuation function
*
- * @shared_data: Shared data base before stack migration
* @status: Always 0
* @hob_list: HOB list pointer
*
* @retval: Never returns
*/
-void fsp_continue(struct shared_data *shared_data, u32 status,
- void *hob_list);
+void fsp_continue(u32 status, void *hob_list);
/**
* Find FSP header offset in FSP image
void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
/**
- * This function overrides the default configurations in the UPD data region.
+ * This function overrides the default configurations of FSP.
*
- * @fsp_upd: A pointer to the upd_region data strcture
+ * @config: A pointer to the FSP configuration data structure
+ * @rt_buf: A pointer to the FSP runtime buffer data structure
*
* @return: None
*/
-void update_fsp_upd(struct upd_region *fsp_upd);
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf);
/**
* fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#define FW_CONTROL_PORT 0x510
+#define FW_DATA_PORT 0x511
+#define FW_DMA_PORT_LOW 0x514
+#define FW_DMA_PORT_HIGH 0x518
+
+enum qemu_fwcfg_items {
+ FW_CFG_SIGNATURE = 0x00,
+ FW_CFG_ID = 0x01,
+ FW_CFG_UUID = 0x02,
+ FW_CFG_RAM_SIZE = 0x03,
+ FW_CFG_NOGRAPHIC = 0x04,
+ FW_CFG_NB_CPUS = 0x05,
+ FW_CFG_MACHINE_ID = 0x06,
+ FW_CFG_KERNEL_ADDR = 0x07,
+ FW_CFG_KERNEL_SIZE = 0x08,
+ FW_CFG_KERNEL_CMDLINE = 0x09,
+ FW_CFG_INITRD_ADDR = 0x0a,
+ FW_CFG_INITRD_SIZE = 0x0b,
+ FW_CFG_BOOT_DEVICE = 0x0c,
+ FW_CFG_NUMA = 0x0d,
+ FW_CFG_BOOT_MENU = 0x0e,
+ FW_CFG_MAX_CPUS = 0x0f,
+ FW_CFG_KERNEL_ENTRY = 0x10,
+ FW_CFG_KERNEL_DATA = 0x11,
+ FW_CFG_INITRD_DATA = 0x12,
+ FW_CFG_CMDLINE_ADDR = 0x13,
+ FW_CFG_CMDLINE_SIZE = 0x14,
+ FW_CFG_CMDLINE_DATA = 0x15,
+ FW_CFG_SETUP_ADDR = 0x16,
+ FW_CFG_SETUP_SIZE = 0x17,
+ FW_CFG_SETUP_DATA = 0x18,
+ FW_CFG_FILE_DIR = 0x19,
+ FW_CFG_FILE_FIRST = 0x20,
+ FW_CFG_WRITE_CHANNEL = 0x4000,
+ FW_CFG_ARCH_LOCAL = 0x8000,
+ FW_CFG_INVALID = 0xffff,
+};
+
+#define FW_CFG_FILE_SLOTS 0x10
+#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH 56
+
+#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR (1 << 0)
+#define FW_CFG_DMA_READ (1 << 1)
+#define FW_CFG_DMA_SKIP (1 << 2)
+#define FW_CFG_DMA_SELECT (1 << 3)
+
+#define FW_CFG_DMA_ENABLED (1 << 1)
+
+struct fw_cfg_file {
+ __be32 size;
+ __be16 select;
+ __be16 reserved;
+ char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_cfg_files {
+ __be32 count;
+ struct fw_cfg_file files[];
+};
+
+struct fw_cfg_dma_access {
+ __be32 control;
+ __be32 length;
+ __be64 address;
+};
+
+/**
+ * Initialize QEMU fw_cfg interface
+ */
+void qemu_fwcfg_init(void);
+
+/**
+ * Get system cpu number
+ *
+ * @return: cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+#endif
printf("---|----------|-----------|------|-");
printf("------------------------------------------\n");
while (!end_of_hob(hdr)) {
- printf("%-2d | %08x | ", i, (unsigned int)hdr);
+ printf("%02x | %08x | ", i, (unsigned int)hdr);
type = hdr->type;
if (type == HOB_TYPE_UNUSED)
desc = "*Unused*";
desc = hob_type[type];
else
desc = "*Invalid*";
- printf("%-9s | %-4d | ", desc, hdr->len);
+ printf("%-9s | %04x | ", desc, hdr->len);
if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
type == HOB_TYPE_GUID_EXT) {
/*
* The second time we enter here, adjust the size of malloc()
* pool before relocation. Given gd->malloc_base was adjusted
- * after the call to board_init_f_mem() in arch/x86/cpu/start.S,
- * we should fix up gd->malloc_limit here.
+ * after the call to board_init_f_init_reserve() in arch/x86/
+ * cpu/start.S, we should fix up gd->malloc_limit here.
*/
gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
}
return (struct fsp_header *)fsp;
}
-void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
+void fsp_continue(u32 status, void *hob_list)
{
- u32 stack_len;
- u32 stack_base;
- u32 stack_top;
-
post_code(POST_MRC);
assert(status == 0);
- /* Get the migrated stack in normal memory */
- stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
- assert(stack_base != 0);
- stack_top = stack_base + stack_len - sizeof(u32);
-
- /*
- * Old stack base is stored at the very end of the stack top,
- * use it to calculate the migrated shared data base
- */
- shared_data = (struct shared_data *)(stack_base +
- ((u32)shared_data - *(u32 *)stack_top));
-
/* The boot loader main function entry */
fsp_init_done(hob_list);
}
void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
{
- struct shared_data shared_data;
+ struct fsp_config_data config_data;
fsp_init_f init;
struct fsp_init_params params;
struct fspinit_rtbuf rt_buf;
- struct vpd_region *fsp_vpd;
struct fsp_header *fsp_hdr;
struct fsp_init_params *params_ptr;
+#ifdef CONFIG_FSP_USE_UPD
+ struct vpd_region *fsp_vpd;
struct upd_region *fsp_upd;
+#endif
#ifdef CONFIG_DEBUG_UART
setup_early_uart();
panic("Invalid FSP header");
}
- fsp_upd = &shared_data.fsp_upd;
- memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
-
- /* Reserve a gap in stack top */
- rt_buf.common.stack_top = (u32 *)stack_top - 32;
- rt_buf.common.boot_mode = boot_mode;
- rt_buf.common.upd_data = fsp_upd;
+ config_data.common.fsp_hdr = fsp_hdr;
+ config_data.common.stack_top = stack_top;
+ config_data.common.boot_mode = boot_mode;
+#ifdef CONFIG_FSP_USE_UPD
/* Get VPD region start */
fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
fsp_hdr->cfg_region_off);
/* Verify the VPD data region is valid */
assert(fsp_vpd->sign == VPD_IMAGE_ID);
+ fsp_upd = &config_data.fsp_upd;
+
/* Copy default data from Flash */
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
sizeof(struct upd_region));
/* Verify the UPD data region is valid */
assert(fsp_upd->terminator == UPD_TERMINATOR);
+#endif
- /* Override any UPD setting if required */
- update_fsp_upd(fsp_upd);
+ memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
+
+ /* Override any configuration if required */
+ update_fsp_configs(&config_data, &rt_buf);
memset(¶ms, 0, sizeof(struct fsp_init_params));
params.nvs_buf = nvs_buf;
init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
params_ptr = ¶ms;
- shared_data.fsp_hdr = fsp_hdr;
- shared_data.stack_top = (u32 *)stack_top;
-
post_code(POST_PRE_MRC);
/* Load GDT for FSP */
setup_fsp_gdt();
/*
- * Use ASM code to ensure the register value in EAX & ECX
- * will be passed into BlContinuationFunc
+ * Use ASM code to ensure the register value in EAX & EDX
+ * will be passed into fsp_continue
*/
asm volatile (
"pushl %0;"
"call *%%eax;"
".global asm_continuation;"
"asm_continuation:;"
- "movl %%ebx, %%eax;" /* shared_data */
- "movl 4(%%esp), %%edx;" /* status */
- "movl 8(%%esp), %%ecx;" /* hob_list */
+ "movl 4(%%esp), %%eax;" /* status */
+ "movl 8(%%esp), %%edx;" /* hob_list */
"jmp fsp_continue;"
- : : "m"(params_ptr), "a"(init), "b"(&shared_data)
+ : : "m"(params_ptr), "a"(init)
);
/*
*
* Copyright (C) 2009 coresystems GmbH
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 or later of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifdef __GNUC__
+++ /dev/null
-if TARGET_DB_88F6820_GP
-
-config SYS_BOARD
- default "db-88f6820-gp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-88f6820-gp"
-
-endif
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-if TARGET_DB_MV784MP_GP
-
-config SYS_BOARD
- default "db-mv784mp-gp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-mv784mp-gp"
-
-endif
return pci_eth_init(bis);
}
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1545 PHY */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
{
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- u16 devadr = phy_addr[0];
- char *name = "neta0";
u16 reg;
- if (miiphy_set_current_dev(name))
- return;
-
/* Enable QSGMII AN */
/* Set page to 4 */
- miiphy_write(name, devadr, 0x16, 4);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
/* Enable AN */
- miiphy_write(name, devadr, 0x0, 0x1140);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
/* Set page to 0 */
- miiphy_write(name, devadr, 0x16, 0);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
/* Phy C_ANEG */
- miiphy_read(name, devadr, 0x4, ®);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
reg |= 0x1E0;
- miiphy_write(name, devadr, 0x4, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
/* Soft-Reset */
- miiphy_write(name, devadr, 22, 0x0000);
- miiphy_write(name, devadr, 0, 0x9140);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
/* Power up the phy */
- miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
- miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
- printf("88E1545 Initialized on %s\n", name);
+ printf("88E1545 Initialized\n");
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
--- /dev/null
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cmd_syno.o
--- /dev/null
+/*
+ * Commands to deal with Synology specifics.
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/io.h>
+#include "../drivers/ddr/marvell/axp/ddr3_init.h"
+
+#define ETH_ALEN 6
+#define ETHADDR_MAX 4
+#define SYNO_SN_TAG "SN="
+#define SYNO_CHKSUM_TAG "CHK="
+
+
+static int do_syno_populate(int argc, char * const argv[])
+{
+ unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+ unsigned int cs = CONFIG_SF_DEFAULT_CS;
+ unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
+ unsigned int mode = CONFIG_SF_DEFAULT_MODE;
+ struct spi_flash *flash;
+ unsigned long addr = 0x80000; /* XXX: parameterize this? */
+ loff_t offset = 0x007d0000;
+ loff_t len = 0x00010000;
+ char *buf, *bufp;
+ char var[128];
+ char val[128];
+ int ret, n;
+
+ /* XXX: arg parsing to select flash here? */
+
+ flash = spi_flash_probe(bus, cs, speed, mode);
+ if (!flash) {
+ printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
+ return 1;
+ }
+
+ buf = map_physmem(addr, len, MAP_WRBACK);
+ if (!buf) {
+ puts("Failed to map physical memory\n");
+ return 1;
+ }
+
+ ret = spi_flash_read(flash, offset, len, buf);
+ if (ret) {
+ puts("Failed to read from SPI flash\n");
+ goto out_unmap;
+ }
+
+ for (n = 0; n < ETHADDR_MAX; n++) {
+ char ethaddr[ETH_ALEN];
+ int i, sum = 0;
+ unsigned char csum = 0;
+
+ for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) {
+ sum += bufp[i];
+ csum += bufp[i];
+ ethaddr[i] = bufp[i];
+ }
+ if (!sum) /* MAC address empty */
+ continue;
+ if (csum != bufp[i]) { /* seventh byte is checksum value */
+ printf("Invalid MAC address for interface %d!\n", n);
+ continue;
+ }
+ if (n == 0)
+ sprintf(var, "ethaddr");
+ else
+ sprintf(var, "eth%daddr", n);
+ snprintf(val, sizeof(val) - 1,
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ ethaddr[0], ethaddr[1], ethaddr[2],
+ ethaddr[3], ethaddr[4], ethaddr[5]);
+ printf("parsed %s = %s\n", var, val);
+ setenv(var, val);
+ }
+ if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) {
+ char *snp, *csump;
+ int csum = 0;
+ unsigned long c;
+
+ snp = bufp = buf + 32 + strlen(SYNO_SN_TAG);
+ for (n = 0; bufp[n] && bufp[n] != ','; n++)
+ csum += bufp[n];
+ bufp[n] = '\0';
+
+ /* should come right after, but you never know */
+ bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG);
+ if (!bufp) {
+ printf("Serial number checksum tag missing!\n");
+ goto out_unmap;
+ }
+
+ csump = bufp += strlen(SYNO_CHKSUM_TAG);
+ for (n = 0; bufp[n] && bufp[n] != ','; n++)
+ ;
+ bufp[n] = '\0';
+
+ if (strict_strtoul(csump, 10, &c) || c != csum) {
+ puts("Invalid serial number found!\n");
+ ret = 1;
+ goto out_unmap;
+ }
+ printf("parsed SN = %s\n", snp);
+ setenv("SN", snp);
+ } else { /* old style format */
+ unsigned char csum = 0;
+
+ for (n = 0, bufp = buf + 32; n < 10; n++)
+ csum += bufp[n];
+
+ if (csum != bufp[n]) {
+ puts("Invalid serial number found!\n");
+ ret = 1;
+ goto out_unmap;
+ }
+ bufp[n] = '\0';
+ printf("parsed SN = %s\n", buf + 32);
+ setenv("SN", buf + 32);
+ }
+out_unmap:
+ unmap_physmem(buf, len);
+ return ret;
+}
+
+/* map bit position to function in POWER_MNG_CTRL_REG */
+static const char * const pwr_mng_bit_func[] = {
+ "audio",
+ "ge3", "ge2", "ge1", "ge0",
+ "pcie00", "pcie01", "pcie02", "pcie03",
+ "pcie10", "pcie11", "pcie12", "pcie13",
+ "bp",
+ "sata0_link", "sata0_core",
+ "lcd",
+ "sdio",
+ "usb0", "usb1", "usb2",
+ "idma", "xor0", "crypto",
+ NULL,
+ "tdm",
+ "pcie20", "pcie30",
+ "xor1",
+ "sata1_link", "sata1_core",
+ NULL,
+};
+
+static int do_syno_clk_gate(int argc, char * const argv[])
+{
+ u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+ const char *func, *state;
+ int i, val;
+
+ if (argc < 2)
+ return -1;
+
+ if (!strcmp(argv[1], "get")) {
+ puts("Clock Gating:\n");
+ for (i = 0; i < 32; i++) {
+ func = pwr_mng_bit_func[i];
+ if (!func)
+ continue;
+ state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF";
+ printf("%s:\t\t%s\n", func, state);
+ }
+ return 0;
+ }
+ if (argc < 4)
+ return -1;
+ if (!strcmp(argv[1], "set")) {
+ func = argv[2];
+ state = argv[3];
+ for (i = 0; i < 32; i++) {
+ if (!pwr_mng_bit_func[i])
+ continue;
+ if (!strcmp(func, pwr_mng_bit_func[i]))
+ break;
+ }
+ if (i == 32) {
+ printf("Error: name '%s' not known\n", func);
+ return -1;
+ }
+ val = state[0] != '0';
+ pwr_mng_ctrl_reg |= (val << i);
+ pwr_mng_ctrl_reg &= ~(!val << i);
+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+ }
+ return 0;
+}
+
+static int do_syno(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ const char *cmd;
+ int ret = 0;
+
+ if (argc < 2)
+ goto usage;
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (!strcmp(cmd, "populate_env"))
+ ret = do_syno_populate(argc, argv);
+ else if (!strcmp(cmd, "clk_gate"))
+ ret = do_syno_clk_gate(argc, argv);
+
+ if (ret != -1)
+ return ret;
+usage:
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ syno, 5, 1, do_syno,
+ "Synology specific commands",
+ "populate_env - Read vendor data from SPI flash into environment\n"
+ "clk_gate (get|set name 1|0) - Manage clock gating\n"
+);
--- /dev/null
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ds414.o
--- /dev/null
+/*
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
+
+#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30))
+#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15))
+#define DS414_GPP_OUT_VAL_HIGH (0)
+
+#define DS414_GPP_OUT_POL_LOW (0)
+#define DS414_GPP_OUT_POL_MID (0)
+#define DS414_GPP_OUT_POL_HIGH (0)
+
+#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30)))
+#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \
+ BIT(13) | BIT(14) | BIT(15)))
+#define DS414_GPP_OUT_ENA_HIGH (~0)
+
+static const u32 ds414_mpp_control[] = {
+ 0x11111111,
+ 0x22221111,
+ 0x22222222,
+ 0x00000000,
+ 0x11110000,
+ 0x00004000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+/* DDR3 static MC configuration */
+
+/* 1G_v1 (4x2Gbits) adapted by DS414 */
+MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
+ {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
+ {0x00001404, 0x30000800}, /*Dunit Control Low Register */
+ {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
+ {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
+
+ {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
+
+ {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
+ {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
+ {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
+ {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
+ {0x00001428, 0x000F8830}, /*Dunit Control High Register */
+ {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
+ {0x0000147C, 0x0000C671},
+
+ {0x000014a0, 0x00000001},
+ {0x000014a8, 0x00000100}, /*2:1 */
+ {0x00020220, 0x00000006},
+
+ {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
+ {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
+ {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
+
+ {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
+ {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
+
+ {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
+ {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
+
+ {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
+ {0x000150C, 0x00000000}, /* CS1 Size */
+ {0x0001514, 0x00000000}, /* CS2 Size */
+ {0x000151C, 0x00000000}, /* CS3 Size */
+
+ {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
+ {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
+
+ {0x000015D0, 0x00000650}, /*MR0 */
+ {0x000015D4, 0x00000044}, /*MR1 */
+ {0x000015D8, 0x00000010}, /*MR2 */
+ {0x000015DC, 0x00000000}, /*MR3 */
+
+ {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
+ {0x000015EC, 0xF800A225}, /*DDR PHY */
+
+ {0x0, 0x0}
+};
+
+MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+ {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
+ { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
+ { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
+ PEX_BUS_DISABLED },
+ 0x0040, serdes_change_m_phy
+ }
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+ return &ds414_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ return &ds414_serdes_cfg[0];
+}
+
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ return (0x1 << 1 | 1);
+}
+
+int board_early_init_f(void)
+{
+ int i;
+
+ /* Set GPP Out value */
+ reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
+ reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
+ reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
+
+ /* set GPP polarity */
+ reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
+ reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
+ reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
+
+ /* Set GPP Out Enable */
+ reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
+ reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
+ reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
+
+ for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
+ reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ u32 pwr_mng_ctrl_reg;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Gate unused clocks
+ *
+ * Note: Disabling unused PCIe lanes will hang PCI bus scan.
+ * Once this is resolved, bits 10-12, 26 and 27 can be
+ * unset here as well.
+ */
+ pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+ pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
+ pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */
+ pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */
+ pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
+ pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
+ pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */
+ pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */
+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: DS414\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
# AMCC 440SPe Reference Platform (yucca) board
#
-ifeq ($(ramsym),1)
-CONFIG_SYS_TEXT_BASE = 0x07FD0000
-else
-CONFIG_SYS_TEXT_BASE = 0xfffb0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
--- /dev/null
+if TARGET_THUNDERX_88XX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "thunderx"
+
+config SYS_VENDOR
+ string
+ default "cavium"
+
+config SYS_CONFIG_NAME
+ string
+ default "thunderx_88xx"
+
+config CMD_ATF
+ bool "Enable ATF query commands"
+ default y
+ help
+ Enable vendor specific ATF query commands such as SPI and SD/MMC
+ devices access, low level environment query, boot device layout
+ and node count.
+
+endif
--- /dev/null
+THUNDERX BOARD
+M: Sergey Temerkhanov <s.temerkhanov@gmail.com>
+S: Maintained
+F: board/cavium/thunderx/
+F: include/configs/thunderx_88xx.h
+F: configs/thunderx_88xx_defconfig
--- /dev/null
+#
+#
+# (C) Copyright 2014, Cavium Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := thunderx.o atf.o
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <asm/system.h>
+#include <cavium/thunderx_svc.h>
+#include <cavium/atf.h>
+#include <cavium/atf_part.h>
+
+#include <asm/psci.h>
+
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_MMC_READ;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_NOR_READ;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_get_pcount(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_PART_COUNT;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_GET_PART;
+ regs.regs[1] = (uintptr_t)part;
+ regs.regs[2] = index;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_erase_nor(uintptr_t offset, size_t size)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = THUNDERX_NOR_ERASE;
+ regs.regs[1] = offset;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = THUNDERX_NOR_WRITE;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = THUNDERX_MMC_WRITE;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_dram_size(unsigned int node)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_DRAM_SIZE;
+ regs.regs[1] = node;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_node_count(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_NODE_COUNT;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_env_count(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_ENV_COUNT;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_env_string(size_t index, char *str)
+{
+ uint64_t *buf = (void *)str;
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_ENV_STRING;
+ regs.regs[1] = index;
+
+ smc_call(®s);
+
+ if (regs.regs > 0) {
+ buf[0] = regs.regs[0];
+ buf[1] = regs.regs[1];
+ buf[2] = regs.regs[2];
+ buf[3] = regs.regs[3];
+
+ return 1;
+ } else {
+ return regs.regs[0];
+ }
+}
+
+#ifdef CONFIG_CMD_ATF
+
+static void atf_print_ver(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = ARM_STD_SVC_VERSION;
+
+ smc_call(®s);
+
+ printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+
+ regs.regs[0] = THUNDERX_SVC_VERSION;
+
+ smc_call(®s);
+
+ printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+}
+
+static void atf_print_uid(void)
+{
+}
+
+static void atf_print_part_table(void)
+{
+ size_t pcount;
+ unsigned long i;
+ int ret;
+ char *ptype;
+
+ struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE;
+
+ pcount = atf_get_pcount();
+
+ printf("Partition count: %lu\n\n", pcount);
+ printf("%10s %10s %10s\n", "Type", "Size", "Offset");
+
+ for (i = 0; i < pcount; i++) {
+ ret = atf_get_part(part, i);
+
+ if (ret < 0) {
+ printf("Uknown error while reading partition: %d\n",
+ ret);
+ return;
+ }
+
+ switch (part->type) {
+ case PARTITION_NBL1FW_REST:
+ ptype = "NBL1FW";
+ break;
+ case PARTITION_BL2_BL31:
+ ptype = "BL2_BL31";
+ break;
+ case PARTITION_UBOOT:
+ ptype = "BOOTLDR";
+ break;
+ case PARTITION_KERNEL:
+ ptype = "KERNEL";
+ break;
+ case PARTITION_DEVICE_TREE:
+ ptype = "DEVTREE";
+ break;
+ default:
+ ptype = "UNKNOWN";
+ }
+ printf("%10s %10d %10lx\n", ptype, part->size, part->offset);
+ }
+}
+
+int do_atf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ssize_t ret;
+ size_t size, offset;
+ void *buffer = 0;
+ unsigned int index, node;
+ char str[4 * sizeof(uint64_t)];
+
+ if ((argc == 5) && !strcmp(argv[1], "readmmc")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_read_mmc(offset, buffer, size);
+ } else if ((argc == 5) && !strcmp(argv[1], "readnor")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_read_nor(offset, buffer, size);
+ } else if ((argc == 5) && !strcmp(argv[1], "writemmc")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_write_mmc(offset, buffer, size);
+ } else if ((argc == 5) && !strcmp(argv[1], "writenor")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_write_nor(offset, buffer, size);
+ } else if ((argc == 2) && !strcmp(argv[1], "part")) {
+ atf_print_part_table();
+ } else if ((argc == 4) && !strcmp(argv[1], "erasenor")) {
+ offset = simple_strtoul(argv[2], NULL, 10);
+ size = simple_strtoul(argv[3], NULL, 10);
+
+ ret = atf_erase_nor(offset, size);
+ } else if ((argc == 2) && !strcmp(argv[1], "envcount")) {
+ ret = atf_env_count();
+ printf("Number of environment strings: %zd\n", ret);
+ } else if ((argc == 3) && !strcmp(argv[1], "envstring")) {
+ index = simple_strtoul(argv[2], NULL, 10);
+ ret = atf_env_string(index, str);
+ if (ret > 0)
+ printf("Environment string %d: %s\n", index, str);
+ else
+ printf("Return code: %zd\n", ret);
+ } else if ((argc == 3) && !strcmp(argv[1], "dramsize")) {
+ node = simple_strtoul(argv[2], NULL, 10);
+ ret = atf_dram_size(node);
+ printf("DRAM size: %zd Mbytes\n", ret >> 20);
+ } else if ((argc == 2) && !strcmp(argv[1], "nodes")) {
+ ret = atf_node_count();
+ printf("Nodes count: %zd\n", ret);
+ } else if ((argc == 2) && !strcmp(argv[1], "ver")) {
+ atf_print_ver();
+ } else if ((argc == 2) && !strcmp(argv[1], "uid")) {
+ atf_print_uid();
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ atf, 10, 1, do_atf,
+ "issue calls to ATF",
+ "\t readmmc addr offset size - read MMC card\n"
+ "\t readnor addr offset size - read NOR flash\n"
+ "\t writemmc addr offset size - write MMC card\n"
+ "\t writenor addr offset size - write NOR flash\n"
+ "\t erasenor offset size - erase NOR flash\n"
+ "\t nodes - number of nodes\n"
+ "\t dramsize node - size of DRAM attached to node\n"
+ "\t envcount - number of environment strings\n"
+ "\t envstring index - print the environment string\n"
+ "\t part - print MMC partition table\n"
+ "\t ver - print ATF call set versions\n"
+);
+
+#endif
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <linux/compiler.h>
+
+#include <cavium/atf.h>
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
+
+static const struct pl01x_serial_platdata serial0 = {
+ .base = CONFIG_SYS_SERIAL0,
+ .type = TYPE_PL011,
+ .clock = 0,
+ .skip_init = true,
+};
+
+U_BOOT_DEVICE(thunderx_serial0) = {
+ .name = "serial_pl01x",
+ .platdata = &serial0,
+};
+
+static const struct pl01x_serial_platdata serial1 = {
+ .base = CONFIG_SYS_SERIAL1,
+ .type = TYPE_PL011,
+ .clock = 0,
+ .skip_init = true,
+};
+
+U_BOOT_DEVICE(thunderx_serial1) = {
+ .name = "serial_pl01x",
+ .platdata = &serial1,
+};
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ ssize_t node_count = atf_node_count();
+ ssize_t dram_size;
+ int node;
+
+ printf("Initializing\nNodes in system: %zd\n", node_count);
+
+ gd->ram_size = 0;
+
+ for (node = 0; node < node_count; node++) {
+ dram_size = atf_dram_size(node);
+ printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
+ gd->ram_size += dram_size;
+ }
+
+ gd->ram_size -= MEM_BASE;
+
+ *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+ puts("DRAM size:");
+
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+ return rc;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ printf("DEBUG: PCI Init TODO *****\n");
+}
+#endif
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80100000
#include <common.h>
#include <command.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
/* Memory sub-system initialization code */
#include <config.h>
+#include <mach/au1x00.h>
#include <asm/regdef.h>
-#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define AU1500_SYS_ADDR 0xB1900000
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
sizeof(f_link));
break;
case 0x98: /* XAUI interface */
- sprintf(alias, "phy_xaui_slot1");
+ strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
- sprintf(alias, "phy_xaui_slot2");
+ strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x9e: /* XAUI interface */
case 0x9a:
case 0x93:
case 0x91:
- sprintf(alias, "phy_xaui_slot1");
+ strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x97: /* XAUI interface */
case 0xc3:
- sprintf(alias, "phy_xaui_slot2");
+ strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
default:
return 1;
/* read out the first block, get the config data information */
- n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
bus->read = hydra_mdio_read;
bus->write = hydra_mdio_write;
bus->reset = hydra_mdio_reset;
- sprintf(bus->name, fakebusname);
+ strcpy(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
bus->read = super_hydra_mdio_read;
bus->write = super_hydra_mdio_write;
bus->reset = super_hydra_mdio_reset;
- sprintf(bus->name, fakebusname);
+ strcpy(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
bus->read = ls1021a_mdio_read;
bus->write = ls1021a_mdio_write;
bus->reset = ls1021a_mdio_reset;
- sprintf(bus->name, fakebusname);
+ strcpy(bus->name, fakebusname);
lsmdio->realbus = miiphy_get_dev_by_name(realbusname);
bus->read = ls1043aqds_mdio_read;
bus->write = ls1043aqds_mdio_write;
bus->reset = ls1043aqds_mdio_reset;
- sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
bus->read = ls2080a_qds_mdio_read;
bus->write = ls2080a_qds_mdio_write;
bus->reset = ls2080a_qds_mdio_reset;
- sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xFF800000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xFFE00000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0
+++ /dev/null
-# Copyright 2010-2012 Freescale Semiconductor, Inc.
-# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xFF800000
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xFF800000
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008,2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
bus->read = t1024qds_mdio_read;
bus->write = t1024qds_mdio_write;
bus->reset = t1024qds_mdio_reset;
- sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
bus->read = t1040_qds_mdio_read;
bus->write = t1040_qds_mdio_write;
bus->reset = t1040_qds_mdio_reset;
- sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
bus->read = t208xqds_mdio_read;
bus->write = t208xqds_mdio_write;
bus->reset = t208xqds_mdio_reset;
- sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
bus->read = t4240qds_mdio_read;
bus->write = t4240qds_mdio_write;
bus->reset = t4240qds_mdio_reset;
- sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
bus->read = ihs_mdio_read;
bus->write = ihs_mdio_write;
bus->reset = ihs_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = info;
* (C) Copyright 2013
* Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* TODO: some more #ifdef's to avoid unneeded code for stage 1 / stage 2 */
ofs = src % blk_len;
if (ofs) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1,
tmp_buf);
if (!n)
goto failure;
}
cnt = size / blk_len;
if (cnt) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no, cnt,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no, cnt,
dst);
if (n != cnt)
goto failure;
block_no += cnt;
}
if (size) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1,
tmp_buf);
if (!n)
goto failure;
* (C) Copyright 2013
* Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONTROLCENTER_ID_H
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
*
* FSL DIU Framebuffer driver
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
return 1;
/* read out the first block, get the config data information */
- n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR
/*
* Copyright 2012 Calxeda, Inc.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
static enum core_card malta_core_card(void)
{
u32 corid, rev;
+ const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
- rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+ rev = __raw_readl(reg);
corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
switch (corid) {
#endif
#if defined(CONFIG_CMD_NET)
+
+static void reset_net_chip(int gpio)
+{
+ if (!gpio_request(gpio, "eth nrst")) {
+ gpio_direction_output(gpio, 1);
+ udelay(1);
+ gpio_set_value(gpio, 0);
+ udelay(40);
+ gpio_set_value(gpio, 1);
+ mdelay(10);
+ }
+}
+
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
- GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
&ctrl_base->gpmc_nadv_ale);
- /* Make GPIO 64 as output pin and send a magic pulse through it */
- if (!gpio_request(64, "")) {
- gpio_direction_output(64, 0);
- gpio_set_value(64, 1);
- udelay(1);
- gpio_set_value(64, 0);
- udelay(1);
- gpio_set_value(64, 1);
- }
+ reset_net_chip(64);
}
#else
static inline void setup_net_chip(void) {}
#if defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
- int rc = 0;
#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#else
+ return 0;
#endif
- return rc;
}
#endif
printf("can't get the IVM_Boardid\n");
return 1;
}
- sprintf((char *)buf, "%s", p);
+ strcpy((char *)buf, p);
setenv("boardid", (char *)buf);
printf("set boardid=%s\n", buf);
printf("can't get the IVM_HWKey\n");
return 1;
}
- sprintf((char *)buf, "%s", p);
+ strcpy((char *)buf, p);
setenv("hwkey", (char *)buf);
printf("set hwkey=%s\n", buf);
printf("Execute manually saveenv for persistent storage.\n");
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \
/* GPMC */ \
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
+ MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
+ MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\
MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\
MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\
MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \
MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \
MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \
/* MMC1 */ \
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /* MMC1_CMD */ \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /* MMC1_DAT0 */ \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /* MMC1_DAT1 */ \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /* MMC1_DAT2 */ \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /* MMC1_DAT3 */ \
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \
/* UART2 */ \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | DIS | M0)) /* UART2_CTS */ \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTU | DIS | M0)) /* UART2_RTS */ \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \
/* UART1 */ \
- MUX_VAL(CP(UART1_TX), (IDIS | PTU | DIS | M0)) /* UART1_TX */ \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTU | DIS | M0)) /* UART1_RTS */ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */ \
- MUX_VAL(CP(UART1_RX), (IEN | PTU | DIS | M0)) /* UART1_RX */ \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \
/* MCBSP4 */ \
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \
/* I2C2 */ \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /* I2C2_SCL */ \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /* I2C2_SDA */ \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \
/* I2C3 */ \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /* I2C3_SCL */ \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /* I2C3_SDA */ \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \
/* I2C4 */ \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \
MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \
/* SYS */ \
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \
/* JTAG */ \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | DIS | M0)) /* JTAG_EMU0 */ \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | DIS | M0)) /* JTAG_EMU1 */ \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \
/* ETK */ \
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \
MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \
MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \
MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \
- MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \
+ MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \
MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \
MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \
MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \
+++ /dev/null
-if TARGET_MAXBCM
-
-config SYS_BOARD
- default "maxbcm"
-
-config SYS_CONFIG_NAME
- default "maxbcm"
-
-endif
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
return 0;
}
-#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E6185 switch */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
{
- char *name = "neta0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* todo: fill this with the real setup / config code */
-
- printf("88E6185 Initialized on %s\n", name);
+ /*
+ * todo:
+ * Fill this with the real setup / config code.
+ * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+ * for details.
+ */
+ printf("88E6185 Initialized\n");
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
+++ /dev/null
-#
-# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# vct_xxx boards with MIPS 4Kc CPU core
-#
-
-ifndef CONFIG_SYS_TEXT_BASE
-CONFIG_SYS_TEXT_BASE = 0x87000000
-endif
*/
static inline void reg_write(u32 addr, u32 data)
{
- __raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+ void *reg = (void *)(addr + REG_GLOBAL_START_ADDR);
+ __raw_writel(data, reg);
}
static inline u32 reg_read(u32 addr)
{
- return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+ const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR);
+ return __raw_readl(reg);
}
#endif /* _VCT_H */
s=getenv ("serial#");
#ifdef CONFIG_PIP405
if (!s || strncmp (s, "PIP405", 6)) {
- sprintf(buf,"### No HW ID - assuming PIP405");
+ strcpy(buf,"### No HW ID - assuming PIP405");
}
#endif
#ifdef CONFIG_MIP405
if (!s || strncmp (s, "MIP405", 6)) {
- sprintf(buf,"### No HW ID - assuming MIP405");
+ strcpy(buf,"### No HW ID - assuming MIP405");
}
#endif
else {
}
buf[i++] = *s;
}
- sprintf(&buf[i]," SN ");
+ strcpy(&buf[i]," SN ");
i+=4;
for (; s < e; ++s) {
buf[i++] = *s;
ctfb.modeIdent);
return;
case 1:
- sprintf (buf, "%s",CONFIG_IDENT_STRING);
+ strcpy(buf, CONFIG_IDENT_STRING);
sprintf (info, " %s", &buf[1]);
return;
}
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_CARDHU_H_
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_DALMORE_H_
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# AMD development board AMD Alchemy Pb1x00, MIPS32 core
-#
-
-# ROM version
-#CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# SDRAM version
-CONFIG_SYS_TEXT_BASE = 0x83800000
/* Memory sub-system initialization code */
#include <config.h>
+#include <mach/au1x00.h>
#include <asm/regdef.h>
-#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define AU1500_SYS_ADDR 0xB1900000
#include <common.h>
#include <command.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
}
/* Request soft I2C gpios */
- sprintf(buf, "soft_i2c_scl");
+ strcpy(buf, "soft_i2c_scl");
gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
- sprintf(buf, "soft_i2c_sda");
+ strcpy(buf, "soft_i2c_sda");
gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
check_hw_revision();
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
sprintf(tmp, "%s_%s", factory_dat.asn,
factory_dat.comp_version);
else
- sprintf(tmp, "QMX7.E38_4.0");
+ strcpy(tmp, "QMX7.E38_4.0");
ret = setenv("boardid", tmp);
if (ret)
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
--- /dev/null
+CLEARFOG BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/soldrun/clearfog/
+F: include/configs/clearfog.h
+F: configs/clearfog_defconfig
--- /dev/null
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := clearfog.o
--- /dev/null
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+Generate the U-Boot image with these commands:
+
+$ make clearfog_defconfig
+$ make
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+Now all you need to do is copy this image on a SD card.
+For example with this command:
+
+$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
+
+Please use the correct device node for your setup instead
+of "/dev/sdX" here!
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG 0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-15t1-clearfog"
+ */
+#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
+#define BOARD_GPP_OUT_ENA_MID 0xffffffff
+
+#define BOARD_GPP_OUT_VAL_LOW 0x0
+#define BOARD_GPP_OUT_VAL_MID 0x0
+#define BOARD_GPP_POL_LOW 0x0
+#define BOARD_GPP_POL_MID 0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+ u8 chip;
+ u8 addr;
+ u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+ { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */
+ { 0x20, 6, 0xf9 },
+ { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */
+ { 0x20, 6, 0xb9 },
+ { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */
+ { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */
+};
+
+static struct serdes_map board_serdes_map[] = {
+ {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_LOW} }, /* temperature */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+ writel(0x10400011, MVEBU_MPP_BASE + 0x08);
+ writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
+ writel(0x44400002, MVEBU_MPP_BASE + 0x10);
+ writel(0x41144004, MVEBU_MPP_BASE + 0x14);
+ writel(0x40333333, MVEBU_MPP_BASE + 0x18);
+ writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int i;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Toggle GPIO41 to reset onboard switch and phy */
+ clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+ clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
+ mdelay(1);
+ setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+ mdelay(10);
+
+ /* Init I2C IO expanders */
+ for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+ i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: SolidRun ClearFog\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
--- /dev/null
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM sdio
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
See I2C0_ENABLE help text.
endif
+config R_I2C_ENABLE
+ bool "Enable the PRCM I2C/TWI controller"
+ default n
+ ---help---
+ Set this to y to enable the I2C controller which is part of the PRCM.
+
if MACH_SUN7I
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
clock_twi_onoff(4, 1);
#endif
#endif
+
+#ifdef CONFIG_R_I2C_ENABLE
+ clock_twi_onoff(5, 1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
+#endif
}
#ifdef CONFIG_SPL_BUILD
+++ /dev/null
-#
-# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffc00000
/*
* Copyright (c) 2014, Marcel Ziswiler
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_APALIS_T30_H_
/*
* Copyright (c) 2013-2014, Stefan Agner
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_
/* get production data */
if (read_eeprom(&header)) {
- sprintf(model, "211");
+ strcpy(model, "211");
} else {
sprintf(model, "%d", header.SystemId);
if (header.SystemId == 215) {
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
# the generated file from your Xilinx design flow.
#
-CONFIG_SYS_TEXT_BASE = 0x29000000
-
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
help
Extract a part of a multi-image.
+config CMD_POWEROFF
+ bool
+
endmenu
menu "Environment commands"
flag = 0; /* assume no special flags for now */
if (len > 0)
- strcpy(lastcommand, console_buffer);
+ strlcpy(lastcommand, console_buffer,
+ CONFIG_SYS_CBSIZE + 1);
else if (len == 0)
flag |= CMD_FLAG_REPEAT;
#ifdef CONFIG_BOOT_RETRY_TIME
"Perform RESET of the CPU",
""
);
+
+#ifdef CONFIG_CMD_POWEROFF
+U_BOOT_CMD(
+ poweroff, 1, 0, do_poweroff,
+ "Perform POWEROFF of the device",
+ ""
+);
+#endif
", Block Size: %ld\n",
info.start, info.size, info.blksz);
- if (dev_desc->block_read(dev, info.start, 1, (ulong *) addr) != 1) {
+ if (dev_desc->block_read(dev_desc, info.start, 1, (ulong *)addr) != 1) {
printf("** Read error on %d:%d\n", dev, part);
bootstage_error(BOOTSTAGE_ID_IDE_PART_READ);
return 1;
cnt /= info.blksz;
cnt -= 1;
- if (dev_desc->block_read(dev, info.start + 1, cnt,
- (ulong *)(addr + info.blksz)) != cnt) {
+ if (dev_desc->block_read(dev_desc, info.start + 1, cnt,
+ (ulong *)(addr + info.blksz)) != cnt) {
printf("** Read error on %d:%d\n", dev, part);
bootstage_error(BOOTSTAGE_ID_IDE_READ);
return 1;
(size_t)255));
} else {
tmp = getenv("bootdev");
- if (tmp)
- ptr = sprintf(build_buf, tmp);
- else
+ if (tmp) {
+ strcpy(build_buf, tmp);
+ ptr = strlen(tmp);
+ } else
printf("## VxWorks boot device not specified\n");
tmp = getenv("bootfile");
ptr += sprintf(build_buf + ptr, "tn=%s ", tmp);
tmp = getenv("othbootargs");
- if (tmp)
- ptr += sprintf(build_buf + ptr, tmp);
+ if (tmp) {
+ strcpy(build_buf + ptr, tmp);
+ ptr += strlen(tmp);
+ }
memcpy((void *)bootaddr, build_buf,
max(strlen(build_buf), (size_t)255));
*
* Inspired by cmd_ext_common.c, cmd_fat.c.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#ifdef CONFIG_ATAPI
static void atapi_inquiry(block_dev_desc_t *dev_desc);
-static ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer);
+static ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
#endif
if (strcmp(argv[1], "read") == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ block_dev_desc_t *dev_desc;
ulong n;
#ifdef CONFIG_SYS_64BIT_LBA
curr_device, blk, cnt);
#endif
- n = ide_dev_desc[curr_device].block_read(curr_device,
- blk, cnt,
- (ulong *)addr);
+ dev_desc = &ide_dev_desc[curr_device];
+ n = dev_desc->block_read(dev_desc, blk, cnt,
+ (ulong *)addr);
/* flush cache after read */
flush_cache(addr,
cnt * ide_dev_desc[curr_device].blksz);
printf("\nIDE write: device %d block # %ld, count %ld ... ",
curr_device, blk, cnt);
#endif
- n = ide_write(curr_device, blk, cnt, (ulong *) addr);
+ n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
+ (ulong *)addr);
printf("%ld blocks written: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
/* ------------------------------------------------------------------------- */
-ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char c;
unsigned char pwrsave = 0; /* power save */
/* ------------------------------------------------------------------------- */
-ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt, const void *buffer)
+ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char c;
#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char ccb[12]; /* Command descriptor block */
ulong cnt;
return CMD_RET_FAILURE;
}
/* Switch to the RPMB partition */
- original_part = mmc->part_num;
- if (mmc->part_num != MMC_PART_RPMB) {
- if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0)
- return CMD_RET_FAILURE;
- mmc->part_num = MMC_PART_RPMB;
- }
+ original_part = mmc->block_dev.part_num;
+ if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
+ return CMD_RET_FAILURE;
ret = cp->cmd(cmdtp, flag, argc, argv);
/* Return to original partition */
- if (mmc->part_num != original_part) {
- if (mmc_switch_part(curr_device, original_part) != 0)
- return CMD_RET_FAILURE;
- mmc->part_num = original_part;
- }
+ if (mmc_select_hwpart(curr_device, original_part) != 0)
+ return CMD_RET_FAILURE;
return ret;
}
#endif
printf("\nMMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
- n = mmc->block_dev.block_read(curr_device, blk, cnt, addr);
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_write(curr_device, blk, cnt, addr);
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk, cnt, addr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_erase(curr_device, blk, cnt);
+ n = mmc->block_dev.block_erase(&mmc->block_dev, blk, cnt);
printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("mmc%d is current device\n", curr_device);
else
printf("mmc%d(part %d) is current device\n",
- curr_device, mmc->part_num);
+ curr_device, mmc->block_dev.hwpart);
return CMD_RET_SUCCESS;
}
return 0;
}
- sprintf(p, "mtdparts=");
+ strcpy(p, "mtdparts=");
p += 9;
list_for_each(dentry, &devices) {
return 1;
}
- if (dev_desc->block_read(dev, offset + blk, cnt, addr) < 0) {
+ if (dev_desc->block_read(dev_desc, offset + blk, cnt, addr) < 0) {
printf("Error reading blocks\n");
return 1;
}
static int sata_curr_device = -1;
block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+static unsigned long sata_bread(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
+{
+ return sata_read(block_dev->dev, start, blkcnt, dst);
+}
+
+static unsigned long sata_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ return sata_write(block_dev->dev, start, blkcnt, buffer);
+}
+
int __sata_initialize(void)
{
int rc;
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].blksz = 512;
sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
- sata_dev_desc[i].block_read = sata_read;
- sata_dev_desc[i].block_write = sata_write;
+ sata_dev_desc[i].block_read = sata_bread;
+ sata_dev_desc[i].block_write = sata_bwrite;
rc = init_sata(i);
if (!rc) {
static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
unsigned long *blksz);
-static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer);
-static ulong scsi_write(int device, lbaint_t blknr,
+static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
+static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer);
ulong n;
printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
scsi_curr_dev, blk, cnt);
- n = scsi_read(scsi_curr_dev, blk, cnt, (ulong *)addr);
+ n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
+ blk, cnt, (ulong *)addr);
printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
return 0;
} else if (strcmp(argv[1], "write") == 0) {
printf("\nSCSI write: device %d block # %ld, "
"count %ld ... ",
scsi_curr_dev, blk, cnt);
- n = scsi_write(scsi_curr_dev, blk, cnt,
- (ulong *)addr);
+ n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
+ blk, cnt, (ulong *)addr);
printf("%ld blocks written: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
return 0;
#define SCSI_MAX_READ_BLK 0xFFFF
#define SCSI_LBA48_READ 0xFFFFFFF
-static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
+static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
/* Almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_WRITE_BLK 0xFFFF
-static ulong scsi_write(int device, lbaint_t blknr,
+static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
printf("\nUSB read: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
- n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt,
+ n = stor_dev->block_read(stor_dev, blk, cnt,
(ulong *)addr);
printf("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
printf("\nUSB write: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
- n = stor_dev->block_write(usb_stor_curr_dev, blk, cnt,
+ n = stor_dev->block_write(stor_dev, blk, cnt,
(ulong *)addr);
printf("%ld blocks write: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
static int ums_read_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf)
{
- block_dev_desc_t *block_dev = ums_dev->block_dev;
+ block_dev_desc_t *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
- return block_dev->block_read(dev_num, blkstart, blkcnt, buf);
+ return block_dev->block_read(block_dev, blkstart, blkcnt, buf);
}
static int ums_write_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, const void *buf)
{
- block_dev_desc_t *block_dev = ums_dev->block_dev;
+ block_dev_desc_t *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
- return block_dev->block_write(dev_num, blkstart, blkcnt, buf);
+ return block_dev->block_write(block_dev, blkstart, blkcnt, buf);
+}
+
+static struct ums *ums;
+static int ums_count;
+
+static void ums_fini(void)
+{
+ int i;
+
+ for (i = 0; i < ums_count; i++)
+ free((void *)ums[i].name);
+ free(ums);
+ ums = 0;
+ ums_count = 0;
}
-static struct ums ums_dev = {
- .read_sector = ums_read_sector,
- .write_sector = ums_write_sector,
- .name = "UMS disk",
-};
+#define UMS_NAME_LEN 16
-struct ums *ums_init(const char *devtype, const char *devnum)
+static int ums_init(const char *devtype, const char *devnums)
{
+ char *s, *t, *devnum, *name;
block_dev_desc_t *block_dev;
int ret;
+ struct ums *ums_new;
- ret = get_device(devtype, devnum, &block_dev);
- if (ret < 0)
- return NULL;
+ s = strdup(devnums);
+ if (!s)
+ return -1;
+
+ t = s;
+ ums_count = 0;
+
+ for (;;) {
+ devnum = strsep(&t, ",");
+ if (!devnum)
+ break;
+
+ ret = get_device(devtype, devnum, &block_dev);
+ if (ret < 0)
+ goto cleanup;
+
+ /* f_mass_storage.c assumes SECTOR_SIZE sectors */
+ if (block_dev->blksz != SECTOR_SIZE) {
+ ret = -1;
+ goto cleanup;
+ }
- /* f_mass_storage.c assumes SECTOR_SIZE sectors */
- if (block_dev->blksz != SECTOR_SIZE)
- return NULL;
+ ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
+ if (!ums_new) {
+ ret = -1;
+ goto cleanup;
+ }
+ ums = ums_new;
+
+ ums[ums_count].read_sector = ums_read_sector;
+ ums[ums_count].write_sector = ums_write_sector;
+ ums[ums_count].start_sector = 0;
+ ums[ums_count].num_sectors = block_dev->lba;
+ name = malloc(UMS_NAME_LEN);
+ if (!name) {
+ ret = -1;
+ goto cleanup;
+ }
+ snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
+ ums[ums_count].name = name;
+ ums[ums_count].block_dev = *block_dev;
+
+ printf("UMS: LUN %d, dev %d, hwpart %d, sector %#x, count %#x\n",
+ ums_count, ums[ums_count].block_dev.dev,
+ ums[ums_count].block_dev.hwpart,
+ ums[ums_count].start_sector,
+ ums[ums_count].num_sectors);
+
+ ums_count++;
+ }
+
+ if (!ums_count)
+ ret = -1;
+ else
+ ret = 0;
- ums_dev.block_dev = block_dev;
- ums_dev.start_sector = 0;
- ums_dev.num_sectors = block_dev->lba;
+cleanup:
+ free(s);
- printf("UMS: disk start sector: %#x, count: %#x\n",
- ums_dev.start_sector, ums_dev.num_sectors);
+ if (ret < 0)
+ ums_fini();
- return &ums_dev;
+ return ret;
}
int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
const char *usb_controller;
const char *devtype;
const char *devnum;
- struct ums *ums;
unsigned int controller_index;
int rc;
int cable_ready_timeout __maybe_unused;
devnum = argv[2];
}
- ums = ums_init(devtype, devnum);
- if (!ums)
+ rc = ums_init(devtype, devnum);
+ if (rc < 0)
return CMD_RET_FAILURE;
controller_index = (unsigned int)(simple_strtoul(
usb_controller, NULL, 0));
if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
error("Couldn't init USB controller.");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_ums_init;
}
- rc = fsg_init(ums);
+ rc = fsg_init(ums, ums_count);
if (rc) {
error("fsg_init failed");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_board;
}
rc = g_dnl_register("usb_dnl_ums");
if (rc) {
error("g_dnl_register failed");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_board;
}
/* Timeout unit: seconds */
while (!g_dnl_board_usb_cable_connected()) {
if (ctrlc()) {
puts("\rCTRL+C - Operation aborted.\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
if (!cable_ready_timeout) {
puts("\rUSB cable not detected.\n" \
"Command exit.\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
printf("\rAuto exit in: %.2d s.", cable_ready_timeout);
if (rc == -EPIPE)
printf("\rCTRL+C - Operation aborted\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
}
-exit:
+
+cleanup_register:
g_dnl_unregister();
+cleanup_board:
board_usb_cleanup(controller_index, USB_INIT_DEVICE);
- return CMD_RET_SUCCESS;
+cleanup_ums_init:
+ ums_fini();
+
+ return rc;
}
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
{
int i;
- for (i = 0; i < sizeof(env_flags_varaccess_mask); i++)
+ for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++)
if (env_flags_varaccess_mask[i] ==
(binflags & ENV_FLAGS_VARACCESS_BIN_MASK))
return (enum env_flags_varaccess)i;
return CONFIG_SYS_MMC_ENV_PART;
}
+static unsigned char env_mmc_orig_hwpart;
+
static int mmc_set_env_part(struct mmc *mmc)
{
uint part = mmc_get_env_part(mmc);
dev = 0;
#endif
- if (part != mmc->part_num) {
- ret = mmc_switch_part(dev, part);
- if (ret)
- puts("MMC partition switch failed\n");
- }
+ env_mmc_orig_hwpart = mmc->block_dev.hwpart;
+ ret = mmc_select_hwpart(dev, part);
+ if (ret)
+ puts("MMC partition switch failed\n");
return ret;
}
#ifdef CONFIG_SPL_BUILD
dev = 0;
#endif
- if (mmc_get_env_part(mmc) != mmc->part_num)
- mmc_switch_part(dev, mmc->part_num);
+ mmc_select_hwpart(dev, env_mmc_orig_hwpart);
#endif
}
blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
- n = mmc->block_dev.block_write(CONFIG_SYS_MMC_ENV_DEV, blk_start,
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
blk_cnt, (u_char *)buffer);
return (n == blk_cnt) ? 0 : -1;
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
- int dev = CONFIG_SYS_MMC_ENV_DEV;
-
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer);
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
+ (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
block_dev_desc_t *dev_desc = sparse->dev_desc;
int ret;
- ret = dev_desc->block_write(dev_desc->dev, offset, size, data);
+ ret = dev_desc->block_write(dev_desc, offset, size, data);
if (!ret)
return -EIO;
puts("Flashing Raw Image\n");
- blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt,
- buffer);
+ blks = dev_desc->block_write(dev_desc, info->start, blkcnt, buffer);
if (blks != blkcnt) {
error("failed writing to device %d\n", dev_desc->dev);
fastboot_fail(response_str, "failed writing to device");
printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
blks_start, blks_start + blks_size);
- blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size);
+ blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
if (blks != blks_size) {
error("failed erasing from device %d", dev_desc->dev);
fastboot_fail(response_str, "failed erasing from device");
void fdt_fixup_ethernet(void *fdt)
{
int node, i, j;
- char enet[16], *tmp, *end;
+ char *tmp, *end;
char mac[16];
const char *path;
unsigned char mac_addr[6];
+ int offset;
node = fdt_path_offset(fdt, "/aliases");
if (node < 0)
return;
- if (!getenv("ethaddr")) {
- if (getenv("usbethaddr")) {
- strcpy(mac, "usbethaddr");
- } else {
- debug("No ethernet MAC Address defined\n");
- return;
- }
- } else {
- strcpy(mac, "ethaddr");
- }
-
- i = 0;
- while ((tmp = getenv(mac)) != NULL) {
- sprintf(enet, "ethernet%d", i);
- path = fdt_getprop(fdt, node, enet, NULL);
- if (!path) {
- debug("No alias for %s\n", enet);
- sprintf(mac, "eth%daddr", ++i);
- continue;
- }
+ for (offset = fdt_first_property_offset(fdt, node);
+ offset > 0;
+ offset = fdt_next_property_offset(fdt, offset)) {
+ const char *name;
+ int len = strlen("ethernet");
+
+ path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
+ if (!strncmp(name, "ethernet", len)) {
+ i = trailing_strtol(name);
+ if (i != -1) {
+ if (i == 0)
+ strcpy(mac, "ethaddr");
+ else
+ sprintf(mac, "eth%daddr", i);
+ } else {
+ continue;
+ }
+ tmp = getenv(mac);
+ if (!tmp)
+ continue;
+
+ for (j = 0; j < 6; j++) {
+ mac_addr[j] = tmp ?
+ simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
- for (j = 0; j < 6; j++) {
- mac_addr[j] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
+ do_fixup_by_path(fdt, path, "mac-address",
+ &mac_addr, 6, 0);
+ do_fixup_by_path(fdt, path, "local-mac-address",
+ &mac_addr, 6, 1);
}
-
- do_fixup_by_path(fdt, path, "mac-address", &mac_addr, 6, 0);
- do_fixup_by_path(fdt, path, "local-mac-address",
- &mac_addr, 6, 1);
-
- sprintf(mac, "eth%daddr", ++i);
}
}
return 0;
}
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+ uint8_t *output, int *output_size)
+{
+ struct hash_algo *algo;
+ int ret;
+
+ ret = hash_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ if (output_size && *output_size < algo->digest_size) {
+ debug("Output buffer size %d too small (need %d bytes)",
+ *output_size, algo->digest_size);
+ return -ENOSPC;
+ }
+ if (output_size)
+ *output_size = algo->digest_size;
+ algo->hash_func_ws(data, len, output, algo->chunk_size);
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
/**
* store_result: Store the resulting sum to an address or variable
*
return 0;
}
-void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
+static void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
{
int i;
printf("%02x", output[i]);
}
-int hash_block(const char *algo_name, const void *data, unsigned int len,
- uint8_t *output, int *output_size)
-{
- struct hash_algo *algo;
- int ret;
-
- ret = hash_lookup_algo(algo_name, &algo);
- if (ret)
- return ret;
-
- if (output_size && *output_size < algo->digest_size) {
- debug("Output buffer size %d too small (need %d bytes)",
- *output_size, algo->digest_size);
- return -ENOSPC;
- }
- if (output_size)
- *output_size = algo->digest_size;
- algo->hash_func_ws(data, len, output, algo->chunk_size);
-
- return 0;
-}
-
int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
return 0;
}
#endif
+#endif
#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS)
- return gd->bd->bi_dram[0].size - tmp;
+ return gd->bd->bi_dram[0].size - (tmp - gd->bd->bi_dram[0].start);
#else
- return gd->bd->bi_memsize - tmp;
+ return gd->bd->bi_memsize - (tmp - gd->bd->bi_memstart);
#endif
}
if (initrd_high == ~0)
initrd_copy_to_ram = 0;
} else {
- /* not set, no restrictions to load high */
- initrd_high = ~0;
+ initrd_high = getenv_bootm_mapsize() + getenv_bootm_low();
}
#define _USE_MEMCPY
#endif
-/* Unfortunately x86 can't compile this code as gd cannot be assigned */
-#ifndef CONFIG_X86
+/* Unfortunately x86 or ARM can't compile this code as gd cannot be assigned */
+#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
__weak void arch_setup_gd(struct global_data *gd_ptr)
{
gd = gd_ptr;
}
-#endif /* !CONFIG_X86 */
+#endif /* !CONFIG_X86 && !CONFIG_ARM */
-ulong board_init_f_mem(ulong top)
+/*
+ * Allocate reserved space for use as 'globals' from 'top' address and
+ * return 'bottom' address of allocated space
+ *
+ * Notes:
+ *
+ * Actual reservation cannot be done from within this function as
+ * it requires altering the C stack pointer, so this will be done by
+ * the caller upon return from this function.
+ *
+ * IMPORTANT:
+ *
+ * Alignment constraints may differ for each 'chunk' allocated. For now:
+ *
+ * - GD is aligned down on a 16-byte boundary
+ *
+ * - the early malloc arena is not aligned, therefore it follows the stack
+ * alignment constraint of the architecture for which we are bulding.
+ *
+ * - GD is allocated last, so that the return value of this functions is
+ * both the bottom of the reserved area and the address of GD, should
+ * the calling context need it.
+ */
+
+ulong board_init_f_alloc_reserve(ulong top)
+{
+ /* Reserve early malloc arena */
+#if defined(CONFIG_SYS_MALLOC_F)
+ top -= CONFIG_SYS_MALLOC_F_LEN;
+#endif
+ /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */
+ top = rounddown(top-sizeof(struct global_data), 16);
+
+ return top;
+}
+
+/*
+ * Initialize reserved space (which has been safely allocated on the C
+ * stack from the C runtime environment handling code).
+ *
+ * Notes:
+ *
+ * Actual reservation was done by the caller; the locations from base
+ * to base+size-1 (where 'size' is the value returned by the allocation
+ * function above) can be accessed freely without risk of corrupting the
+ * C runtime environment.
+ *
+ * IMPORTANT:
+ *
+ * Upon return from the allocation function above, on some architectures
+ * the caller will set gd to the lowest reserved location. Therefore, in
+ * this initialization function, the global data MUST be placed at base.
+ *
+ * ALSO IMPORTANT:
+ *
+ * On some architectures, gd will already be good when entering this
+ * function. On others, it will only be good once arch_setup_gd() returns.
+ * Therefore, global data accesses must be done:
+ *
+ * - through gd_ptr if before the call to arch_setup_gd();
+ *
+ * - through gd once arch_setup_gd() has been called.
+ *
+ * Do not use 'gd->' until arch_setup_gd() has been called!
+ *
+ * IMPORTANT TOO:
+ *
+ * Initialization for each "chunk" (GD, early malloc arena...) ends with
+ * an incrementation line of the form 'base += <some size>'. The last of
+ * these incrementations seems useless, as base will not be used any
+ * more after this incrementation; but if/when a new "chunk" is appended,
+ * this increment will be essential as it will give base right value for
+ * this new chunk (which will have to end with its own incrementation
+ * statement). Besides, the compiler's optimizer will silently detect
+ * and remove the last base incrementation, therefore leaving that last
+ * (seemingly useless) incrementation causes no code increase.
+ */
+
+void board_init_f_init_reserve(ulong base)
{
struct global_data *gd_ptr;
#ifndef _USE_MEMCPY
int *ptr;
#endif
- /* Leave space for the stack we are running with now */
- top -= 0x40;
+ /*
+ * clear GD entirely and set it up.
+ * Use gd_ptr, as gd may not be properly set yet.
+ */
- top -= sizeof(struct global_data);
- top = ALIGN(top, 16);
- gd_ptr = (struct global_data *)top;
+ gd_ptr = (struct global_data *)base;
+ /* zero the area */
#ifdef _USE_MEMCPY
memset(gd_ptr, '\0', sizeof(*gd));
#else
for (ptr = (int *)gd_ptr; ptr < (int *)(gd_ptr + 1); )
*ptr++ = 0;
#endif
+ /* set GD unless architecture did it already */
+#if !defined(CONFIG_ARM)
arch_setup_gd(gd_ptr);
+#endif
+ /* next alloc will be higher by one GD plus 16-byte alignment */
+ base += roundup(sizeof(struct global_data), 16);
+
+ /*
+ * record early malloc arena start.
+ * Use gd as it is now properly set for all architectures.
+ */
#if defined(CONFIG_SYS_MALLOC_F)
- top -= CONFIG_SYS_MALLOC_F_LEN;
- gd->malloc_base = top;
+ /* go down one 'early malloc arena' */
+ gd->malloc_base = base;
+ /* next alloc will be higher by one 'early malloc arena' size */
+ base += CONFIG_SYS_MALLOC_F_LEN;
#endif
-
- return top;
}
* more stack space for things like the MMC sub-system.
*
* This function calculates the stack position, copies the global_data into
- * place and returns the new stack position. The caller is responsible for
- * setting up the sp register.
+ * place, sets the new gd (except for ARM, for which setting GD within a C
+ * function may not always work) and returns the new stack position. The
+ * caller is responsible for setting up the sp register and, in the case
+ * of ARM, setting up gd.
+ *
+ * All of this is done using the same layout and alignments as done in
+ * board_init_f_init_reserve() / board_init_f_alloc_reserve().
*
* @return new stack location, or 0 to use the same stack
*/
{
#ifdef CONFIG_SPL_STACK_R
gd_t *new_gd;
- ulong ptr;
-
- /* Get stack position: use 8-byte alignment for ABI compliance */
- ptr = CONFIG_SPL_STACK_R_ADDR - sizeof(gd_t);
- ptr &= ~7;
- new_gd = (gd_t *)ptr;
- memcpy(new_gd, (void *)gd, sizeof(gd_t));
- gd = new_gd;
+ ulong ptr = CONFIG_SPL_STACK_R_ADDR;
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
gd->malloc_ptr = 0;
}
#endif
-
+ /* Get stack position: use 8-byte alignment for ABI compliance */
+ ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
+ new_gd = (gd_t *)ptr;
+ memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if !defined(CONFIG_ARM)
+ gd = new_gd;
+#endif
return ptr;
#else
return 0;
unsigned long count;
u32 image_size_sectors;
struct image_header *header;
- int dev_num = mmc->block_dev.dev;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
sizeof(struct image_header));
/* read image header to find the image size & load address */
- count = mmc->block_dev.block_read(dev_num, sector, 1, header);
+ count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
debug("read sector %lx, count=%lu\n", sector, count);
if (count == 0)
goto end;
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
- count = mmc->block_dev.block_read(dev_num, sector, image_size_sectors,
+ count = mmc->block_dev.block_read(&mmc->block_dev, sector,
+ image_size_sectors,
(void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
{
unsigned long count;
- count = mmc->block_dev.block_read(
- mmc->block_dev.dev,
+ count = mmc->block_dev.block_read(&mmc->block_dev,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *) CONFIG_SYS_SPL_ARGS_ADDR);
}
epno = dev->config.if_desc[ifno].no_of_ep;
if_desc = &dev->config.if_desc[ifno];
- if (epno > USB_MAXENDPOINTS) {
+ if (epno >= USB_MAXENDPOINTS) {
printf("Interface %d has too many endpoints!\n",
if_desc->desc.bInterfaceNumber);
return -EINVAL;
block_dev_desc_t *dev_desc);
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss);
-unsigned long usb_stor_read(int device, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer);
-unsigned long usb_stor_write(int device, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer);
+static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
+static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer);
void uhci_show_temp_int_td(void);
#ifdef CONFIG_PARTITIONS
}
#endif /* CONFIG_USB_BIN_FIXUP */
-unsigned long usb_stor_read(int device, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer)
+static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
return blkcnt;
}
-unsigned long usb_stor_write(int device, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer)
+static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
CONFIG_M68K=y
CONFIG_TARGET_M5208EVBE=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M52277EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000"
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_M68K=y
CONFIG_TARGET_M52277EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000"
+CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_M68K=y
CONFIG_TARGET_M5235EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000"
+CONFIG_SYS_TEXT_BASE=0xFFC00000
+CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5235EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000"
+CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M5249EVB=y
+CONFIG_SYS_TEXT_BASE=0xffe00000
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_M68K=y
CONFIG_TARGET_M5253DEMO=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5253EVBE=y
+CONFIG_SYS_TEXT_BASE=0xFFE00000
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_M68K=y
CONFIG_TARGET_M5272C3=y
+CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M5275EVB=y
+CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M5282EVB=y
+CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M53017EVB=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5329EVB=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5329EVB=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5373EVB=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000"
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000"
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000"
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000"
+CONFIG_SYS_TEXT_BASE=0x47e00000
+CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666"
+CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333"
+CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666"
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333"
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333"
+CONFIG_SYS_TEXT_BASE=0x4FE00000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
+CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_M68K=y
CONFIG_TARGET_AMCORE=y
+CONFIG_SYS_TEXT_BASE=0xffc00000
CONFIG_SYS_PROMPT="amcore $ "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_CLEARFOG=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_M68K=y
CONFIG_TARGET_COBRA5272=y
+CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_SYS_PROMPT="COBRA > "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6820_GP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DS414=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
CONFIG_M68K=y
CONFIG_TARGET_EB_CPU5282=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400"
+CONFIG_SYS_TEXT_BASE=0xFF000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_SYS_PROMPT="\nEB+CPU5282> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_EB_CPU5282=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418"
+CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MAXBCM=y
-CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_MICROBLAZE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_SYS_TEXT_BASE=0x29000000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_R_I2C_ENABLE=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USE_TINY_PRINTF=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_THUNDERX_88XX=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
+CONFIG_SYS_EXTRA_OPTIONS="ARM64"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ThunderX_88XX> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_DM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_BASE=0x87e024000000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_REGEX=y
CONFIG_ARM=y
CONFIG_TARGET_WORK_92105=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
goto cleanup;
}
+#ifdef HAVE_BLOCK_DEVICE
+ /*
+ * Updates the partition table for the specified hw partition.
+ * Does not need to be done for hwpart 0 since it is default and
+ * already loaded.
+ */
+ if(hwpart != 0)
+ init_part(*dev_desc);
+#endif
+
cleanup:
free(dup_str);
return dev;
for (i=0; i<limit; i++)
{
- ulong res = dev_desc->block_read(dev_desc->dev, i, 1,
- (ulong *)block_buffer);
+ ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer;
for (i = 0; i < limit; i++)
{
- ulong res = dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)block_buffer);
+ ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct bootcode_block *boot = (struct bootcode_block *)block_buffer;
while (block != 0xFFFFFFFF)
{
- ulong res = dev_desc->block_read(dev_desc->dev, block, 1,
+ ulong res = dev_desc->block_read(dev_desc, block, 1,
(ulong *)block_buffer);
if (res == 1)
{
PRINTF("Trying to load block #0x%X\n", block);
- res = dev_desc->block_read(dev_desc->dev, block, 1,
- (ulong *)block_buffer);
+ res = dev_desc->block_read(dev_desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
/* Convert char[4] in little endian format to the host format integer
*/
-static inline int le32_to_int(unsigned char *le32)
+static inline unsigned int le32_to_int(unsigned char *le32)
{
return ((le32[3] << 24) +
(le32[2] << 16) +
return p->boot_ind == 0x80;
}
-static void print_one_part(dos_partition_t *p, int ext_part_sector,
+static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
int part_num, unsigned int disksig)
{
- int lba_start = ext_part_sector + le32_to_int (p->start4);
- int lba_size = le32_to_int (p->size4);
+ lbaint_t lba_start = ext_part_sector + le32_to_int (p->start4);
+ lbaint_t lba_size = le32_to_int (p->size4);
- printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
+ printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength
+ "u\t%08x-%02x\t%02x%s%s\n",
part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
(is_bootable(p) ? " Boot" : ""));
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1)
+ if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)buffer) != 1)
return -1;
if (test_block_type(buffer) != DOS_MBR)
/* Print a partition that is relative to its Extended partition table
*/
static void print_partition_extended(block_dev_desc_t *dev_desc,
- int ext_part_sector, int relative,
+ lbaint_t ext_part_sector,
+ lbaint_t relative,
int part_num, unsigned int disksig)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
int i;
- if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
+ (ulong *)buffer) != 1) {
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return;
}
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
print_partition_extended(dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
/* Print a partition that is relative to its Extended partition table
*/
-static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector,
- int relative, int part_num,
+static int get_partition_info_extended (block_dev_desc_t *dev_desc,
+ lbaint_t ext_part_sector,
+ lbaint_t relative, int part_num,
int which_part, disk_partition_t *info,
unsigned int disksig)
{
int i;
int dos_type;
- if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
+ (ulong *)buffer) != 1) {
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return -1;
}
break;
}
/* sprintf(info->type, "%d, pt->sys_ind); */
- sprintf ((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(pt);
#ifdef CONFIG_PARTITION_UUIDS
sprintf(info->uuid, "%08x-%02x", disksig, part_num);
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
return get_partition_info_extended (dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
info->size = dev_desc->lba;
info->blksz = DOS_PART_DEFAULT_SECTOR;
info->bootable = 0;
- sprintf ((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
#ifdef CONFIG_PARTITION_UUIDS
info->uuid[0] = 0;
#endif
sprintf((char *)info->name, "%s",
print_efiname(&gpt_pte[part - 1]));
- sprintf((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(&gpt_pte[part - 1]);
#ifdef CONFIG_PARTITION_UUIDS
uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
/* Read legacy MBR from block 0 and validate it */
- if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)legacymbr) != 1)
+ if ((dev_desc->block_read(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
return -1;
}
p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
/* Write MBR sector to the MMC device */
- if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) {
+ if (dev_desc->block_write(dev_desc, 0, 1, p_mbr) != 1) {
printf("** Can't write to device %d **\n",
dev_desc->dev);
return -1;
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
/* Write the First GPT to the block right after the Legacy MBR */
- if (dev_desc->block_write(dev_desc->dev, 1, 1, gpt_h) != 1)
+ if (dev_desc->block_write(dev_desc, 1, 1, gpt_h) != 1)
goto err;
- if (dev_desc->block_write(dev_desc->dev, 2, pte_blk_cnt, gpt_e)
+ if (dev_desc->block_write(dev_desc, 2, pte_blk_cnt, gpt_e)
!= pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
- if (dev_desc->block_write(dev_desc->dev,
+ if (dev_desc->block_write(dev_desc,
(lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ 1,
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
- if (dev_desc->block_write(dev_desc->dev,
+ if (dev_desc->block_write(dev_desc,
(lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
gpt_h) != 1)
goto err;
/* write MBR */
lba = 0; /* MBR is always at 0 */
cnt = 1; /* MBR (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, buf) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "MBR", cnt, lba);
return 1;
/* write Primary GPT */
lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
cnt = 1; /* GPT Header (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Primary GPT Header", cnt, lba);
return 1;
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Primary GPT Entries", cnt, lba);
return 1;
/* write Backup GPT */
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Backup GPT Entries", cnt, lba);
return 1;
lba = le64_to_cpu(gpt_h->my_lba);
cnt = 1; /* GPT Header (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Backup GPT Header", cnt, lba);
return 1;
}
/* Read GPT Header from device */
- if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head)
- != 1) {
+ if (dev_desc->block_read(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
printf("*** ERROR: Can't read GPT header ***\n");
return 0;
}
gpt_header * pgpt_head)
{
size_t count = 0, blk_cnt;
+ lbaint_t blk;
gpt_entry *pte = NULL;
if (!dev_desc || !pgpt_head) {
}
/* Read GPT Entries from device */
+ blk = le64_to_cpu(pgpt_head->partition_entry_lba);
blk_cnt = BLOCK_CNT(count, dev_desc);
- if (dev_desc->block_read (dev_desc->dev,
- (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba),
- (lbaint_t) (blk_cnt), pte)
- != blk_cnt) {
-
+ if (dev_desc->block_read(dev_desc, blk, (lbaint_t)blk_cnt, pte)
+ != blk_cnt) {
printf("*** ERROR: Can't read GPT Entries ***\n");
free(pte);
return NULL;
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
- if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1)
- return (-1);
+ if (dev_desc->block_read(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+ return -1;
if(ppr->desctype!=0x01) {
if(verb)
printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
PRINTF(" Lastsect:%08lx\n",lastsect);
for(i=blkaddr;i<lastsect;i++) {
PRINTF("Reading block %d\n", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1)
- return (-1);
+ if (dev_desc->block_read(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+ return -1;
if(ppr->desctype==0x00)
break; /* boot entry found */
if(ppr->desctype==0xff) {
}
bootaddr=le32_to_int(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1) {
+ if (dev_desc->block_read(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
bootaddr,dev_desc->dev, part_num);
/* the validation entry seems to be ok, now search the "partition" */
entry_num=0;
offset=0x20;
- sprintf ((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_SATA:
n = 1; /* assuming at least one partition */
for (i=1; i<=n; ++i) {
- if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)mpart) != 1) ||
+ if ((dev_desc->block_read(dev_desc, i, 1,
+ (ulong *)mpart) != 1) ||
(mpart->signature != MAC_PARTITION_MAGIC) ) {
return (-1);
}
char c;
printf ("%4ld: ", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)mpart) != 1) {
+ if (dev_desc->block_read(dev_desc, i, 1, (ulong *)mpart) != 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
dev_desc->dev, i);
return;
*/
static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p)
{
- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)ddb_p) != 1) {
+ if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
printf ("** Can't read Driver Desriptor Block **\n");
return (-1);
}
* partition 1 first since this is the only way to
* know how many partitions we have.
*/
- if (dev_desc->block_read (dev_desc->dev, n, 1, (ulong *)pdb_p) != 1) {
+ if (dev_desc->block_read(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
printf ("** Can't read Partition Map on %d:%d **\n",
dev_desc->dev, n);
return (-1);
6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
aarch32 specific codes.
+7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores
+ supporting 64k pages it allows usage of full 48+ virtual/physical addresses
+
+ Enabling this option requires the following ones to be defined:
+ - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the
+ system memory map (start, length, attributes)
+ - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP
+ - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries
+ - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries
+ for the largest CONFIG_SYS_MEM_MAP entry
+ - CONFIG_COREID_MASK - the mask value used to get the core from the
+ MPIDR_EL1 register
+ - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level
+ page tables
+ - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block
+ entry from L2 page tables
+ - CONFIG_SYS_PGTABLE_SIZE - total size of the page table
+ - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3}
+
+
+
+
Contributor
===========
- Tom Rini <trini@ti.com>
- Scott Wood <scottwood@freescale.com>
- York Sun <yorksun@freescale.com>
- Simon Glass <sjg@chromium.org>
- Sharma Bhupesh <bhupesh.sharma@freescale.com>
- Rob Herring <robherring2@gmail.com>
+ Tom Rini <trini@ti.com>
+ Scott Wood <scottwood@freescale.com>
+ York Sun <yorksun@freescale.com>
+ Simon Glass <sjg@chromium.org>
+ Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ Rob Herring <robherring2@gmail.com>
+ Sergey Temerkhanov <s.temerkhanov@gmail.com>
If you want to check both consoles, use '-serial stdio'.
Multicore is also supported by QEMU via '-smp n' where n is the number of cores
-to instantiate. Currently the default U-Boot built for QEMU supports 2 cores.
-In order to support more cores, you need add additional cpu nodes in the device
-tree and change CONFIG_MAX_CPUS accordingly.
+to instantiate. Note, the maximum supported CPU number in QEMU is 255.
+
+The fw_cfg interface in QEMU also provides information about kernel data, initrd,
+command-line arguments and more. U-Boot supports directly accessing these informtion
+from fw_cfg interface, this saves the time of loading them from hard disk or
+network again, through emulated devices. To use it , simply providing them in
+QEMU command line:
+
+$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
+ -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
+
+Note: -initrd and -smp are both optional
+
+Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+
+ => qfw
+qfw - QEMU firmware interface
+
+Usage:
+qfw <command>
+ - list : print firmware(s) currently loaded
+ - cpus : print online cpu number
+ - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
+
+=> qfw load
+loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
+
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
+can be used to boot the kernel:
+
+=> zboot 02000000 - 04000000 1b1ab50
CPU Microcode
-------------
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ddr/marvell/a38x/
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ddr/marvell/axp/
+obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
+obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
obj-$(CONFIG_SATA_DWC) += sata_dwc.o
+obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_IDE_SIL680) += sil680.o
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/soc.h>
-#elif defined(CONFIG_ARMADA_XP)
+#elif defined(CONFIG_ARCH_MVEBU)
#include <linux/mbus.h>
#endif
* Initialize SATA memory windows for Armada XP
*/
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_ARCH_MVEBU
static void mvsata_ide_conf_mbus_windows(void)
{
const struct mbus_dram_target_info *dram;
int ret = MVSATA_STATUS_TIMEOUT;
int status;
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_ARCH_MVEBU
mvsata_ide_conf_mbus_windows();
#endif
return NULL;
}
-static unsigned long host_block_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer)
+static unsigned long host_block_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
{
+ int dev = block_dev->dev;
struct host_block_dev *host_dev = find_host_device(dev);
if (!host_dev)
return -1;
}
-static unsigned long host_block_write(int dev, unsigned long start,
- lbaint_t blkcnt, const void *buffer)
+static unsigned long host_block_write(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ const void *buffer)
{
+ int dev = block_dev->dev;
struct host_block_dev *host_dev = find_host_device(dev);
if (os_lseek(host_dev->fd,
start * host_dev->blk_dev.blksz,
if (id[162] & 1)
printf("supports DRM functions and may "
"not be fully accessable.\n");
- sprintf(revbuf, "%s", "CFA");
+ strcpy(revbuf, "CFA");
} else {
if (ata_id_has_tpm(id))
printf("supports DRM functions and may "
ncq_desc[0] = '\0';
if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
- sprintf(ncq_desc, "%s", "NCQ (not used)");
+ strcpy(ncq_desc, "NCQ (not used)");
if (ap.flags & ATA_FLAG_NCQ)
ata_dev->flags |= ATA_DFLAG_NCQ;
--- /dev/null
+/*
+ * Copyright (C) Excito Elektronik i Skåne AB, 2010.
+ * Author: Tor Krill <tor@excito.com>
+ *
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This driver supports the SATA controller of some Mavell SoC's.
+ * Here a (most likely incomplete) list of the supported SoC's:
+ * - Kirkwood
+ * - Armada 370
+ * - Armada XP
+ *
+ * This driver implementation is an alternative to the already available
+ * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
+ * But this driver only supports PIO mode and as this new driver also
+ * supports transfer via DMA, its much faster.
+ *
+ * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
+ * by this driver. As they have an AHCI compatible SATA controller
+ * integrated.
+ */
+
+/*
+ * TODO:
+ * Better error recovery
+ * No support for using PRDs (Thus max 64KB transfers)
+ * No NCQ support
+ * No port multiplier support
+ */
+
+#include <common.h>
+#include <fis.h>
+#include <libata.h>
+#include <malloc.h>
+#include <sata.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <linux/mbus.h>
+
+#if defined(CONFIG_KIRKWOOD)
+#include <asm/arch/kirkwood.h>
+#define SATAHC_BASE KW_SATA_BASE
+#else
+#include <asm/arch/soc.h>
+#define SATAHC_BASE MVEBU_AXP_SATA_BASE
+#endif
+
+#define SATA0_BASE (SATAHC_BASE + 0x2000)
+#define SATA1_BASE (SATAHC_BASE + 0x4000)
+
+/* EDMA registers */
+#define EDMA_CFG 0x000
+#define EDMA_CFG_NCQ (1 << 5)
+#define EDMA_CFG_EQUE (1 << 9)
+#define EDMA_TIMER 0x004
+#define EDMA_IECR 0x008
+#define EDMA_IEMR 0x00c
+#define EDMA_RQBA_HI 0x010
+#define EDMA_RQIPR 0x014
+#define EDMA_RQIPR_IPMASK (0x1f << 5)
+#define EDMA_RQIPR_IPSHIFT 5
+#define EDMA_RQOPR 0x018
+#define EDMA_RQOPR_OPMASK (0x1f << 5)
+#define EDMA_RQOPR_OPSHIFT 5
+#define EDMA_RSBA_HI 0x01c
+#define EDMA_RSIPR 0x020
+#define EDMA_RSIPR_IPMASK (0x1f << 3)
+#define EDMA_RSIPR_IPSHIFT 3
+#define EDMA_RSOPR 0x024
+#define EDMA_RSOPR_OPMASK (0x1f << 3)
+#define EDMA_RSOPR_OPSHIFT 3
+#define EDMA_CMD 0x028
+#define EDMA_CMD_ENEDMA (0x01 << 0)
+#define EDMA_CMD_DISEDMA (0x01 << 1)
+#define EDMA_CMD_ATARST (0x01 << 2)
+#define EDMA_CMD_FREEZE (0x01 << 4)
+#define EDMA_TEST_CTL 0x02c
+#define EDMA_STATUS 0x030
+#define EDMA_IORTO 0x034
+#define EDMA_CDTR 0x040
+#define EDMA_HLTCND 0x060
+#define EDMA_NTSR 0x094
+
+/* Basic DMA registers */
+#define BDMA_CMD 0x224
+#define BDMA_STATUS 0x228
+#define BDMA_DTLB 0x22c
+#define BDMA_DTHB 0x230
+#define BDMA_DRL 0x234
+#define BDMA_DRH 0x238
+
+/* SATA Interface registers */
+#define SIR_ICFG 0x050
+#define SIR_CFG_GEN2EN (0x1 << 7)
+#define SIR_PLL_CFG 0x054
+#define SIR_SSTATUS 0x300
+#define SSTATUS_DET_MASK (0x0f << 0)
+#define SIR_SERROR 0x304
+#define SIR_SCONTROL 0x308
+#define SIR_SCONTROL_DETEN (0x01 << 0)
+#define SIR_LTMODE 0x30c
+#define SIR_LTMODE_NELBE (0x01 << 7)
+#define SIR_PHYMODE3 0x310
+#define SIR_PHYMODE4 0x314
+#define SIR_PHYMODE1 0x32c
+#define SIR_PHYMODE2 0x330
+#define SIR_BIST_CTRL 0x334
+#define SIR_BIST_DW1 0x338
+#define SIR_BIST_DW2 0x33c
+#define SIR_SERR_IRQ_MASK 0x340
+#define SIR_SATA_IFCTRL 0x344
+#define SIR_SATA_TESTCTRL 0x348
+#define SIR_SATA_IFSTATUS 0x34c
+#define SIR_VEND_UNIQ 0x35c
+#define SIR_FIS_CFG 0x360
+#define SIR_FIS_IRQ_CAUSE 0x364
+#define SIR_FIS_IRQ_MASK 0x368
+#define SIR_FIS_DWORD0 0x370
+#define SIR_FIS_DWORD1 0x374
+#define SIR_FIS_DWORD2 0x378
+#define SIR_FIS_DWORD3 0x37c
+#define SIR_FIS_DWORD4 0x380
+#define SIR_FIS_DWORD5 0x384
+#define SIR_FIS_DWORD6 0x388
+#define SIR_PHYM9_GEN2 0x398
+#define SIR_PHYM9_GEN1 0x39c
+#define SIR_PHY_CFG 0x3a0
+#define SIR_PHYCTL 0x3a4
+#define SIR_PHYM10 0x3a8
+#define SIR_PHYM12 0x3b0
+
+/* Shadow registers */
+#define PIO_DATA 0x100
+#define PIO_ERR_FEATURES 0x104
+#define PIO_SECTOR_COUNT 0x108
+#define PIO_LBA_LOW 0x10c
+#define PIO_LBA_MID 0x110
+#define PIO_LBA_HI 0x114
+#define PIO_DEVICE 0x118
+#define PIO_CMD_STATUS 0x11c
+#define PIO_STATUS_ERR (0x01 << 0)
+#define PIO_STATUS_DRQ (0x01 << 3)
+#define PIO_STATUS_DF (0x01 << 5)
+#define PIO_STATUS_DRDY (0x01 << 6)
+#define PIO_STATUS_BSY (0x01 << 7)
+#define PIO_CTRL_ALTSTAT 0x120
+
+/* SATAHC arbiter registers */
+#define SATAHC_CFG 0x000
+#define SATAHC_RQOP 0x004
+#define SATAHC_RQIP 0x008
+#define SATAHC_ICT 0x00c
+#define SATAHC_ITT 0x010
+#define SATAHC_ICR 0x014
+#define SATAHC_ICR_PORT0 (0x01 << 0)
+#define SATAHC_ICR_PORT1 (0x01 << 1)
+#define SATAHC_MIC 0x020
+#define SATAHC_MIM 0x024
+#define SATAHC_LED_CFG 0x02c
+
+#define REQUEST_QUEUE_SIZE 32
+#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
+
+struct crqb {
+ u32 dtb_low; /* DW0 */
+ u32 dtb_high; /* DW1 */
+ u32 control_flags; /* DW2 */
+ u32 drb_count; /* DW3 */
+ u32 ata_cmd_feat; /* DW4 */
+ u32 ata_addr; /* DW5 */
+ u32 ata_addr_exp; /* DW6 */
+ u32 ata_sect_count; /* DW7 */
+};
+
+#define CRQB_ALIGN 0x400
+
+#define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
+#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
+#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
+#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
+#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
+#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
+#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
+#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
+
+#define CRQB_CMDFEAT_CMDMASK (0xff << 16)
+#define CRQB_CMDFEAT_CMDSHIFT 16
+#define CRQB_CMDFEAT_FEATMASK (0xff << 16)
+#define CRQB_CMDFEAT_FEATSHIFT 24
+
+#define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
+#define CRQB_ADDR_LBA_LOWSHIFT 0
+#define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
+#define CRQB_ADDR_LBA_MIDSHIFT 8
+#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
+#define CRQB_ADDR_LBA_HIGHSHIFT 16
+#define CRQB_ADDR_DEVICE_MASK (0xff << 24)
+#define CRQB_ADDR_DEVICE_SHIFT 24
+
+#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
+#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
+#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
+#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
+#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
+#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
+#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
+#define CRQB_ADDR_FEATURE_EXP_SHIFT 24
+
+#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
+#define CRQB_SECTCOUNT_COUNT_SHIFT 0
+#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
+#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
+
+#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
+
+struct eprd {
+ u32 phyaddr_low;
+ u32 bytecount_eot;
+ u32 phyaddr_hi;
+ u32 reserved;
+};
+
+#define EPRD_PHYADDR_MASK 0xfffffffe
+#define EPRD_BYTECOUNT_MASK 0x0000ffff
+#define EPRD_EOT (0x01 << 31)
+
+struct crpb {
+ u32 id;
+ u32 flags;
+ u32 timestamp;
+};
+
+#define CRPB_ALIGN 0x100
+
+#define READ_CMD 0
+#define WRITE_CMD 1
+
+/*
+ * Since we don't use PRDs yet max transfer size
+ * is 64KB
+ */
+#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
+
+/* Keep track if hw is initialized or not */
+static u32 hw_init;
+
+struct mv_priv {
+ char name[12];
+ u32 link;
+ u32 regbase;
+ u32 queue_depth;
+ u16 pio;
+ u16 mwdma;
+ u16 udma;
+
+ void *crqb_alloc;
+ struct crqb *request;
+
+ void *crpb_alloc;
+ struct crpb *response;
+};
+
+static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
+{
+ ulong start;
+
+ start = get_timer(0);
+ do {
+ if ((in_le32(addr) & mask) == val)
+ return 0;
+ } while (get_timer(start) < timeout_msec);
+
+ return -ETIMEDOUT;
+}
+
+/* Cut from sata_mv in linux kernel */
+static int mv_stop_edma_engine(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int i;
+
+ /* Disable eDMA. The disable bit auto clears. */
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
+
+ /* Wait for the chip to confirm eDMA is off. */
+ for (i = 10000; i > 0; i--) {
+ u32 reg = in_le32(priv->regbase + EDMA_CMD);
+ if (!(reg & EDMA_CMD_ENEDMA)) {
+ debug("EDMA stop on port %d succesful\n", port);
+ return 0;
+ }
+ udelay(10);
+ }
+ debug("EDMA stop on port %d failed\n", port);
+ return -1;
+}
+
+static int mv_start_edma_engine(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ /* Check preconditions */
+ tmp = in_le32(priv->regbase + SIR_SSTATUS);
+ if ((tmp & SSTATUS_DET_MASK) != 0x03) {
+ printf("Device error on port: %d\n", port);
+ return -1;
+ }
+
+ tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
+ if (tmp & (ATA_BUSY | ATA_DRQ)) {
+ printf("Device not ready on port: %d\n", port);
+ return -1;
+ }
+
+ /* Clear interrupt cause */
+ out_le32(priv->regbase + EDMA_IECR, 0x0);
+
+ tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
+ tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
+ out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
+
+ /* Configure edma operation */
+ tmp = in_le32(priv->regbase + EDMA_CFG);
+ tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
+ tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
+ out_le32(priv->regbase + EDMA_CFG, tmp);
+
+ out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
+
+ /* Configure fis, set all to no-wait for now */
+ out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
+
+ /* Setup request queue */
+ out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RQIPR, priv->request);
+ out_le32(priv->regbase + EDMA_RQOPR, 0x0);
+
+ /* Setup response queue */
+ out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RSOPR, priv->response);
+ out_le32(priv->regbase + EDMA_RSIPR, 0x0);
+
+ /* Start edma */
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
+
+ return 0;
+}
+
+static int mv_reset_channel(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ /* Make sure edma is stopped */
+ mv_stop_edma_engine(port);
+
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
+ udelay(25); /* allow reset propagation */
+ out_le32(priv->regbase + EDMA_CMD, 0);
+ mdelay(10);
+
+ return 0;
+}
+
+static void mv_reset_port(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ mv_reset_channel(port);
+
+ out_le32(priv->regbase + EDMA_CMD, 0x0);
+ out_le32(priv->regbase + EDMA_CFG, 0x101f);
+ out_le32(priv->regbase + EDMA_IECR, 0x0);
+ out_le32(priv->regbase + EDMA_IEMR, 0x0);
+ out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RQIPR, 0x0);
+ out_le32(priv->regbase + EDMA_RQOPR, 0x0);
+ out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RSIPR, 0x0);
+ out_le32(priv->regbase + EDMA_RSOPR, 0x0);
+ out_le32(priv->regbase + EDMA_IORTO, 0xfa);
+}
+
+static void mv_reset_one_hc(void)
+{
+ out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
+ out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
+ out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
+}
+
+static int probe_port(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int tries, tries2, set15 = 0;
+ u32 tmp;
+
+ debug("Probe port: %d\n", port);
+
+ for (tries = 0; tries < 2; tries++) {
+ /* Clear SError */
+ out_le32(priv->regbase + SIR_SERROR, 0x0);
+
+ /* trigger com-init */
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
+ out_le32(priv->regbase + SIR_SCONTROL, tmp);
+
+ mdelay(1);
+
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ tries2 = 5;
+ do {
+ tmp = (tmp & 0x0f0) | 0x300;
+ out_le32(priv->regbase + SIR_SCONTROL, tmp);
+ mdelay(10);
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ } while ((tmp & 0xf0f) != 0x300 && tries2--);
+
+ mdelay(10);
+
+ for (tries2 = 0; tries2 < 200; tries2++) {
+ tmp = in_le32(priv->regbase + SIR_SSTATUS);
+ if ((tmp & SSTATUS_DET_MASK) == 0x03) {
+ debug("Found device on port\n");
+ return 0;
+ }
+ mdelay(1);
+ }
+
+ if ((tmp & SSTATUS_DET_MASK) == 0) {
+ debug("No device attached on port %d\n", port);
+ return -ENODEV;
+ }
+
+ if (!set15) {
+ /* Try on 1.5Gb/S */
+ debug("Try 1.5Gb link\n");
+ set15 = 1;
+ out_le32(priv->regbase + SIR_SCONTROL, 0x304);
+
+ tmp = in_le32(priv->regbase + SIR_ICFG);
+ tmp &= ~SIR_CFG_GEN2EN;
+ out_le32(priv->regbase + SIR_ICFG, tmp);
+
+ mv_reset_channel(port);
+ }
+ }
+
+ debug("Failed to probe port\n");
+ return -1;
+}
+
+/* Get request queue in pointer */
+static int get_reqip(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
+ tmp = tmp >> EDMA_RQIPR_IPSHIFT;
+
+ return tmp;
+}
+
+static void set_reqip(int port, int reqin)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
+ tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
+ out_le32(priv->regbase + EDMA_RQIPR, tmp);
+}
+
+/* Get next available slot, ignoring possible overwrite */
+static int get_next_reqip(int port)
+{
+ int slot = get_reqip(port);
+ slot = (slot + 1) % REQUEST_QUEUE_SIZE;
+ return slot;
+}
+
+/* Get response queue in pointer */
+static int get_rspip(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
+ tmp = tmp >> EDMA_RSIPR_IPSHIFT;
+
+ return tmp;
+}
+
+/* Get response queue out pointer */
+static int get_rspop(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
+ tmp = tmp >> EDMA_RSOPR_OPSHIFT;
+ return tmp;
+}
+
+/* Get next response queue pointer */
+static int get_next_rspop(int port)
+{
+ return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE;
+}
+
+/* Set response queue pointer */
+static void set_rspop(int port, int reqin)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
+ tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
+
+ out_le32(priv->regbase + EDMA_RSOPR, tmp);
+}
+
+static int wait_dma_completion(int port, int index, u32 timeout_msec)
+{
+ u32 tmp, res;
+
+ tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
+ res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
+ tmp, timeout_msec);
+ if (res)
+ printf("Failed to wait for completion on port %d\n", port);
+
+ return res;
+}
+
+static void process_responses(int port)
+{
+#ifdef DEBUG
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+#endif
+ u32 tmp;
+ u32 outind = get_rspop(port);
+
+ /* Ack interrupts */
+ tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
+ if (port == 0)
+ tmp &= ~(BIT(0) | BIT(8));
+ else
+ tmp &= ~(BIT(1) | BIT(9));
+ tmp &= ~(BIT(4));
+ out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
+
+ while (get_rspip(port) != outind) {
+#ifdef DEBUG
+ debug("Response index %d flags %08x on port %d\n", outind,
+ priv->response[outind].flags, port);
+#endif
+ outind = get_next_rspop(port);
+ set_rspop(port, outind);
+ }
+}
+
+static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
+ u8 *buffer, u32 len, u32 iswrite)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ struct crqb *req;
+ int slot;
+
+ if (len >= 64 * 1024) {
+ printf("We only support <64K transfers for now\n");
+ return -1;
+ }
+
+ /* Initialize request */
+ slot = get_reqip(port);
+ memset(&priv->request[slot], 0, sizeof(struct crqb));
+ req = &priv->request[slot];
+
+ req->dtb_low = (u32)buffer;
+
+ /* Dont use PRDs */
+ req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
+ req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
+ req->control_flags |=
+ ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
+ & CRQB_CNTRLFLAGS_PMPORTMASK);
+
+ req->drb_count = len;
+
+ req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
+ CRQB_CMDFEAT_CMDMASK;
+ req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
+ CRQB_CMDFEAT_FEATMASK;
+
+ req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
+ CRQB_ADDR_LBA_LOWMASK;
+ req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
+ CRQB_ADDR_LBA_MIDMASK;
+ req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
+ CRQB_ADDR_LBA_HIGHMASK;
+ req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
+ CRQB_ADDR_DEVICE_MASK;
+
+ req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
+ CRQB_ADDR_LBA_LOW_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
+ CRQB_ADDR_LBA_MID_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
+ CRQB_ADDR_LBA_HIGH_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
+ CRQB_ADDR_FEATURE_EXP_MASK;
+
+ req->ata_sect_count =
+ (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
+ CRQB_SECTCOUNT_COUNT_MASK;
+ req->ata_sect_count |=
+ (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
+ CRQB_SECTCOUNT_COUNT_EXP_MASK;
+
+ /* Flush data */
+ flush_dcache_range((u32)req, (u32)req + sizeof(*req));
+
+ /* Trigger operation */
+ slot = get_next_reqip(port);
+ set_reqip(port, slot);
+
+ /* Wait for completion */
+ if (wait_dma_completion(port, slot, 10000)) {
+ printf("ATA operation timed out\n");
+ return -1;
+ }
+
+ process_responses(port);
+
+ /* Invalidate data on read */
+ if (buffer && len)
+ invalidate_dcache_range((u32)buffer, (u32)buffer + len);
+
+ return len;
+}
+
+static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
+ u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d cfis;
+ u32 res;
+ u64 block;
+
+ block = (u64)start;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
+
+ cfis.lba_high_exp = (block >> 40) & 0xff;
+ cfis.lba_mid_exp = (block >> 32) & 0xff;
+ cfis.lba_low_exp = (block >> 24) & 0xff;
+ cfis.lba_high = (block >> 16) & 0xff;
+ cfis.lba_mid = (block >> 8) & 0xff;
+ cfis.lba_low = block & 0xff;
+ cfis.device = ATA_LBA;
+ cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
+ cfis.sector_count = blkcnt & 0xff;
+
+ res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
+ is_write);
+
+ return res >= 0 ? blkcnt : res;
+}
+
+static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
+ int is_write)
+{
+ struct sata_fis_h2d cfis;
+ lbaint_t block;
+ u32 res;
+
+ block = start;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+ cfis.device = ATA_LBA;
+
+ cfis.device |= (block >> 24) & 0xf;
+ cfis.lba_high = (block >> 16) & 0xff;
+ cfis.lba_mid = (block >> 8) & 0xff;
+ cfis.lba_low = block & 0xff;
+ cfis.sector_count = (u8)(blkcnt & 0xff);
+
+ res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
+ is_write);
+
+ return res >= 0 ? blkcnt : res;
+}
+
+static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer, int is_write)
+{
+ lbaint_t start, blks;
+ u8 *addr;
+ int max_blks;
+
+ debug("%s: %ld %ld\n", __func__, blknr, blkcnt);
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = MV_ATA_MAX_SECTORS;
+ do {
+ if (blks > max_blks) {
+ if (sata_dev_desc[dev].lba48) {
+ mv_sata_rw_cmd_ext(dev, start, max_blks, addr,
+ is_write);
+ } else {
+ mv_sata_rw_cmd(dev, start, max_blks, addr,
+ is_write);
+ }
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ if (sata_dev_desc[dev].lba48) {
+ mv_sata_rw_cmd_ext(dev, start, blks, addr,
+ is_write);
+ } else {
+ mv_sata_rw_cmd(dev, start, blks, addr,
+ is_write);
+ }
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blkcnt;
+}
+
+static int mv_ata_exec_ata_cmd_nondma(int port,
+ struct sata_fis_h2d *cfis, u8 *buffer,
+ u32 len, u32 iswrite)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int i;
+ u16 *tp;
+
+ debug("%s\n", __func__);
+
+ out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
+ out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
+ out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
+ out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
+ out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
+ out_le32(priv->regbase + PIO_DEVICE, cfis->device);
+ out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
+
+ if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
+ ATA_BUSY, 0x0, 10000)) {
+ debug("Failed to wait for completion\n");
+ return -1;
+ }
+
+ if (len > 0) {
+ tp = (u16 *)buffer;
+ for (i = 0; i < len / 2; i++) {
+ if (iswrite)
+ out_le16(priv->regbase + PIO_DATA, *tp++);
+ else
+ *tp++ = in_le16(priv->regbase + PIO_DATA);
+ }
+ }
+
+ return len;
+}
+
+static int mv_sata_identify(int port, u16 *id)
+{
+ struct sata_fis_h2d h2d;
+
+ memset(&h2d, 0, sizeof(struct sata_fis_h2d));
+
+ h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ h2d.command = ATA_CMD_ID_ATA;
+
+ /* Give device time to get operational */
+ mdelay(10);
+
+ return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id,
+ ATA_ID_WORDS * 2, READ_CMD);
+}
+
+static void mv_sata_xfer_mode(int port, u16 *id)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ priv->pio = id[ATA_ID_PIO_MODES];
+ priv->mwdma = id[ATA_ID_MWDMA_MODES];
+ priv->udma = id[ATA_ID_UDMA_MODES];
+ debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
+ priv->udma);
+}
+
+static void mv_sata_set_features(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ struct sata_fis_h2d cfis;
+ u8 udma_cap;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_SET_FEATURES;
+ cfis.features = SETFEATURES_XFER;
+
+ /* First check the device capablity */
+ udma_cap = (u8) (priv->udma & 0xff);
+
+ if (udma_cap == ATA_UDMA6)
+ cfis.sector_count = XFER_UDMA_6;
+ if (udma_cap == ATA_UDMA5)
+ cfis.sector_count = XFER_UDMA_5;
+ if (udma_cap == ATA_UDMA4)
+ cfis.sector_count = XFER_UDMA_4;
+ if (udma_cap == ATA_UDMA3)
+ cfis.sector_count = XFER_UDMA_3;
+
+ mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD);
+}
+
+int mv_sata_spin_down(int dev)
+{
+ struct sata_fis_h2d cfis;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
+
+ if (priv->link == 0) {
+ debug("No device on port: %d\n", dev);
+ return 1;
+ }
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_STANDBY;
+
+ return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
+}
+
+int mv_sata_spin_up(int dev)
+{
+ struct sata_fis_h2d cfis;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
+
+ if (priv->link == 0) {
+ debug("No device on port: %d\n", dev);
+ return 1;
+ }
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_IDLE;
+
+ return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
+}
+
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+ return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD);
+}
+
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
+{
+ return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD);
+}
+
+/*
+ * Initialize SATA memory windows
+ */
+static void mvsata_ide_conf_mbus_windows(void)
+{
+ const struct mbus_dram_target_info *dram;
+ int i;
+
+ dram = mvebu_mbus_dram_info();
+
+ /* Disable windows, Set Size/Base to 0 */
+ for (i = 0; i < 4; i++) {
+ writel(0, MVSATA_WIN_CONTROL(i));
+ writel(0, MVSATA_WIN_BASE(i));
+ }
+
+ for (i = 0; i < dram->num_cs; i++) {
+ const struct mbus_dram_window *cs = dram->cs + i;
+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ MVSATA_WIN_CONTROL(i));
+ writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
+ }
+}
+
+int init_sata(int dev)
+{
+ struct mv_priv *priv;
+
+ debug("Initialize sata dev: %d\n", dev);
+
+ if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
+ printf("Invalid sata device %d\n", dev);
+ return -1;
+ }
+
+ priv = (struct mv_priv *)malloc(sizeof(struct mv_priv));
+ if (!priv) {
+ printf("Failed to allocate memory for private sata data\n");
+ return -ENOMEM;
+ }
+
+ memset((void *)priv, 0, sizeof(struct mv_priv));
+
+ /* Allocate and align request buffer */
+ priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
+ CRQB_ALIGN);
+ if (!priv->crqb_alloc) {
+ printf("Unable to allocate memory for request queue\n");
+ return -ENOMEM;
+ }
+ memset(priv->crqb_alloc, 0,
+ sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
+ priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
+ ~(CRQB_ALIGN - 1));
+
+ /* Allocate and align response buffer */
+ priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
+ CRPB_ALIGN);
+ if (!priv->crpb_alloc) {
+ printf("Unable to allocate memory for response queue\n");
+ return -ENOMEM;
+ }
+ memset(priv->crpb_alloc, 0,
+ sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
+ priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
+ ~(CRPB_ALIGN - 1));
+
+ sata_dev_desc[dev].priv = (void *)priv;
+
+ sprintf(priv->name, "SATA%d", dev);
+
+ priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE;
+
+ if (!hw_init) {
+ debug("Initialize sata hw\n");
+ hw_init = 1;
+ mv_reset_one_hc();
+ mvsata_ide_conf_mbus_windows();
+ }
+
+ mv_reset_port(dev);
+
+ if (probe_port(dev)) {
+ priv->link = 0;
+ return -ENODEV;
+ }
+ priv->link = 1;
+
+ return 0;
+}
+
+int reset_sata(int dev)
+{
+ return 0;
+}
+
+int scan_sata(int port)
+{
+ unsigned char serial[ATA_ID_SERNO_LEN + 1];
+ unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
+ unsigned char product[ATA_ID_PROD_LEN + 1];
+ u64 n_sectors;
+ u16 *id;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ if (!priv->link)
+ return -ENODEV;
+
+ id = (u16 *)malloc(ATA_ID_WORDS * 2);
+ if (!id) {
+ printf("Failed to malloc id data\n");
+ return -ENOMEM;
+ }
+
+ mv_sata_identify(port, id);
+ ata_swap_buf_le16(id, ATA_ID_WORDS);
+#ifdef DEBUG
+ ata_dump_id(id);
+#endif
+
+ /* Serial number */
+ ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
+ memcpy(sata_dev_desc[port].product, serial, sizeof(serial));
+
+ /* Firmware version */
+ ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
+ memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware));
+
+ /* Product model */
+ ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
+ memcpy(sata_dev_desc[port].vendor, product, sizeof(product));
+
+ /* Total sectors */
+ n_sectors = ata_id_n_sectors(id);
+ sata_dev_desc[port].lba = n_sectors;
+
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ sata_dev_desc[port].lba48 = 1;
+ debug("Device support LBA48\n");
+ }
+
+ /* Get the NCQ queue depth from device */
+ priv->queue_depth = ata_id_queue_depth(id);
+
+ /* Get the xfer mode from device */
+ mv_sata_xfer_mode(port, id);
+
+ /* Set the xfer mode to highest speed */
+ mv_sata_set_features(port);
+
+ /* Start up */
+ mv_start_edma_engine(port);
+
+ return 0;
+}
return in16(base + off);
}
-static unsigned long systemace_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer);
+static unsigned long systemace_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer);
static block_dev_desc_t systemace_dev = { 0 };
* the dev_desc) to read blocks of data. The return value is the
* number of blocks read. A zero return indicates an error.
*/
-static unsigned long systemace_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer)
+static unsigned long systemace_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
{
int retry;
unsigned blk_countdown;
bool "Support numbered aliases in device tree"
depends on DM
default y
+ help
+ Most boards will have a '/aliases' node containing the path to
+ numbered devices (e.g. serial0 = &serial0). This feature can be
+ disabled if it is not required.
+
+config SPL_DM_SEQ_ALIAS
+ bool "Support numbered aliases in device tree in SPL"
+ depends on DM
+ default n
help
Most boards will have a '/aliases' node containing the path to
numbered devices (e.g. serial0 = &serial0). This feature can be
dev->seq = -1;
dev->req_seq = -1;
- if (CONFIG_IS_ENABLED(OF_CONTROL) && IS_ENABLED(CONFIG_DM_SEQ_ALIAS)) {
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) {
/*
* Some devices, such as a SPI bus, I2C bus and serial ports
* are numbered using aliases.
return dev->uclass->uc_drv->name;
}
-fdt_addr_t dev_get_addr(struct udevice *dev)
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
fdt_addr_t addr;
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
const fdt32_t *reg;
+ int len = 0;
+ int na, ns;
- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
- if (!reg)
+ na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (na < 1) {
+ debug("bad #address-cells\n");
return FDT_ADDR_T_NONE;
+ }
+
+ ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (ns < 0) {
+ debug("bad #size-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+ if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
+ debug("Req index out of range\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ reg += index * (na + ns);
/*
* Use the full-fledged translate function for complex
addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev->parent->of_offset,
dev->of_offset, "reg",
- 0, NULL);
+ index, NULL);
if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
if (device_get_uclass_id(dev->parent) ==
UCLASS_SIMPLE_BUS)
#endif
}
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+ return dev_get_addr_index(dev, 0);
+}
+
bool device_has_children(struct udevice *dev)
{
return !list_empty(&dev->child_head);
readl(&sdr_ctrl->protport_default));
for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
sdram_get_rule(&rule);
debug("Rule %d, rules ...\n", rules);
debug(" sdram start %x\n", rule.sdram_start);
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* from ddr3 spd, please refer to the spec
* JEDEC standard No.21-C 4_01_02_11R18.pdf
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
return MV_OK;
}
-/*
- * Read training result table
- */
-int hws_ddr3_tip_read_training_result(
- u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
-{
- dev_num = dev_num;
-
- if (result == NULL)
- return MV_BAD_PARAM;
- memcpy(result, training_result, sizeof(result));
-
- return MV_OK;
-}
-
/*
* Get training result info pointer
*/
struct hws_topology_map *topology);
int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
-int hws_ddr3_tip_read_training_result(u32 dev_num,
- enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
#define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define ECC_SUPPORT
+#endif
#define NEW_FABRIC_TWSI_ADDR 0x4E
#ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
* DDR3_TRAINING_DEBUG - Debug prints of internal code
*/
#define DDR_TARGET_FABRIC 5
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define DRAM_ECC 1
+#else
+#define DRAM_ECC 0
+#endif
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
#define BUS_WIDTH 32
#else
#define BUS_WIDTH 64
#define __AXP_MC_STATIC_H
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
-#else /* MV_DDR_64BIT */
+#else /* CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B040}, /*Dunit Control Low Register */
};
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
/*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
#endif
DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n")
#ifdef MV_DEBUG_WL
+#define DEBUG_WL_S(s) puts(s)
+#define DEBUG_WL_D(d, l) printf("%x", d)
#define DEBUG_RL_S(s) \
debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s)
#define DEBUG_RL_D(d, l) \
DEBUG_WL_FULL_D((u32) phase, 1);
DEBUG_WL_FULL_S(", Delay = ");
DEBUG_WL_FULL_D((u32) delay, 1);
- DEBUG_WL_FULL_S(", Counter = ");
- DEBUG_WL_FULL_D((u32) i, 1);
DEBUG_WL_FULL_S("\n");
/* Drive DQS high for one cycle - All data PUPs */
static long dfu_file_buf_len;
static long dfu_file_buf_filled;
-static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
-{
- int ret;
-
- if (part == mmc->part_num)
- return 0;
-
- ret = mmc_switch_part(dfu->data.mmc.dev_num, part);
- if (ret) {
- error("Cannot switch to partition %d\n", part);
- return ret;
- }
- mmc->part_num = part;
-
- return 0;
-}
-
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
{
}
if (dfu->data.mmc.hw_partition >= 0) {
- part_num_bkp = mmc->part_num;
- ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition);
+ part_num_bkp = mmc->block_dev.hwpart;
+ ret = mmc_select_hwpart(dfu->data.mmc.dev_num,
+ dfu->data.mmc.hw_partition);
if (ret)
return ret;
}
dfu->data.mmc.dev_num, blk_start, blk_count, buf);
switch (op) {
case DFU_OP_READ:
- n = mmc->block_dev.block_read(dfu->data.mmc.dev_num, blk_start,
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk_start,
blk_count, buf);
break;
case DFU_OP_WRITE:
- n = mmc->block_dev.block_write(dfu->data.mmc.dev_num, blk_start,
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
blk_count, buf);
break;
default:
if (n != blk_count) {
error("MMC operation failed");
if (dfu->data.mmc.hw_partition >= 0)
- mmc_access_part(dfu, mmc, part_num_bkp);
+ mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
return -EIO;
}
if (dfu->data.mmc.hw_partition >= 0) {
- ret = mmc_access_part(dfu, mmc, part_num_bkp);
+ ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
if (ret)
return ret;
}
/* Prior programming the FPGA, all bridges need to be shut off */
/* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
+ writel(0, &sysmgr_regs->fpgaintfgrp_gbl);
/* Disable all signals from FPGA to HPS SDRAM */
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
* 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
* Changes for multibus/multiadapter I2C support.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
-#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
+#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
#include <asm/arch/soc.h>
#elif defined(CONFIG_SUNXI)
#include <asm/arch/i2c.h>
#define MVTWSI_CONTROL_TWSIEN 0x00000040
#define MVTWSI_CONTROL_INTEN 0x00000080
+/*
+ * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1,
+ * on other platforms it is a normal r/w bit which is cleared by writing 0.
+ */
+
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
+#else
+#define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
+#endif
+
/*
* Status register values -- only those expected in normal master
* operation on non-10-bit-address devices; whatever status we don't
#ifdef CONFIG_I2C_MVTWSI_BASE4
case 4:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE5
+ case 5:
+ return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5;
#endif
default:
printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
/* globally set TWSIEN in case it was not */
twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
/* assert START */
- writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
+ twsi_control_flags |= MVTWSI_CONTROL_START | MVTWSI_CONTROL_CLEAR_IFLG;
+ writel(twsi_control_flags, &twsi->control);
/* wait for controller to process START */
return twsi_wait(adap, expected_status);
}
/* put byte in data register for sending */
writel(byte, &twsi->data);
/* clear any pending interrupt -- that'll cause sending */
- writel(twsi_control_flags, &twsi->control);
+ writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and check ACK */
return twsi_wait(adap, expected_status);
}
else
expected_status = MVTWSI_STATUS_DATA_R_NAK;
/* acknowledge *previous state* and launch receive */
- writel(twsi_control_flags, &twsi->control);
+ writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and assert ACK or NAK */
status = twsi_wait(adap, expected_status);
/* if we did receive expected byte then store it */
/* assert STOP */
control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
- writel(control, &twsi->control);
+ writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
do {
stop_status = readl(&twsi->status);
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE5
+U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
+ twsi_i2c_read, twsi_i2c_write,
+ twsi_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
+
+#endif
/*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst);
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
+ vdst);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
hang();
/*
* Read source addr from sd card
*/
- err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
+ err = mmc->block_dev.block_read(&mmc->block_dev,
+ CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
if (err != 1) {
puts("spl: mmc read failed!!\n");
free(tmp_buf);
#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
- err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
return blkcnt;
}
-static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
+static ulong mmc_bread(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
{
+ int dev_num = block_dev->dev;
+ int err;
lbaint_t cur, blocks_todo = blkcnt;
if (blkcnt == 0)
if (!mmc)
return 0;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return 0;
+
if ((start + blkcnt) > mmc->block_dev.lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
if (!mmc)
return -ENODEV;
- if (mmc->part_num == hwpart)
+ if (mmc->block_dev.hwpart == hwpart)
return 0;
if (mmc->part_config == MMCPART_NOAVAILABLE) {
if (ret)
return ret;
- mmc->part_num = hwpart;
-
return 0;
}
* Set the capacity if the switch succeeded or was intended
* to return to representing the raw device.
*/
- if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
+ if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
ret = mmc_set_capacity(mmc, part_num);
+ mmc->block_dev.hwpart = part_num;
+ }
return ret;
}
mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
}
- err = mmc_set_capacity(mmc, mmc->part_num);
+ err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
if (err)
return err;
/* fill in device description */
mmc->block_dev.lun = 0;
+ mmc->block_dev.hwpart = 0;
mmc->block_dev.type = 0;
mmc->block_dev.blksz = mmc->read_bl_len;
mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
return err;
/* The internal partition reset to user partition(0) at every CMD0*/
- mmc->part_num = 0;
+ mmc->block_dev.hwpart = 0;
/* Test for SD version 2 */
err = mmc_send_if_cond(mmc);
#ifndef CONFIG_SPL_BUILD
-extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt);
+unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt);
-extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
- const void *src);
+unsigned long mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src);
#else /* CONFIG_SPL_BUILD */
/* SPL will never write or erase, declare dummies to reduce code size. */
-static inline unsigned long mmc_berase(int dev_num, lbaint_t start,
- lbaint_t blkcnt)
+static inline unsigned long mmc_berase(block_dev_desc_t *block_dev,
+ lbaint_t start, lbaint_t blkcnt)
{
return 0;
}
-static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
- const void *src)
+static inline ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src)
{
return 0;
}
return err;
}
-unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt)
+unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt)
{
+ int dev_num = block_dev->dev;
int err = 0;
u32 start_rem, blkcnt_rem;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return -1;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return -1;
+
/*
* We want to see if the requested start or total block count are
* unaligned. We discard the whole numbers and only care about the
return blkcnt;
}
-ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src)
+ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt,
+ const void *src)
{
+ int dev_num = block_dev->dev;
lbaint_t cur, blocks_todo = blkcnt;
+ int err;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return 0;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return 0;
+
if (mmc_set_blocklen(mmc, mmc->write_bl_len))
return 0;
/* use non-removeable as sdcard and emmc as judgement */
if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
+ host->dev_index = 0;
+ else
host->dev_index = 1;
return 0;
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _SH_MMCIF_H_
panic("Failed to allocate memory\n");
if (mmc_getcd(mmc) && mmc_init(mmc) == 0 &&
- mmc->block_dev.block_read(mmc->block_dev.dev, 16, 1, buf) == 1 &&
+ mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 &&
strncmp(&buf[4], "eGON.BT0", 8) == 0)
valid_signature = 1;
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
*
* Based on original driver mpc5121_nfc.c.
*
- * This is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*
* Limitations:
* - Untested on MPC5125 and M54418.
void spi_flash_free(struct spi_flash *flash)
{
- spi_flash_remove(flash->spi->dev);
+ device_remove(flash->spi->dev);
}
int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
{
struct spi_slave *slave;
struct udevice *bus;
- char name[30], *str;
+ char *str;
int ret;
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_TINY_PRINTF)
+ str = "spi_flash";
+#else
+ char name[30];
+
snprintf(name, sizeof(name), "spi_flash@%d:%d", busnum, cs);
str = strdup(name);
+#endif
ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
"spi_flash_std", str, &bus, &slave);
if (ret)
return 0;
}
-int spi_flash_remove(struct udevice *dev)
-{
- return device_remove(dev);
-}
-
static int spi_flash_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
enum spi_dual_flash {
SF_SINGLE_FLASH = 0,
- SF_DUAL_STACKED_FLASH = 1 << 0,
- SF_DUAL_PARALLEL_FLASH = 1 << 1,
+ SF_DUAL_STACKED_FLASH = BIT(0),
+ SF_DUAL_PARALLEL_FLASH = BIT(1),
};
/* Enum list - Full read commands */
enum spi_read_cmds {
- ARRAY_SLOW = 1 << 0,
- ARRAY_FAST = 1 << 1,
- DUAL_OUTPUT_FAST = 1 << 2,
- DUAL_IO_FAST = 1 << 3,
- QUAD_OUTPUT_FAST = 1 << 4,
- QUAD_IO_FAST = 1 << 5,
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ QUAD_OUTPUT_FAST = BIT(3),
+ DUAL_IO_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
};
/* Normal - Extended - Full command set */
/* sf param flags */
enum {
-#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
- SECT_4K = 1 << 0,
+#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
+ SECT_4K = 0,
#else
- SECT_4K = 0 << 0,
+ SECT_4K = BIT(0),
#endif
- SECT_32K = 1 << 1,
- E_FSR = 1 << 2,
- SST_WR = 1 << 3,
- WR_QPP = 1 << 4,
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_WR = BIT(3),
+ WR_QPP = BIT(4),
};
enum spi_nor_option_flags {
- SNOR_F_SST_WR = (1 << 0),
- SNOR_F_USE_FSR = (1 << 1),
+ SNOR_F_SST_WR = BIT(0),
+ SNOR_F_USE_FSR = BIT(1),
};
#define SPI_FLASH_3B_ADDR_LEN 3
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS1 0x35
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
#endif
/* Common status */
-#define STATUS_WIP (1 << 0)
-#define STATUS_QEB_WINSPAN (1 << 1)
-#define STATUS_QEB_MXIC (1 << 6)
-#define STATUS_PEC (1 << 7)
+#define STATUS_WIP BIT(0)
+#define STATUS_QEB_WINSPAN BIT(1)
+#define STATUS_QEB_MXIC BIT(6)
+#define STATUS_PEC BIT(7)
+#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (flash->spi->mode & SPI_TX_BYTE)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
cmd[3] = addr >> 0;
}
-/* Read commands array */
-static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_QUAD_IO_FAST,
-};
-
static int read_sr(struct spi_flash *flash, u8 *rs)
{
int ret;
}
#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int read_evcr(struct spi_flash *flash, u8 *evcr)
+{
+ int ret;
+ const u8 cmd = CMD_READ_EVCR;
+
+ ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
+ if (ret < 0) {
+ debug("SF: error reading EVCR\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int write_evcr(struct spi_flash *flash, u8 evcr)
+{
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_WRITE_EVCR;
+ ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
+ if (ret < 0) {
+ debug("SF: error while writing EVCR register\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
{
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bank_end;
+ goto bar_end;
switch (idcode0) {
case SPI_FLASH_CFI_MFR_SPANSION:
return ret;
}
-bank_end:
+bar_end:
flash->bank_curr = curr_bank;
return 0;
}
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
+ struct spi_slave *spi = flash->spi;
+
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- flash->spi->flags |= SPI_XFER_U_PAGE;
+ spi->flags |= SPI_XFER_U_PAGE;
} else {
- flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ spi->flags &= ~SPI_XFER_U_PAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
if (buf == NULL)
timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
byte_addr = offset % page_size;
chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
- if (flash->spi->max_write_size)
+ if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
+ (size_t)spi->max_write_size);
spi_flash_addr(write_addr, cmd);
struct spi_slave *spi = flash->spi;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ struct spi_slave *spi = flash->spi;
u8 *cmd, cmdsz;
u32 remain_len, read_len, read_addr;
int bank_sel = 0;
/* Handle memory-mapped SPI */
if (flash->memory_map) {
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
}
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
spi_flash_copy_mmap(data, flash->memory_map + offset, len);
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
- spi_release_bus(flash->spi);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+ spi_release_bus(spi);
return 0;
}
#ifdef CONFIG_SPI_FLASH_SST
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
int ret;
u8 cmd[4] = {
CMD_SST_BP,
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
return ret;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
if (ret)
return ret;
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual, cmd_len;
int ret;
u8 cmd[4];
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
cmd[0], offset);
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len,
buf + actual, 2);
if (ret) {
debug("SF: sst word program failed\n");
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
-static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+static int macronix_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_MXIC) {
- debug("SF: mxic: QEB is already set\n");
- } else {
- ret = write_sr(flash, STATUS_QEB_MXIC);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_MXIC)
+ return 0;
+
+ ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+
+ /* read SR and check it */
+ ret = read_sr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
+ printf("SF: Macronix SR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_WINSPAN) {
- debug("SF: winspan: QEB is already set\n");
- } else {
- ret = write_cr(flash, STATUS_QEB_WINSPAN);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_WINSPAN)
+ return 0;
+
+ ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+
+ /* read CR and check it */
+ ret = read_cr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
+ printf("SF: Spansion CR Quad bit not clear\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int micron_quad_enable(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = read_evcr(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (!(qeb_status & STATUS_QEB_MICRON))
+ return 0;
+
+ ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
+ if (ret < 0)
+ return ret;
+
+ /* read EVCR and check it */
+ ret = read_evcr(flash, &qeb_status);
+ if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
+ printf("SF: Micron EVCR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
}
#endif
-static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
- return spi_flash_set_qeb_mxic(flash);
+ return macronix_quad_enable(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
- return spi_flash_set_qeb_winspan(flash);
+ return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- debug("SF: QEB is volatile for %02x flash\n", idcode0);
- return 0;
+ return micron_quad_enable(flash);
#endif
default:
printf("SF: Need set QEB func for %02x flash\n", idcode0);
struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params;
u16 jedec, ext_jedec;
- u8 idcode[5];
- u8 cmd;
+ u8 cmd, idcode[5];
int ret;
+ static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_ARRAY_FAST,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_IO_FAST };
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
/* Assign spi data */
flash->name = params->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = flash->spi->option;
+ flash->dual_flash = spi->option;
/* Assign spi flash flags */
if (params->flags & SST_WR)
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (spi->mode & SPI_TX_BYTE)
flash->write = sst_write_bp;
else
flash->write = sst_write_wp;
flash->sector_size = flash->erase_size;
/* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ cmd = fls(params->e_rd_cmd & spi->mode_rx);
if (cmd) {
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
}
/* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = spi_flash_set_qeb(flash, idcode[0]);
+ ret = set_quad_mode(flash, idcode[0]);
if (ret) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
return -EINVAL;
bus->read = tse_mdio_read;
bus->write = tse_mdio_write;
- snprintf(bus->name, sizeof(bus->name), name);
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
bus->priv = (void *)priv;
memset(emacfix, 0, sizeof(emac_device));
memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "emac");
+ strcpy(dev->name, "emac");
dev->iobase = iobase;
dev->priv = emacfix;
dev->init = at91emac_init;
memset (priv, 0, sizeof *priv);
- sprintf (dev->name, "ax88180");
+ strcpy(dev->name, "ax88180");
dev->iobase = AX88180_BASE;
dev->priv = priv;
dev->init = ax88180_init;
bus->read = cpsw_mdio_read;
bus->write = cpsw_mdio_write;
- sprintf(bus->name, name);
+ strcpy(bus->name, name);
mdio_register(bus);
}
return -1;
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "DaVinci-EMAC");
+ strcpy(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
- snprintf(bus->name, sizeof(bus->name), name);
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
bus->priv = (void *)mac_regs_p;
dev->halt = dm9000_halt;
dev->send = dm9000_send;
dev->recv = dm9000_rx;
- sprintf(dev->name, "dm9000");
+ strcpy(dev->name, "dm9000");
eth_register(dev);
eeprom->use_eerd = true;
eeprom->use_eewr = false;
break;
-
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- case e1000_ich8lan:
- {
- int32_t i = 0;
-
- eeprom->type = e1000_eeprom_ich8;
- eeprom->use_eerd = false;
- eeprom->use_eewr = false;
- eeprom->word_size = E1000_SHADOW_RAM_WORDS;
- uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
- ICH_FLASH_GFPREG);
- /* Zero the shadow RAM structure. But don't load it from NVM
- * so as to save time for driver init */
- if (hw->eeprom_shadow_ram != NULL) {
- for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = false;
- hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
- }
- }
-
- hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
- ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size = ((flash_size >> 16)
- & ICH_GFPREG_BASE_MASK) + 1;
- hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
-
- hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size /= 2 * sizeof(uint16_t);
- break;
- }
-#endif
default:
break;
}
if (eeprom->use_eerd == true)
return e1000_read_eeprom_eerd(hw, offset, words, data);
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- /* ICH EEPROM access is done via the ICH flash controller */
- if (eeprom->type == e1000_eeprom_ich8)
- return e1000_read_eeprom_ich8(hw, offset, words, data);
-#endif
/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
* acquired the EEPROM at this point, so any returns should relase it */
if (eeprom->type == e1000_eeprom_spi) {
* occuring when accessing our register space */
E1000_WRITE_FLUSH(hw);
}
-#if 0
- /* Set the PCI priority bit correctly in the CTRL register. This
- * determines if the adapter gives priority to receives, or if it
- * gives equal priority to transmits and receives. Valid only on
- * 82542 and 82543 silicon.
- */
- if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
- ctrl = E1000_READ_REG(hw, CTRL);
- E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
- }
-#endif
+
switch (hw->mac_type) {
case e1000_82545_rev_3:
case e1000_82546_rev_3:
break;
}
-#if 0
- /* Clear all of the statistics registers (clear on read). It is
- * important that we do this after we have tried to establish link
- * because the symbol error count will increment wildly if there
- * is no link.
- */
- e1000_clear_hw_cntrs(hw);
-
- /* ICH8 No-snoop bits are opposite polarity.
- * Set to snoop by default after reset. */
- if (hw->mac_type == e1000_ich8lan)
- e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
-#endif
-
if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
- /* put the card in its initial state */
-#if 0
- E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
-#endif
mdelay(10);
}
#ifndef CONFIG_E1000_NO_NVM
/* Validate the EEPROM and get chipset information */
-#if !defined(CONFIG_MVBC_1G)
if (e1000_init_eeprom_params(hw)) {
E1000_ERR(hw, "EEPROM is invalid!\n");
return -EINVAL;
if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
e1000_validate_eeprom_checksum(hw))
return -ENXIO;
-#endif
e1000_read_mac_addr(hw, enetaddr);
#endif
e1000_get_bus_type(hw);
e1000_media_type media_type;
e1000_fc_type fc;
e1000_bus_type bus_type;
-#if 0
- e1000_bus_speed bus_speed;
- e1000_bus_width bus_width;
- uint32_t io_base;
-#endif
uint32_t asf_firmware_present;
#ifndef CONFIG_E1000_NO_NVM
uint32_t eeprom_semaphore_present;
uint32_t original_fc;
uint32_t txcw;
uint32_t autoneg_failed;
-#if 0
- uint32_t max_frame_size;
- uint32_t min_frame_size;
- uint32_t mc_filter_type;
- uint32_t num_mc_addrs;
- uint32_t collision_delta;
- uint32_t tx_packet_delta;
- uint32_t ledctl_default;
- uint32_t ledctl_mode1;
- uint32_t ledctl_mode2;
-#endif
uint16_t autoneg_advertised;
uint16_t pci_cmd_word;
uint16_t fc_high_water;
uint16_t fc_low_water;
uint16_t fc_pause_time;
-#if 0
- uint16_t current_ifs_val;
- uint16_t ifs_min_val;
- uint16_t ifs_max_val;
- uint16_t ifs_step_size;
- uint16_t ifs_ratio;
-#endif
uint16_t device_id;
uint16_t vendor_id;
uint16_t subsystem_id;
uint8_t forced_speed_duplex;
uint8_t wait_autoneg_complete;
uint8_t dma_fairness;
-#if 0
- uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
-#endif
bool disable_polarity_correction;
bool speed_downgraded;
bool get_link_status;
bool report_tx_early;
bool phy_reset_disable;
bool initialize_hw_bits_disable;
-#if 0
- bool adaptive_ifs;
- bool ifs_params_forced;
- bool in_ifs_mode;
-#endif
e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state;
};
* These have been tested to perform correctly, but they are not used by any
* of the EEPROM commands at this time.
*/
-#if 0
-static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr)
+static __maybe_unused int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw,
+ bool intr)
{
u8 op[] = { SPI_EEPROM_DISABLE_WR };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
-static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
- u8 status, bool intr)
+static __maybe_unused int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
+ u8 status, bool intr)
{
u8 op[] = { SPI_EEPROM_WRITE_STATUS, status };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
-#endif
static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr)
{
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
bus->read = memac_mdio_read;
bus->write = memac_mdio_write;
bus->reset = memac_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = info->regs;
bus->read = tgec_mdio_read;
bus->write = tgec_mdio_write;
bus->reset = tgec_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = info->regs;
bus->read = tsec_phy_read;
bus->write = tsec_phy_write;
bus->reset = fsl_pq_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = (void *)info->regs;
memset(dev, 0, sizeof(*dev));
memset(priv, 0, sizeof(*priv));
- sprintf(dev->name, "FTGMAC100");
+ strcpy(dev->name, "FTGMAC100");
dev->iobase = CONFIG_FTGMAC100_BASE;
dev->init = ftgmac100_init;
dev->halt = ftgmac100_halt;
memset (dev, 0, sizeof (*dev));
memset (priv, 0, sizeof (*priv));
- sprintf (dev->name, "FTMAC100");
+ strcpy(dev->name, "FTMAC100");
dev->iobase = CONFIG_FTMAC100_BASE;
dev->init = ftmac100_init;
dev->halt = ftmac100_halt;
/* Make descriptor string */
if (greth->gbit_mac) {
- sprintf(dev->name, "GRETH_10/100/GB");
+ strcpy(dev->name, "GRETH_10/100/GB");
} else {
- sprintf(dev->name, "GRETH_10/100");
+ strcpy(dev->name, "GRETH_10/100");
}
/* initiate PHY, select speed/duplex depending on connected PHY */
mdio_bus->write = keystone2_mdio_write;
mdio_bus->reset = keystone2_mdio_reset;
mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
- sprintf(mdio_bus->name, "ethernet-mdio");
+ strcpy(mdio_bus->name, "ethernet-mdio");
res = mdio_register(mdio_bus);
if (res)
#endif
memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint));
- sprintf(dpmac_endpoint.type, "dpmac");
+ strcpy(dpmac_endpoint.type, "dpmac");
dpmac_endpoint.id = priv->dpmac_id;
memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint));
- sprintf(dpni_endpoint.type, "dpni");
+ strcpy(dpni_endpoint.type, "dpni");
dpni_endpoint.id = dflt_dpni->dpni_id;
err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS,
return -EFAULT;
}
+ /* write the phy and reg addressse into the MII address reg */
+ writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
+ ®s->madr);
+
+ /* write data to the MII write register */
+ writel(data, ®s->mwtd);
+
/* wait till the MII is not busy */
timeout = MII_TIMEOUT;
do {
return -EFAULT;
}
- /* write the phy and reg addressse into the MII address reg */
- writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
- ®s->madr);
-
- /* write data to the MII write register */
- writel(data, ®s->mwtd);
-
/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
reg_ofs, data);*/
}
bus->read = lpc32xx_eth_phy_read;
bus->write = lpc32xx_eth_phy_write;
- sprintf(bus->name, dev->name);
+ strcpy(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {
dev->send = mpc512x_fec_send;
dev->recv = mpc512x_fec_recv;
- sprintf (dev->name, "FEC");
+ strcpy(dev->name, "FEC");
eth_register (dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
dev->send = mpc5xxx_fec_send;
dev->recv = mpc5xxx_fec_recv;
- sprintf(dev->name, "FEC");
+ strcpy(dev->name, "FEC");
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
}
bus->read = mvgbe_phy_read;
bus->write = mvgbe_phy_write;
- sprintf(bus->name, dev->name);
+ strcpy(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {
* Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
*
* U-Boot version:
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
*
* Based on the Linux version which is:
* Copyright (C) 2012 Marvell
*/
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
#include <linux/compat.h>
#include <linux/mbus.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if !defined(CONFIG_PHYLIB)
# error Marvell mvneta requires PHYLIB
#endif
mvneta_port_enable(pp);
}
-static void mvneta_adjust_link(struct eth_device *dev)
+static void mvneta_adjust_link(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct phy_device *phydev = pp->phydev;
int status_change = 0;
}
}
-static int mvneta_open(struct eth_device *dev)
+static int mvneta_open(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
int ret;
ret = mvneta_setup_rxqs(pp);
}
/* Initialize hw */
-static int mvneta_init(struct mvneta_port *pp)
+static int mvneta_init2(struct mvneta_port *pp)
{
int queue;
}
/* Device initialization routine */
-static int mvneta_probe(struct eth_device *dev)
+static int mvneta_init(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvneta_port *pp = dev_get_priv(dev);
int err;
pp->tx_ring_size = MVNETA_MAX_TXD;
pp->rx_ring_size = MVNETA_MAX_RXD;
- err = mvneta_init(pp);
+ err = mvneta_init2(pp);
if (err < 0) {
dev_err(&pdev->dev, "can't init eth hal\n");
return err;
}
- mvneta_conf_mbus_windows(pp);
-
- mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def);
+ mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
err = mvneta_port_power_up(pp, pp->phy_interface);
if (err < 0) {
}
/*
- * smi_reg_read - miiphy_read callback function.
+ * mvneta_mdio_read - miiphy_read callback function.
*
* Returns 16bit phy register value, or 0xffff on error
*/
-static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data)
+static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = bus->priv;
u32 smi_reg;
u32 timeout;
/* check parameters */
- if (phy_adr > MVNETA_PHY_ADDR_MASK) {
- printf("Error: Invalid PHY address %d\n", phy_adr);
+ if (addr > MVNETA_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
return -EFAULT;
}
- if (reg_ofs > MVNETA_PHY_REG_MASK) {
- printf("Err: Invalid register offset %d\n", reg_ofs);
+ if (reg > MVNETA_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
return -EFAULT;
}
return -EFAULT;
/* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS)
+ smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
+ | (reg << MVNETA_SMI_REG_ADDR_OFFS)
| MVNETA_SMI_OPCODE_READ;
/* write the smi register */
mvreg_write(pp, MVNETA_SMI, smi_reg);
- /*wait till read value is ready */
+ /* wait till read value is ready */
timeout = MVNETA_SMI_TIMEOUT;
do {
for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
;
- *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK);
-
- return 0;
+ return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
}
/*
- * smi_reg_write - imiiphy_write callback function.
+ * mvneta_mdio_write - miiphy_write callback function.
*
* Returns 0 if write succeed, -EINVAL on bad parameters
* -ETIME on timeout
*/
-static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = bus->priv;
u32 smi_reg;
/* check parameters */
- if (phy_adr > MVNETA_PHY_ADDR_MASK) {
- printf("Error: Invalid PHY address %d\n", phy_adr);
+ if (addr > MVNETA_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
return -EFAULT;
}
- if (reg_ofs > MVNETA_PHY_REG_MASK) {
- printf("Err: Invalid register offset %d\n", reg_ofs);
+ if (reg > MVNETA_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
return -EFAULT;
}
return -EFAULT;
/* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << MVNETA_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS);
+ smi_reg = value << MVNETA_SMI_DATA_OFFS;
+ smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
+ | (reg << MVNETA_SMI_REG_ADDR_OFFS);
smi_reg &= ~MVNETA_SMI_OPCODE_READ;
/* write the smi register */
return 0;
}
-static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis)
+static int mvneta_start(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct phy_device *phydev;
mvneta_port_power_up(pp, pp->phy_interface);
}
/* Full init on first call */
- mvneta_probe(dev);
+ mvneta_init(dev);
pp->init = 1;
} else {
/* Upon all following calls, this is enough */
return 0;
}
-static int mvneta_send(struct eth_device *dev, void *ptr, int len)
+static int mvneta_send(struct udevice *dev, void *packet, int length)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct mvneta_tx_queue *txq = &pp->txqs[0];
struct mvneta_tx_desc *tx_desc;
int sent_desc;
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
- tx_desc->buf_phys_addr = (u32)ptr;
- tx_desc->data_size = len;
- flush_dcache_range((u32)ptr, (u32)ptr + len);
+ tx_desc->buf_phys_addr = (u32)packet;
+ tx_desc->data_size = length;
+ flush_dcache_range((u32)packet, (u32)packet + length);
/* First and Last descriptor */
tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
/* txDone has increased - hw sent packet */
mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
- return 0;
return 0;
}
-static int mvneta_recv(struct eth_device *dev)
+static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
int rx_done;
- int packets_done;
struct mvneta_rx_queue *rxq;
+ int rx_bytes = 0;
/* get rx queue */
rxq = mvneta_rxq_handle_get(pp, rxq_def);
rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
- packets_done = rx_done;
- while (packets_done--) {
+ if (rx_done) {
struct mvneta_rx_desc *rx_desc;
unsigned char *data;
u32 rx_status;
- int rx_bytes;
/*
* No cache invalidation needed here, since the desc's are
(rx_status & MVNETA_RXD_ERR_SUMMARY)) {
mvneta_rx_error(pp, rx_desc);
/* leave the descriptor untouched */
- continue;
+ return -EIO;
}
/* 2 bytes for marvell header. 4 bytes for crc */
* No cache invalidation needed here, since the rx_buffer's are
* located in a uncached memory region
*/
- net_process_received_packet(data, rx_bytes);
- }
+ *packetp = data;
- /* Update rxq management counters */
- if (rx_done)
mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+ }
- return 0;
-}
-
-static void mvneta_halt(struct eth_device *dev)
-{
- struct mvneta_port *pp = dev->priv;
-
- mvneta_port_down(pp);
- mvneta_port_disable(pp);
+ return rx_bytes;
}
-int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr)
+static int mvneta_probe(struct udevice *dev)
{
- struct eth_device *dev;
- struct mvneta_port *pp;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvneta_port *pp = dev_get_priv(dev);
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ struct mii_dev *bus;
+ unsigned long addr;
void *bd_space;
- dev = calloc(1, sizeof(*dev));
- if (dev == NULL)
- return -ENOMEM;
-
- pp = calloc(1, sizeof(*pp));
- if (pp == NULL)
- return -ENOMEM;
-
- dev->priv = pp;
-
/*
* Allocate buffer area for descs and rx_buffers. This is only
* done once for all interfaces. As only one interface can
MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
}
- sprintf(dev->name, "neta%d", devnum);
+ pp->base = (void __iomem *)pdata->iobase;
- pp->base = (void __iomem *)base_addr;
- dev->iobase = base_addr;
- dev->init = mvneta_init_u_boot;
- dev->halt = mvneta_halt;
- dev->send = mvneta_send;
- dev->recv = mvneta_recv;
- dev->write_hwaddr = NULL;
+ /* Configure MBUS address windows */
+ mvneta_conf_mbus_windows(pp);
- /*
- * The PHY interface type is configured via the
- * board specific CONFIG_SYS_NETA_INTERFACE_TYPE
- * define.
- */
- pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE;
+ /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
+ pp->phy_interface = pdata->phy_interface;
+
+ /* Now read phyaddr from DT */
+ addr = fdtdec_get_int(blob, node, "phy", 0);
+ addr = fdt_node_offset_by_phandle(blob, addr);
+ pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mvneta_mdio_read;
+ bus->write = mvneta_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)pp;
+ pp->bus = bus;
- eth_register(dev);
+ return mdio_register(bus);
+}
- pp->phyaddr = phy_addr;
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
- pp->bus = miiphy_get_dev_by_name(dev->name);
+static void mvneta_stop(struct udevice *dev)
+{
+ struct mvneta_port *pp = dev_get_priv(dev);
- return 1;
+ mvneta_port_down(pp);
+ mvneta_port_disable(pp);
}
+
+static const struct eth_ops mvneta_ops = {
+ .start = mvneta_start,
+ .send = mvneta_send,
+ .recv = mvneta_recv,
+ .stop = mvneta_stop,
+};
+
+static int mvneta_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const char *phy_mode;
+
+ pdata->iobase = dev_get_addr(dev);
+
+ /* Get phy-mode / phy_interface from DT */
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mvneta_ids[] = {
+ { .compatible = "marvell,armada-370-neta" },
+ { .compatible = "marvell,armada-xp-neta" },
+ { }
+};
+
+U_BOOT_DRIVER(mvneta) = {
+ .name = "mvneta",
+ .id = UCLASS_ETH,
+ .of_match = mvneta_ids,
+ .ofdata_to_platdata = mvneta_ofdata_to_platdata,
+ .probe = mvneta_probe,
+ .ops = &mvneta_ops,
+ .priv_auto_alloc_size = sizeof(struct mvneta_port),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
dev->send = ne2k_send;
dev->recv = ne2k_recv;
- sprintf(dev->name, "NE2000");
+ strcpy(dev->name, "NE2000");
return eth_register(dev);
}
bus->read = pch_gbe_mdio_read;
bus->write = pch_gbe_mdio_write;
- sprintf(bus->name, name);
+ strcpy(bus->name, name);
bus->priv = (void *)mac_regs;
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
-#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
-#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
+static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
+ void *addr, bool uncached)
+{
+ pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+ void *virt_addr = addr;
+
+ if (uncached)
+ virt_addr = (void *)CKSEG0ADDR(addr);
+
+ return pci_virt_to_mem(devbusfn, virt_addr);
+}
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]);
+ addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+ uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
- uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
+ addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+ uc->init_block.rx_ring = cpu_to_le32(addr);
+ addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+ uc->init_block.tx_ring = cpu_to_le32(addr);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
uc->init_block.tlen_rlen,
* Tell the controller where the Init Block is located.
*/
barrier();
- addr = PCI_TO_MEM(dev, &lp->uc->init_block);
+ addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
pcnet_write_csr(dev, 1, addr & 0xffff);
pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
int i, status;
+ u32 addr;
struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
+ addr = pcnet_virt_to_mem(dev, packet, false);
writew(-pkt_len, &entry->length);
writel(0, &entry->misc);
- writel(PCI_TO_MEM(dev, packet), &entry->base);
+ writel(addr, &entry->base);
writew(0x8300, &entry->status);
/* Trigger an immediate send poll. */
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
dev->recv = sh_eth_recv;
eth->port_info[eth->port].dev = dev;
- sprintf(dev->name, SHETHER_NAME);
+ strcpy(dev->name, SHETHER_NAME);
/* Register Device to EtherNet subsystem */
eth_register(dev);
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
- sprintf(dev->name, tsec_info->devname);
+ strcpy(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
dev->iobase = 0;
case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
debug("PCI AutoConfig: Found PowerPC device\n");
+ /* fall through */
default:
dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
bar_res = prefetch;
else
bar_res = mem;
-#endif
debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
bar_nr, bar_res == prefetch ? "Prf" : "Mem",
(unsigned long long)bar_size);
+#endif
}
#ifndef CONFIG_PCI_ENUM_ONLY
}
#endif
+static int mvebu_pex_unit_is_x4(int pex_idx)
+{
+ int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
+ u32 mask = (0x0f << (pex_unit * 8));
+
+ return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
+}
+
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
{
u32 val;
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
bus = hose->last_busno + 1;
+
+ /* need to skip more for X4 links, otherwise scan will hang */
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ if (mvebu_pex_unit_is_x4(i))
+ i += 3;
+ }
}
}
return 0;
}
-int pci_rom_load(struct pci_rom_header *rom_header,
- struct pci_rom_header **ram_headerp)
+/**
+ * pci_rom_load() - Load a ROM image and return a pointer to it
+ *
+ * @rom_header: Pointer to ROM image
+ * @ram_headerp: Returns a pointer to the image in RAM
+ * @allocedp: Returns true if @ram_headerp was allocated and needs
+ * to be freed
+ * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
+ * the error state. Even if this function returns an error, it may have
+ * allocated memory.
+ */
+static int pci_rom_load(struct pci_rom_header *rom_header,
+ struct pci_rom_header **ram_headerp, bool *allocedp)
{
struct pci_rom_data *rom_data;
unsigned int rom_size;
unsigned int image_size = 0;
void *target;
+ *allocedp = false;
do {
/* Get next image, until we see an x86 version */
rom_header = (struct pci_rom_header *)((void *)rom_header +
target = (void *)malloc(rom_size);
if (!target)
return -ENOMEM;
+ *allocedp = true;
#endif
if (target != rom_header) {
ulong start = get_timer(0);
int exec_method)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
- struct pci_rom_header *rom, *ram;
+ struct pci_rom_header *rom, *ram = NULL;
int vesa_mode = -1;
- bool emulate;
+ bool emulate, alloced;
int ret;
/* Only execute VGA ROMs */
if (ret)
return ret;
- ret = pci_rom_load(rom, &ram);
+ ret = pci_rom_load(rom, &ram, &alloced);
if (ret)
- return ret;
+ goto err;
- if (!board_should_run_oprom(dev))
- return -ENXIO;
+ if (!board_should_run_oprom(dev)) {
+ ret = -ENXIO;
+ goto err;
+ }
#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
defined(CONFIG_FRAMEBUFFER_VESA_MODE)
#else
if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
printf("BIOS native execution is only available on x86\n");
- return -ENOSYS;
+ ret = -ENOSYS;
+ goto err;
}
emulate = true;
#endif
#else
if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
- return -ENOSYS;
+ ret = -ENOSYS;
+ goto err;
}
emulate = false;
#endif
ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
if (ret)
- return ret;
+ goto err;
biosemu_set_interrupt_handler(0x15, int15_handler);
ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
info, true, vesa_mode, &mode_info);
if (ret)
- return ret;
+ goto err;
#endif
} else {
#ifdef CONFIG_X86
#endif
}
debug("Final vesa mode %#x\n", mode_info.video_mode);
+ ret = 0;
- return 0;
+err:
+ if (alloced)
+ free(ram);
+ return ret;
}
switch (on_off) {
case OPMODE_OFF:
- *enable = 0;
+ *enable = false;
break;
case OPMODE_ON:
- *enable = 1;
+ *enable = true;
break;
default:
return -EINVAL;
}
} else if (op == PMIC_OP_SET) {
- switch (*enable) {
- case 0:
- on_off = OPMODE_OFF;
- break;
- case 1:
+ if (*enable)
on_off = OPMODE_ON;
- break;
- default:
- return -EINVAL;
- }
+ else
+ on_off = OPMODE_OFF;
ret = max77686_ldo_mode(dev, op, &on_off);
if (ret)
return -EINVAL;
}
} else if (op == PMIC_OP_SET) {
- switch (*enable) {
- case 0:
- on_off = OPMODE_OFF;
- break;
- case 1:
+ if (*enable)
on_off = OPMODE_ON;
- break;
- default:
- return -EINVAL;
- }
+ else
+ on_off = OPMODE_OFF;
ret = max77686_buck_mode(dev, op, &on_off);
if (ret)
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_PL010
+ bool "pl010"
+ help
+ Select this to enable a debug UART using the pl01x driver with the
+ PL010 UART type. You will need to provide parameters to make this
+ work. The driver will be available until the real driver model
+ serial is running.
+
+config DEBUG_UART_PL011
+ bool "pl011"
+ help
+ Select this to enable a debug UART using the pl01x driver with the
+ PL011 UART type. You will need to provide parameters to make this
+ work. The driver will be available until the real driver model
+ serial is running.
+
endchoice
config DEBUG_UART_BASE
debug_uart_init()). This can be useful just as a check that
everything is working.
+config DEBUG_UART_SKIP_INIT
+ bool "Skip UART initialization"
+ help
+ Select this if the UART you want to use for debug output is already
+ initialized by the time U-Boot starts its execution.
+
config ALTERA_JTAG_UART
bool "Altera JTAG UART support"
depends on DM_SERIAL
* Copyright (C) 2004-2007 ARM Limited.
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*
* As a special exception, if other files instantiate templates or use macros
* or inline functions from this file, or you compile this file and link it
/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
+#include <dm.h>
#include <serial.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
+#include <asm/arch/uart.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
+struct lpc32xx_hsuart_priv {
+ struct hsuart_regs *hsuart;
+};
-static void lpc32xx_serial_setbrg(void)
+static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
{
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
u32 div;
/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
- div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
+ div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
if (div > 255)
div = 255;
writel(div, &hsuart->rate);
+
+ return 0;
}
-static int lpc32xx_serial_getc(void)
+static int lpc32xx_serial_getc(struct udevice *dev)
{
- while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
- /* NOP */;
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
+ return -EAGAIN;
return readl(&hsuart->rx) & HSUART_RX_DATA;
}
-static void lpc32xx_serial_putc(const char c)
+static int lpc32xx_serial_putc(struct udevice *dev, const char c)
{
- if (c == '\n')
- serial_putc('\r');
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ /* Wait for empty FIFO */
+ if (readl(&hsuart->level) & HSUART_LEVEL_TX)
+ return -EAGAIN;
writel(c, &hsuart->tx);
- /* Wait for character to be sent */
- while (readl(&hsuart->level) & HSUART_LEVEL_TX)
- /* NOP */;
+ return 0;
}
-static int lpc32xx_serial_tstc(void)
+static int lpc32xx_serial_pending(struct udevice *dev, bool input)
{
- if (readl(&hsuart->level) & HSUART_LEVEL_RX)
- return 1;
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ if (input) {
+ if (readl(&hsuart->level) & HSUART_LEVEL_RX)
+ return 1;
+ } else {
+ if (readl(&hsuart->level) & HSUART_LEVEL_TX)
+ return 1;
+ }
return 0;
}
-static int lpc32xx_serial_init(void)
+static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
{
- lpc32xx_serial_setbrg();
-
/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
&hsuart->ctrl);
+
return 0;
}
-static struct serial_device lpc32xx_serial_drv = {
- .name = "lpc32xx_serial",
- .start = lpc32xx_serial_init,
- .stop = NULL,
+static int lpc32xx_hsuart_probe(struct udevice *dev)
+{
+ struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+
+ priv->hsuart = (struct hsuart_regs *)platdata->base;
+
+ lpc32xx_serial_init(priv->hsuart);
+
+ return 0;
+}
+
+static const struct dm_serial_ops lpc32xx_hsuart_ops = {
.setbrg = lpc32xx_serial_setbrg,
- .putc = lpc32xx_serial_putc,
- .puts = default_serial_puts,
.getc = lpc32xx_serial_getc,
- .tstc = lpc32xx_serial_tstc,
+ .putc = lpc32xx_serial_putc,
+ .pending = lpc32xx_serial_pending,
};
-void lpc32xx_serial_initialize(void)
-{
- serial_register(&lpc32xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &lpc32xx_serial_drv;
-}
+U_BOOT_DRIVER(lpc32xx_hsuart) = {
+ .name = "lpc32xx_hsuart",
+ .id = UCLASS_SERIAL,
+ .probe = lpc32xx_hsuart_probe,
+ .ops = &lpc32xx_hsuart_ops,
+ .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
};
#endif
+
+#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
+
+#include <debug_uart.h>
+
+static void _debug_uart_init(void)
+{
+#ifndef CONFIG_DEBUG_UART_SKIP_INIT
+ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
+ enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
+ TYPE_PL011 : TYPE_PL010;
+
+ pl01x_generic_serial_init(regs, type);
+ pl01x_generic_setbrg(regs, type,
+ CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+#endif
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
+
+ pl01x_putc(regs, ch);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
* and byte program command for SST flash
*/
if (plat->ich_version == 7) {
- slave->op_mode_rx = SPI_OPM_RX_AS;
- slave->op_mode_tx = SPI_OPM_TX_BP;
+ slave->mode_rx = SPI_RX_SLOW;
+ slave->mode = SPI_TX_BYTE;
}
return 0;
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#endif
#include <asm/arch-mvebu/spi.h>
+static void _spi_cs_activate(struct kwspi_registers *reg)
+{
+ setbits_le32(®->ctrl, KWSPI_CSN_ACT);
+}
+
+static void _spi_cs_deactivate(struct kwspi_registers *reg)
+{
+ clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
+}
+
+static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ unsigned int tmpdout, tmpdin;
+ int tm, isread = 0;
+
+ debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
+
+ if (flags & SPI_XFER_BEGIN)
+ _spi_cs_activate(reg);
+
+ /*
+ * handle data in 8-bit chunks
+ * TBD: 2byte xfer mode to be enabled
+ */
+ clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
+
+ while (bitlen > 4) {
+ debug("loopstart bitlen %d\n", bitlen);
+ tmpdout = 0;
+
+ /* Shift data so it's msb-justified */
+ if (dout)
+ tmpdout = *(u32 *)dout & 0xff;
+
+ clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
+ writel(tmpdout, ®->dout); /* Write the data out */
+ debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+ tmpdout, bitlen);
+
+ /*
+ * Wait for SPI transmit to get out
+ * or time out (1 second = 1000 ms)
+ * The NE event must be read and cleared first
+ */
+ for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
+ if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
+ isread = 1;
+ tmpdin = readl(®->din);
+ debug("spi_xfer: din %p..%08x read\n",
+ din, tmpdin);
+
+ if (din) {
+ *((u8 *)din) = (u8)tmpdin;
+ din += 1;
+ }
+ if (dout)
+ dout += 1;
+ bitlen -= 8;
+ }
+ if (isread)
+ break;
+ }
+ if (tm >= KWSPI_TIMEOUT)
+ printf("*** spi_xfer: Time out during SPI transfer\n");
+
+ debug("loopend bitlen %d\n", bitlen);
+ }
+
+ if (flags & SPI_XFER_END)
+ _spi_cs_deactivate(reg);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+
static struct kwspi_registers *spireg =
(struct kwspi_registers *)MVEBU_SPI_BASE;
void spi_cs_activate(struct spi_slave *slave)
{
- setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
+ _spi_cs_activate(spireg);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
+ _spi_cs_deactivate(spireg);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- unsigned int tmpdout, tmpdin;
- int tm, isread = 0;
+ return _spi_xfer(spireg, bitlen, dout, din, flags);
+}
- debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
- slave->bus, slave->cs, dout, din, bitlen);
+#else
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+/* Here now the DM part */
- /*
- * handle data in 8-bit chunks
- * TBD: 2byte xfer mode to be enabled
- */
- clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
+struct mvebu_spi_platdata {
+ struct kwspi_registers *spireg;
+};
- while (bitlen > 4) {
- debug("loopstart bitlen %d\n", bitlen);
- tmpdout = 0;
+struct mvebu_spi_priv {
+ struct kwspi_registers *spireg;
+};
- /* Shift data so it's msb-justified */
- if (dout)
- tmpdout = *(u32 *)dout & 0xff;
+static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data;
- clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ);
- writel(tmpdout, &spireg->dout); /* Write the data out */
- debug("*** spi_xfer: ... %08x written, bitlen %d\n",
- tmpdout, bitlen);
+ /* calculate spi clock prescaller using max_hz */
+ data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
+ data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
+ data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
- /*
- * Wait for SPI transmit to get out
- * or time out (1 second = 1000 ms)
- * The NE event must be read and cleared first
- */
- for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
- if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
- isread = 1;
- tmpdin = readl(&spireg->din);
- debug("spi_xfer: din %p..%08x read\n",
- din, tmpdin);
+ /* program spi clock prescaler using max_hz */
+ writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
+ debug("data = 0x%08x\n", data);
- if (din) {
- *((u8 *)din) = (u8)tmpdin;
- din += 1;
- }
- if (dout)
- dout += 1;
- bitlen -= 8;
- }
- if (isread)
- break;
- }
- if (tm >= KWSPI_TIMEOUT)
- printf("*** spi_xfer: Time out during SPI transfer\n");
+ return 0;
+}
- debug("loopend bitlen %d\n", bitlen);
- }
+static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
+}
+
+static int mvebu_spi_probe(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+
+ writel(KWSPI_SMEMRDY, ®->ctrl);
+ writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
+ writel(KWSPI_IRQMASK, ®->irq_mask);
+
+ return 0;
+}
+
+static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
return 0;
}
+
+static const struct dm_spi_ops mvebu_spi_ops = {
+ .xfer = mvebu_spi_xfer,
+ .set_speed = mvebu_spi_set_speed,
+ .set_mode = mvebu_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mvebu_spi_ids[] = {
+ { .compatible = "marvell,armada-380-spi" },
+ { .compatible = "marvell,armada-xp-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mvebu_spi) = {
+ .name = "mvebu_spi",
+ .id = UCLASS_SPI,
+ .of_match = mvebu_spi_ids,
+ .ops = &mvebu_spi_ops,
+ .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
+ .probe = mvebu_spi_probe,
+};
+#endif
50000000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
- debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ debug("%s: base=%lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
*
* Copyright (C) 2011-2012 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __SH_SPI_H__
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
+ slave->mode_rx = plat->mode_rx;
return 0;
}
int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat)
{
- int mode = 0;
+ int mode = 0, mode_rx = 0;
+ int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
mode |= SPI_3WIRE;
if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
+
+ /* Device DUAL/QUAD mode */
+ value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_TX_QUAD;
+ break;
+ default:
+ error("spi-tx-bus-width %d not supported\n", value);
+ break;
+ }
+
plat->mode = mode;
+ value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode_rx |= SPI_RX_DUAL;
+ break;
+ case 4:
+ mode_rx |= SPI_RX_QUAD;
+ break;
+ default:
+ error("spi-rx-bus-width %d not supported\n", value);
+ break;
+ }
+
+ plat->mode_rx = mode_rx;
+
return 0;
}
*
* Copyright (c) 2010-2013 NVIDIA Corporation
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
*
* Copyright (c) 2010-2013 NVIDIA Corporation
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE QSPI_WC
#define MM_SWITCH 0x01
-#define MEM_CS 0x100
+#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff0ff
#define MMAP_START_ADDR_DRA 0x5c000000
#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
-#define QSPI_CMD_READ_QUAD (0x6b << 0)
+#define QSPI_CMD_READ_DUAL (0x6b << 0)
+#define QSPI_CMD_READ_QUAD (0x6c << 0)
#define QSPI_CMD_READ_FAST (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
+#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
+#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
-#define QSPI_CMD_WRITE (0x2 << 16)
+#define QSPI_CMD_WRITE (0x12 << 16)
#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
/* ti qspi register set */
u32 data3;
};
-/* ti qspi slave */
-struct ti_qspi_slave {
+/* ti qspi priv */
+struct ti_qspi_priv {
+#ifndef CONFIG_DM_SPI
struct spi_slave slave;
+#else
+ void *memory_map;
+ uint max_hz;
+ u32 num_cs;
+#endif
struct ti_qspi_regs *base;
+ void *ctrl_mod_mmap;
unsigned int mode;
u32 cmd;
u32 dc;
};
-static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct ti_qspi_slave, slave);
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
- struct spi_slave *slave = &qslave->slave;
- u32 memval = 0;
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- slave->memory_map = (void *)MMAP_START_ADDR_DRA;
-#else
- slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
-#endif
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
- memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_8_BITS |
- QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS);
- slave->op_mode_rx = SPI_OPM_RX_QOF;
-#else
- memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
- QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS;
-#endif
-
- writel(memval, &qslave->base->setup0);
-}
-
-static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint clk_div;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
clk_div = (QSPI_FCLK / hz) - 1;
/* disable SCLK */
- writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
- &qslave->base->clk_ctrl);
+ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
+ &priv->base->clk_ctrl);
/* assign clk_div values */
if (clk_div < 0)
clk_div = QSPI_CLK_DIV_MAX;
/* enable SCLK */
- writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
+ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}
-void spi_cs_activate(struct spi_slave *slave)
+static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
- /* CS handled in xfer */
- return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
-
- writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+ writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
/* dummy readl to ensure bus sync */
- readl(&qslave->base->cmd);
+ readl(&priv->base->cmd);
}
-void spi_init(void)
+static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
- /* nothing to do */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ti_qspi_slave *qslave;
-
-#ifdef CONFIG_AM43XX
- gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
- gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
- qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
- if (!qslave) {
- printf("SPI_error: Fail to allocate ti_qspi_slave\n");
- return NULL;
- }
-
- qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
- qslave->mode = mode;
-
- ti_spi_set_speed(&qslave->slave, max_hz);
+ priv->dc = 0;
+ if (mode & SPI_CPHA)
+ priv->dc |= QSPI_CKPHA(0);
+ if (mode & SPI_CPOL)
+ priv->dc |= QSPI_CKPOL(0);
+ if (mode & SPI_CS_HIGH)
+ priv->dc |= QSPI_CSPOL(0);
-#ifdef CONFIG_TI_SPI_MMAP
- ti_spi_setup_spi_register(qslave);
-#endif
-
- return &qslave->slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
- free(qslave);
-}
+ writel(priv->dc, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
-
- qslave->dc = 0;
- if (qslave->mode & SPI_CPHA)
- qslave->dc |= QSPI_CKPHA(slave->cs);
- if (qslave->mode & SPI_CPOL)
- qslave->dc |= QSPI_CKPOL(slave->cs);
- if (qslave->mode & SPI_CS_HIGH)
- qslave->dc |= QSPI_CSPOL(slave->cs);
-
- writel(qslave->dc, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ priv->dc <<= cs * 8;
+ writel(priv->dc, &priv->base->dc);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ writel(0, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
+}
- debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
+static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
+{
+ u32 val;
- writel(0, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ val = readl(ctrl_mod_mmap);
+ if (enable)
+ val |= MEM_CS(cs);
+ else
+ val &= MEM_CS_UNSELECT;
+ writel(val, ctrl_mod_mmap);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags,
+ u32 cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout;
uchar *rxp = din;
uint status;
int timeout;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- int val;
-#endif
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
- slave->bus, slave->cs, bitlen, words, flags);
-
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val |= MEM_CS;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val &= MEM_CS_UNSELECT;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(~MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
return 0;
}
}
/* Setup command reg */
- qslave->cmd = 0;
- qslave->cmd |= QSPI_WLEN(8);
- qslave->cmd |= QSPI_EN_CS(slave->cs);
- if (qslave->mode & SPI_3WIRE)
- qslave->cmd |= QSPI_3_PIN;
- qslave->cmd |= 0xfff;
+ priv->cmd = 0;
+ priv->cmd |= QSPI_WLEN(8);
+ priv->cmd |= QSPI_EN_CS(cs);
+ if (priv->mode & SPI_3WIRE)
+ priv->cmd |= QSPI_3_PIN;
+ priv->cmd |= 0xfff;
/* FIXME: This delay is required for successfull
* completion of read/write/erase. Once its root
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
- qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
- writel(*txp++, &qslave->base->data);
- writel(qslave->cmd | QSPI_WR_SNGL,
- &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
+ writel(*txp++, &priv->base->data);
+ writel(priv->cmd | QSPI_WR_SNGL,
+ &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: TX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
debug("tx done, status %08x\n", status);
}
if (rxp) {
- qslave->cmd |= QSPI_RD_SNGL;
+ priv->cmd |= QSPI_RD_SNGL;
debug("rx cmd %08x dc %08x\n",
- qslave->cmd, qslave->dc);
+ priv->cmd, priv->dc);
#ifdef CONFIG_DRA7XX
udelay(500);
#endif
- writel(qslave->cmd, &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ writel(priv->cmd, &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: RX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
- *rxp++ = readl(&qslave->base->data);
+ *rxp++ = readl(&priv->base->data);
debug("rx done, status %08x, read %02x\n",
status, *(rxp-1));
}
/* Terminate frame */
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ ti_qspi_cs_deactivate(priv);
return 0;
}
*((unsigned int *)offset) += len;
}
#endif
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_priv, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ ti_qspi_cs_deactivate(priv);
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
+{
+ u32 memval = 0;
+
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+ struct spi_slave *slave = &priv->slave;
+ memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+ QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS);
+ slave->mode_rx = SPI_RX_QUAD;
+#else
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+ QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS;
+#endif
+
+ writel(memval, &priv->base->setup0);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct ti_qspi_priv *priv;
+
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
+ priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
+ if (!priv) {
+ printf("SPI_error: Fail to allocate ti_qspi_priv\n");
+ return NULL;
+ }
+
+ priv->base = (struct ti_qspi_regs *)QSPI_BASE;
+ priv->mode = mode;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
+
+ ti_spi_set_speed(priv, max_hz);
+
+#ifdef CONFIG_TI_SPI_MMAP
+ ti_spi_setup_spi_register(priv);
+#endif
+
+ return &priv->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_set_mode(priv, priv->mode);
+ return __ti_qspi_claim_bus(priv, priv->slave.cs);
+}
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_release_bus(priv);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
+ priv->slave.bus, priv->slave.cs, bitlen, flags);
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+}
+
+#else /* CONFIG_DM_SPI */
+
+static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
+ struct spi_slave *slave,
+ bool enable)
+{
+ u32 memval;
+ u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
+
+ if (!enable) {
+ writel(0, &priv->base->setup0);
+ return;
+ }
+
+ memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+
+ switch (mode) {
+ case SPI_RX_QUAD:
+ memval |= QSPI_CMD_READ_QUAD;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_QUAD;
+ slave->mode_rx = SPI_RX_QUAD;
+ break;
+ case SPI_RX_DUAL:
+ memval |= QSPI_CMD_READ_DUAL;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_DUAL;
+ break;
+ default:
+ memval |= QSPI_CMD_READ;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
+ memval |= QSPI_SETUP0_READ_NORMAL;
+ break;
+ }
+
+ writel(memval, &priv->base->setup0);
+}
+
+
+static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ ti_spi_set_speed(priv, max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ return __ti_qspi_set_mode(priv, mode);
+}
+
+static int ti_qspi_claim_bus(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave_plat->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ __ti_qspi_setup_memorymap(priv, slave, true);
+
+ return __ti_qspi_claim_bus(priv, slave_plat->cs);
+}
+
+static int ti_qspi_release_bus(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ __ti_qspi_setup_memorymap(priv, slave, false);
+ __ti_qspi_release_bus(priv);
+
+ return 0;
+}
+
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+}
+
+static int ti_qspi_probe(struct udevice *bus)
+{
+ /* Nothing to do in probe */
+ return 0;
+}
+
+static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+ fdt_addr_t addr;
+
+ priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
+ priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+ addr = dev_get_addr_index(bus, 2);
+ priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+
+ priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
+ if (priv->max_hz < 0) {
+ debug("Error: Max frequency missing\n");
+ return -ENODEV;
+ }
+ priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
+ debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
+ (int)priv->base, priv->max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_child_pre_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ slave->memory_map = priv->memory_map;
+ return 0;
+}
+
+static const struct dm_spi_ops ti_qspi_ops = {
+ .claim_bus = ti_qspi_claim_bus,
+ .release_bus = ti_qspi_release_bus,
+ .xfer = ti_qspi_xfer,
+ .set_speed = ti_qspi_set_speed,
+ .set_mode = ti_qspi_set_mode,
+};
+
+static const struct udevice_id ti_qspi_ids[] = {
+ { .compatible = "ti,dra7xxx-qspi" },
+ { .compatible = "ti,am4372-qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(ti_qspi) = {
+ .name = "ti_qspi",
+ .id = UCLASS_SPI,
+ .of_match = ti_qspi_ids,
+ .ops = &ti_qspi_ops,
+ .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
+ .probe = ti_qspi_probe,
+ .child_pre_probe = ti_qspi_child_pre_probe,
+};
+#endif /* CONFIG_DM_SPI */
* Copyright (C) 2005 by Ivan Kokshaysky
* Copyright (C) 2006 by SAN People
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91_UDC_H
return ret;
ret = ci_udc_probe();
-#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS)
- /*
- * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all
- * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection
- */
- if (!ret) {
- struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
-
- /* select ULPI phy */
- writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
+ if (ret) {
+ DBG("udc probe failed, returned %d\n", ret);
+ return ret;
}
-#endif
ret = driver->bind(&controller.gadget);
if (ret) {
req->complete = rx_handler_command;
req->length = EP_BUFFER_SIZE;
- sprintf(response, "OKAY");
+ strcpy(response, "OKAY");
fastboot_tx_write_str(response);
printf("\ndownloading of %d bytes finished\n", download_bytes);
printf("Starting download of %d bytes\n", download_size);
if (0 == download_size) {
- sprintf(response, "FAILdata invalid size");
+ strcpy(response, "FAILdata invalid size");
} else if (download_size > CONFIG_FASTBOOT_BUF_SIZE) {
download_size = 0;
- sprintf(response, "FAILdata too large");
+ strcpy(response, "FAILdata too large");
} else {
sprintf(response, "DATA%08x", download_size);
req->complete = rx_handler_dl_image;
/*-------------------------------------------------------------------------*/
-struct ums *ums;
-struct fsg_common *the_fsg_common;
+static struct ums *ums;
+static int ums_count;
+static struct fsg_common *the_fsg_common;
static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
{
}
/* Perform the read */
- rc = ums->read_sector(ums,
+ rc = ums[common->lun].read_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
amount = bh->outreq->actual;
/* Perform the write */
- rc = ums->write_sector(ums,
+ rc = ums[common->lun].write_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
}
/* Perform the read */
- rc = ums->read_sector(ums,
+ rc = ums[common->lun].read_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
buf[4] = 31; /* Additional length */
/* No special options */
sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id ,
- ums->name, (u16) 0xffff);
+ ums[common->lun].name, (u16) 0xffff);
return 36;
}
int nluns, i, rc;
/* Find out how many LUNs there should be */
- nluns = 1;
+ nluns = ums_count;
if (nluns < 1 || nluns > FSG_MAX_LUNS) {
printf("invalid number of LUNs: %u\n", nluns);
return ERR_PTR(-EINVAL);
for (i = 0; i < nluns; i++) {
common->luns[i].removable = 1;
- rc = fsg_lun_open(&common->luns[i], "");
+ rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, "");
if (rc)
goto error_luns;
}
return fsg_bind_config(c->cdev, c, fsg_common);
}
-int fsg_init(struct ums *ums_dev)
+int fsg_init(struct ums *ums_devs, int count)
{
- ums = ums_dev;
+ ums = ums_devs;
+ ums_count = count;
return 0;
}
* Authors: Benedikt Spranger, Pengutronix
* Robert Schwebel, Pengutronix
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2, as published by the Free Software Foundation.
- *
* This software was originally developed in conformance with
* Microsoft's Remote NDIS Specification License Agreement.
*
*
* Copyright (C) 2004 by David Brownell
* updates to merge with Linux 2.6, better match RNDIS spec
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* Authors: Benedikt Spranger, Pengutronix
* Robert Schwebel, Pengutronix
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2, as published by the Free Software Foundation.
- *
* This software was originally developed in conformance with
* Microsoft's Remote NDIS Specification License Agreement.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _USBGADGET_RNDIS_H
* the caller must own fsg->filesem for writing.
*/
-static int fsg_lun_open(struct fsg_lun *curlun, const char *filename)
+static int fsg_lun_open(struct fsg_lun *curlun, unsigned int num_sectors,
+ const char *filename)
{
int ro;
ro = curlun->initially_ro;
curlun->ro = ro;
- curlun->file_length = ums->num_sectors << 9;
- curlun->num_sectors = ums->num_sectors;
+ curlun->file_length = num_sectors << 9;
+ curlun->num_sectors = num_sectors;
debug("open backing file: %s\n", filename);
return 0;
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
}
+int __weak board_usb_phy_mode(int port)
+{
+ return 0;
+}
+
int __weak board_ehci_hcd_init(int port)
{
return 0;
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
+ enum usb_init_type type;
if (index >= ARRAY_SIZE(nc_reg_bases))
return -EINVAL;
- if (init == USB_INIT_DEVICE && index == 1)
- return -ENODEV;
- if (init == USB_INIT_HOST && index == 0)
- return -ENODEV;
-
ehci = (struct usb_ehci *)nc_reg_bases[index];
/* Do board specific initialisation */
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ type = board_usb_phy_mode(index);
+ if (type != init)
+ return -ENODEV;
+
if (init == USB_INIT_DEVICE) {
setbits_le32(&ehci->usbmode, CM_DEVICE);
writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*
*/
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_CORE_H__
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_LINUX_DEBUG_H__
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_DMA_H__
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*
* musb_dsps.c will be a common file for all the TI DSPS platforms
* such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
* Copyright (C) 2006-2007 Nokia Corporation
* Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_GADGET_H
* Copyright (C) 2006-2007 Nokia Corporation
* Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
* Copyright (C) 2006-2007 Nokia Corporation
* Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _MUSB_HOST_H
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_LINUX_PLATFORM_ARCH_H__
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_REGS_H__
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
#include <linux/module.h>
/*
* Copyright (C) 2005-2006 by Texas Instruments
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_OMAP243X_H__
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/arch/cpu.h>
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
- *
- * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
- * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
- * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
- * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
- * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
- * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
- * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
- * GRAPHICS SUPPORT CUSTOMER.
+ * SPDX-License-Identifier: GPL-2.0
******************************************************************/
#ifndef __MUSB_HDRC_DEFS_H__
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
* Original Copyright follow:
* Copyright (C) 2011 Google, Inc.
*
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
{
u32 reg;
- /* Set the AC Bias Period and Number of Transisitons per Interrupt */
+ /* Set the AC Bias Period and Number of Transitions per Interrupt */
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
reg |= LCD_AC_BIAS_FREQUENCY(period) |
LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
/* Pixels per line = (PPL + 1)*16 */
if (lcd_revision == LCD_VERSION_1) {
/*
- * 0x3F in bits 4..9 gives max horisontal resolution = 1024
+ * 0x3F in bits 4..9 gives max horizontal resolution = 1024
* pixels
*/
width &= 0x3f0;
lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
- /* Configure for disply */
+ /* Configure for display */
ret = lcd_cfg_display(cfg);
if (ret < 0)
return ret;
lcdc_write(stat, &da8xx_fb_reg_base->stat);
- /* Disable PL completion inerrupt */
+ /* Disable PL completion interrupt */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
reg_ras &= ~LCD_V1_PL_INT_ENA;
lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
- /* Disable PL completion inerrupt */
+ /* Disable PL completion interrupt */
reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
(LCD_V2_PL_INT_ENA);
lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
return -EINVAL;
}
- /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
+ /* Refer VESA Display Port Standard Ver1.1a Page 120 */
if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
return ret;
}
- /* Set link rate and count as you want to establish*/
+ /* Set link rate and count as you want to establish */
exynos_dp_set_link_bandwidth(edp_info->lane_bw);
exynos_dp_set_lane_count(edp_info->lane_cnt);
ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
DPCD_TRAINING_PATTERN_DISABLED);
if (ret != EXYNOS_DP_SUCCESS) {
- printf("DP requst_link_traninig_req failed\n");
+ printf("DP request_link_training_req failed\n");
return -EAGAIN;
}
unsigned int dpcd_addr;
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
- /*lane_num value is used as arry index, so this range 0 ~ 3 */
+ /* lane_num value is used as array index, so this range 0 ~ 3 */
dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
ret = exynos_dp_training_pattern_dis();
if (ret != EXYNOS_DP_SUCCESS) {
- printf("DP training_patter_disable() failed\n");
+ printf("DP training_pattern_disable() failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL;
}
ret = exynos_dp_write_bytes_to_dpcd(
DPCD_TRAINING_PATTERN_SET, 5, buf);
if (ret != EXYNOS_DP_SUCCESS) {
- printf("DP write traning pattern1 failed\n");
+ printf("DP write training pattern1 failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL;
return ret;
} else
ret = exynos_dp_write_bytes_to_dpcd(
DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
if (ret != EXYNOS_DP_SUCCESS) {
- printf("DP write traning pattern2 failed\n");
+ printf("DP write training pattern2 failed\n");
edp_info->lt_info.lt_status = DP_LT_FAIL;
return ret;
}
ret = exynos_dp_sw_link_training(edp_info);
if (ret != EXYNOS_DP_SUCCESS)
- printf("DP dp_sw_link_traning() failed\n");
+ printf("DP dp_sw_link_training() failed\n");
return ret;
}
reg = readl(&dp_regs->video_ctl1);
reg &= ~VIDEO_EN_MASK;
- /* enable video input*/
+ /* enable video input */
if (enable)
reg |= VIDEO_EN_MASK;
void exynos_dp_enable_video_bist(unsigned int enable)
{
- /*enable video bist*/
+ /* enable video bist */
unsigned int reg;
reg = readl(&dp_regs->video_ctl4);
reg &= ~VIDEO_BIST_MASK;
- /*enable video bist*/
+ /* enable video bist */
if (enable)
reg |= VIDEO_BIST_MASK;
/*
* Set AUX TX terminal resistor to 102 ohm
* Set AUX channel amplitude control
- */
+ */
reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
writel(reg, &dp_regs->pll_filter_ctl1);
*/
writel(INT_POL, &dp_regs->int_ctl);
- /* Clear pending regisers */
+ /* Clear pending registers */
writel(0xff, &dp_regs->common_int_sta1);
writel(0xff, &dp_regs->common_int_sta2);
writel(0xff, &dp_regs->common_int_sta3);
{
unsigned int reg_func_1;
- /*dp tx sw reset*/
+ /* dp tx sw reset */
writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
exynos_dp_enable_video_input(DP_DISABLE);
unsigned int retry_cnt = 10;
unsigned int reg;
- /*Power On All Analog block */
+ /* Power On All Analog block */
exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
reg = PLL_LOCK_CHG;
reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
writel(reg, &dp_regs->debug_ctl);
- /*Assert DP PLL Reset*/
+ /* Assert DP PLL Reset */
reg = readl(&dp_regs->pll_ctl);
reg |= DP_PLL_RESET;
writel(reg, &dp_regs->pll_ctl);
mdelay(1);
- /*Deassert DP PLL Reset*/
+ /* Deassert DP PLL Reset */
reg = readl(&dp_regs->pll_ctl);
reg &= ~(DP_PLL_RESET);
writel(reg, &dp_regs->pll_ctl);
{
unsigned int reg;
- /* Clear interrupts releated to Hot Plug Dectect */
+ /* Clear interrupts related to Hot Plug Detect */
reg = HOTPLUG_CHG | HPD_LOST | PLUG;
writel(reg, &dp_regs->common_int_sta4);
{
unsigned int reg;
- /* Clear inerrupts related to AUX channel */
+ /* Clear interrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR;
writel(reg, &dp_regs->int_sta);
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
writel(reg, &dp_regs->aux_hw_retry_ctl);
- /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+ /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
reg = DEFER_CTRL_EN | DEFER_COUNT(1);
writel(reg, &dp_regs->aux_ch_defer_ctl);
reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
writel(reg, &dp_regs->video_ctl10);
- /*Set video mode to slave mode */
+ /* Set video mode to slave mode */
reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
writel(reg, &dp_regs->soc_general_ctl);
}
clean-files := dt.dtb.S
# Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts
if (byte_offset != 0) {
int readlen;
/* read first part which isn't aligned with start of sector */
- if (ext4fs_block_dev_desc->
- block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf(" ** ext2fs_devread() read error **\n");
return 0;
}
ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_block_dev_desc->blksz);
block_len = ext4fs_block_dev_desc->blksz;
- ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
+ ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
part_info->start + sector,
- 1, (unsigned long *)p);
+ 1, (void *)p);
memcpy(buf, p, byte_len);
return 1;
}
- if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector,
- block_len >> log2blksz,
- (unsigned long *) buf) !=
- block_len >> log2blksz) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ block_len >> log2blksz,
+ (void *)buf) !=
+ block_len >> log2blksz) {
printf(" ** %s read error - block\n", __func__);
return 0;
}
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
- if (ext4fs_block_dev_desc->
- block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf("* %s read error - last part\n", __func__);
return 0;
}
if (remainder) {
if (fs->dev_desc->block_read) {
- fs->dev_desc->block_read(fs->dev_desc->dev,
+ fs->dev_desc->block_read(fs->dev_desc,
startblock, 1, sec_buf);
temp_ptr = sec_buf;
memcpy((temp_ptr + remainder),
(unsigned char *)buf, size);
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock, 1, sec_buf);
}
} else {
if (size >> log2blksz != 0) {
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock,
size >> log2blksz,
(unsigned long *)buf);
} else {
- fs->dev_desc->block_read(fs->dev_desc->dev,
+ fs->dev_desc->block_read(fs->dev_desc,
startblock, 1, sec_buf);
temp_ptr = sec_buf;
memcpy(temp_ptr, buf, size);
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock, 1,
(unsigned long *)sec_buf);
}
ti_gp_blockno = ext4fs_get_new_blk_no();
if (ti_gp_blockno == -1) {
printf("no block left to assign\n");
- goto fail;
+ return;
}
ti_gp_buff = zalloc(fs->blksz);
if (!ti_gp_buff)
- goto fail;
+ return;
ti_gp_buff_start_addr = ti_gp_buff;
(*no_blks_reqd)++;
ti_child_blockno = ext4fs_get_new_blk_no();
if (ti_child_blockno == -1) {
printf("no block left assign\n");
- goto fail;
+ goto fail1;
}
ti_child_buff = zalloc(fs->blksz);
if (!ti_child_buff)
- goto fail;
+ goto fail1;
ti_cbuff_start_addr = ti_child_buff;
*ti_parent_buff = ti_child_blockno;
ext4fs_get_new_blk_no();
if (actual_block_no == -1) {
printf("no block left\n");
- goto fail;
+ free(ti_cbuff_start_addr);
+ goto fail1;
}
*ti_child_buff = actual_block_no;
debug("TIAB %ld: %u\n", actual_block_no,
put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
ti_gp_buff_start_addr, fs->blksz);
file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
+ free(ti_gp_buff_start_addr);
+ return;
}
+fail1:
+ free(ti_pbuff_start_addr);
fail:
free(ti_gp_buff_start_addr);
}
if (!cur_dev || !cur_dev->block_read)
return -1;
- ret = cur_dev->block_read(cur_dev->dev,
- cur_part_info.start + block, nr_blocks, buf);
+ ret = cur_dev->block_read(cur_dev, cur_part_info.start + block,
+ nr_blocks, buf);
if (nr_blocks && ret == 0)
return -1;
return -1;
}
- ret = cur_dev->block_write(cur_dev->dev,
- cur_part_info.start + block,
+ ret = cur_dev->block_write(cur_dev, cur_part_info.start + block,
nr_blocks, buf);
if (nr_blocks && ret == 0)
return -1;
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start +
+ sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf (" ** reiserfs_devread() read error\n");
return 0;
}
/* read sector aligned part */
block_len = byte_len & ~(SECTOR_SIZE-1);
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, block_len/SECTOR_SIZE,
- (unsigned long *)buf) != block_len/SECTOR_SIZE) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start + sector,
+ block_len / SECTOR_SIZE,
+ (void *)buf)
+ != block_len/SECTOR_SIZE) {
printf (" ** reiserfs_devread() read error - block\n");
return 0;
}
if ( byte_len != 0 ) {
/* read rest of data which are not in whole sector */
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start +
+ sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf (" ** reiserfs_devread() read error - last part\n");
return 0;
}
* (C) Copyright 2008-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 51
- * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
* Authors: Artem Bityutskiy (Битюцкий Артём)
* Adrian Hunter
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
- if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector, 1,
+ (void *)sec_buf)
+ != 1) {
printf(" ** zfs_devread() read error **\n");
return 1;
}
u8 p[SECTOR_SIZE];
block_len = SECTOR_SIZE;
- zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector,
- 1, (unsigned long *)p);
+ zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)p);
memcpy(buf, p, byte_len);
return 0;
}
- if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, block_len / SECTOR_SIZE,
- (unsigned long *) buf) != block_len / SECTOR_SIZE) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ block_len / SECTOR_SIZE,
+ (void *)buf)
+ != block_len / SECTOR_SIZE) {
printf(" ** zfs_devread() read error - block\n");
return 1;
}
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
- if (zfs_block_dev_desc->
- block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf) != 1) {
printf(" ** zfs_devread() read error - last part\n");
return 1;
}
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <asm/types.h>
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+#ifndef __ATF_H__
+#define __ATF_H__
+#include <cavium/atf_part.h>
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_get_pcount(void);
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index);
+ssize_t atf_erase_nor(uintptr_t offset, size_t size);
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_dram_size(unsigned int node);
+ssize_t atf_node_count(void);
+ssize_t atf_env_count(void);
+ssize_t atf_env_string(size_t index, char *str);
+
+#endif
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#ifndef __ATF_PART_H__
+#define __ATF_PART_H__
+
+struct storage_partition {
+ unsigned int type;
+ unsigned int size;
+ unsigned long offset;
+};
+
+enum {
+ PARTITION_NBL1FW_REST = 0,
+ PARTITION_BL2_BL31 = 1,
+ PARTITION_UBOOT = 2,
+ PARTITION_UEFI = 2,
+ PARTITION_KERNEL = 3,
+ PARTITION_DEVICE_TREE = 4,
+ PARTITION_LAST,
+};
+
+#endif
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#ifndef __THUNDERX_SVC_H__
+#define __THUNDERX_SVC_H__
+
+/* SMC function IDs for general purpose queries */
+
+#define THUNDERX_SVC_CALL_COUNT 0x4300ff00
+#define THUNDERX_SVC_UID 0x4300ff01
+
+#define THUNDERX_SVC_VERSION 0x4300ff03
+
+#define ARM_STD_SVC_VERSION 0x8400ff03
+
+/* ThunderX Service Calls version numbers */
+#define THUNDERX_VERSION_MAJOR 0x0
+#define THUNDERX_VERSION_MINOR 0x1
+
+#define THUNDERX_MMC_READ 0x43000101
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_MMC_WRITE 0x43000102
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+
+#define THUNDERX_NOR_READ 0x43000111
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_WRITE 0x43000112
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_ERASE 0x43000113
+/* x1 - block address
+ */
+
+#define THUNDERX_PART_COUNT 0x43000201
+#define THUNDERX_GET_PART 0x43000202
+/* x1 - pointer to the buffer
+ * x2 - index
+ */
+
+#define THUNDERX_DRAM_SIZE 0x43000301
+/* x1 - node number
+ */
+
+#define THUNDERX_GTI_SYNC 0x43000401
+
+#define THUNDERX_ENV_COUNT 0x43000501
+#define THUNDERX_ENV_STRING 0x43000502
+/* x1 - index
+ */
+
+#define THUNDERX_NODE_COUNT 0x43000601
+
+#endif /* __THUNDERX_SVC_H__ */
char *const argv[]);
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*
* Error codes that commands return to cmd_process(). We use the standard 0
void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
/**
- * board_init_f_mem() - Allocate global data and set stack position
+ * ulong board_init_f_alloc_reserve - allocate reserved area
*
* This function is called by each architecture very early in the start-up
- * code to set up the environment for board_init_f(). It allocates space for
- * global_data (see include/asm-generic/global_data.h) and places the stack
- * below this.
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
*
- * This function requires a stack[1] Normally this is at @top. The function
- * starts allocating space from 64 bytes below @top. First it creates space
- * for global_data. Then it calls arch_setup_gd() which sets gd to point to
- * the global_data space and can reserve additional bytes of space if
- * required). Finally it allocates early malloc() memory
- * (CONFIG_SYS_MALLOC_F_LEN). The new top of the stack is just below this,
- * and it returned by this function.
+ * @top: top of the reserve area, growing down.
+ * @return: bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
*
- * [1] Strictly speaking it would be possible to implement this function
- * in C on many archs such that it does not require a stack. However this
- * does not seem hugely important as only 64 byte are wasted. The 64 bytes
- * are used to handle the calling standard which generally requires pushing
- * addresses or registers onto the stack. We should be able to get away with
- * less if this becomes important.
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
*
- * @top: Top of available memory, also normally the top of the stack
- * @return: New stack location
+ * @base: top from which reservation was done
*/
-ulong board_init_f_mem(ulong top);
+void board_init_f_init_reserve(ulong base);
/**
* arch_setup_gd() - Set up the global_data pointer
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef COMMON_TIMING_PARAMS_H
#endif
#undef CONFIG_DM_WARN
-#undef CONFIG_DM_SEQ_ALIAS
#undef CONFIG_DM_STDIO
#endif /* CONFIG_SPL_BUILD */
#endif
#if defined(CONFIG_SERIAL_BOOT)
-#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
#include <configs/ti_am335x_common.h>
-/* Don't override the distro default bootdelay */
-#undef CONFIG_BOOTDELAY
-#include <config_distro_defaults.h>
-
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_FIT
# define CONFIG_FIT
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
#endif
#ifndef CONFIG_SPL_BUILD
#define CONFIG_HOSTNAME bamboo
#include "amcc-common.h"
+/* Reclaim some space. */
+#undef CONFIG_SYS_LONGHELP
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_CLEARFOG_H
+#define _CONFIG_CLEARFOG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MV_SDHCI
+#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
+
+/* Partition support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_ENV_MIN_ENTRIES 128
+
+/* Environment in MMC */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SECT_SIZE 0x200
+#define CONFIG_ENV_SIZE 0x10000
+/*
+ * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
+ * boot image starts @ LBA-0.
+ * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
+ * image and environment
+ */
+#define CONFIG_ENV_OFFSET 0xf0000
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH 1
+#define SPL_BOOT_SDIO_MMC_CARD 2
+#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\
+ + 1)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
+#endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_CLEARFOG_H */
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
-#define CONFIG_ARMADA_38X
-#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
-#define CONFIG_SYS_L2_PL310
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 1, 0 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+#endif
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
#endif
#endif
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_A38X
-#define CONFIG_DDR3
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* SATA support */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE
-
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
-
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
-
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA_MV
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_EFI_PARTITION
#define CONFIG_DOS_PARTITION
-#endif /* CONFIG_CMD_IDE */
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+#endif
/* NAND */
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e
+#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
#define CONFIG_FLASH_CFI_DRIVER 1
/* The following #defines are needed to get flash environment right */
+/* ROM version */
+#define CONFIG_SYS_TEXT_BASE 0xbfc00000
+/* RAM version */
+/* #define CONFIG_SYS_TEXT_BASE 0x80100000 */
+
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
-#define CONFIG_SYS_TEXT_BASE 0x83FA0000
+#define CONFIG_SYS_TEXT_BASE 0x83F00000
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
#define CONFIG_BAUDRATE 115200
+/*
+ * DMA
+ */
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DMA_LPC32XX
+#endif
+
/*
* I2C
*/
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_LPC32XX
+#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
/*
* U-Boot General Configurations
*/
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
#define CONFIG_QSPI_QUAD_SUPPORT
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x010000 : QSPI.SPL (64KiB)
--- /dev/null
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_SYNOLOGY_DS414_H
+#define _CONFIG_SYNOLOGY_DS414_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define CONFIG_PHY_ADDR { 0x1, 0x0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* USB/EHCI/XHCI configuration */
+
+#define CONFIG_DM_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* FIXME: broken XHCI support
+ * Below defines should enable support for the two rear USB3 ports. Sadly, this
+ * does not work because:
+ * - xhci-pci seems to not support DM_USB, so with that enabled it is not
+ * found.
+ * - USB init fails, controller does not respond in time */
+#if 0
+#undef CONFIG_DM_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_PCI
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if !defined(CONFIG_USB_XHCI)
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_SYS_MVFS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+
+/* DS414 bus width is 32bits */
+#define CONFIG_DDR_32BIT
+
+/* Use random ethernet address if not configured */
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
+/* Default Environment */
+#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+#define CONFIG_LOADADDR 0x80000
+#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
+#define CONFIG_PREBOOT "usb start; sf probe"
+
+#endif /* _CONFIG_SYNOLOGY_DS414_H */
#define CONFIG_IDENT_STRING " iocon 0.06"
#include "amcc-common.h"
+/* Reclaim some space. */
+#undef CONFIG_SYS_LONGHELP
+
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#ifndef _MALTA_CONFIG_H
#define _MALTA_CONFIG_H
-#include <asm/addrspace.h>
-#include <asm/malta.h>
-
/*
* System configuration
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (115200 * 16)
-#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
-#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM1 0xb80003f8
+#define CONFIG_SYS_NS16550_COM2 0xbb0003f8
#define CONFIG_CONS_INDEX 1
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
+#define CONFIG_SYS_FLASH_BASE 0xbe000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
+#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MX6_COMMON_H
#else
#error "status LED not defined for this machine."
#endif
-#define RED_LED_DEV 0
+#define RED_LED_DEV 0
#define STATUS_LED_BIT RED_LED_GPIO
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
/* USB */
-#define CONFIG_USB_MUSB_UDC 1
+#define CONFIG_USB_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_TWL4030_USB 1
#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_CMD_ONENAND /* ONENAND support */
#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
- (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
-#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-/*#undef CONFIG_ENV_IS_NOWHERE*/
-
#ifndef CONFIG_SPL_BUILD
-#include <config_distro_defaults.h>
-
/* Environment */
#define ENV_DEVICE_SETTINGS \
"stdin=serial\0" \
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
+#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
/* OneNAND boot config */
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
/* The following #defines are needed to get flash environment right */
+/* ROM version */
+/* #define CONFIG_SYS_TEXT_BASE 0xbfc00000 */
+/* SDRAM version */
+#define CONFIG_SYS_TEXT_BASE 0x83800000
+
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
*/
#define CONFIG_PARTITION_UUIDS
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_CMD_PART
-/*
- * Filesystems
- */
-
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-
/*
* SPL
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x82000000\0" \
+ "loadaddr=0x82000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "fdtaddr=0x88000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80000000\0" \
+ "bootm_size=0x10000000\0" \
"boot_mmc_dev=0\0" \
"kernel_mmc_part=3\0" \
"recovery_mmc_part=4\0" \
+ "fdtfile=omap3-sniper.dtb\0" \
+ "bootfile=/boot/extlinux/extlinux.conf\0" \
"bootargs=console=ttyO2 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
/*
- * ATAGs / Device Tree
+ * ATAGs
*/
-#define CONFIG_OF_LIBFDT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
*/
#define CONFIG_SYS_LOAD_ADDR 0x82000000
-#define CONFIG_BOOTDELAY 1
#define CONFIG_ANDROID_BOOT_IMAGE
*/
#include <config_defaults.h>
+#include <config_distro_defaults.h>
#endif
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_DM_SEQ_ALIAS 1
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_STM32F4
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_STM32F4DISCOVERY
#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
- defined CONFIG_I2C4_ENABLE
+ defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_SYS_I2C_SPEED 400000
if (i) \
sprintf(ethname, "eth%daddr", i); \
else \
- sprintf(ethname, "ethaddr"); \
+ strcpy(ethname, "ethaddr"); \
printf("Setting %s from EEPROM with %s\n", ethname, buf);\
setenv(ethname, buf); \
} \
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_COMMON_H_
--- /dev/null
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#ifndef __THUNDERX_88XX_H__
+#define __THUNDERX_88XX_H__
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_THUNDERX
+
+#define CONFIG_SYS_64BIT
+
+#define CONFIG_SYS_NO_FLASH
+
+
+#define CONFIG_IDENT_STRING \
+ " for Cavium Thunder CN88XX ARM v8 Multi-Core"
+#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
+
+#define MEM_BASE 0x00500000
+
+#define CONFIG_COREID_MASK 0xffffff
+
+#define CONFIG_SYS_FULL_VA
+
+#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
+
+#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \
+ PTL2_MEMTYPE(MT_NORMAL) | \
+ PTL2_BLOCK_NON_SHARE}, \
+ {0x800000000000UL, 0x40000000000UL, \
+ PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \
+ PTL2_BLOCK_NON_SHARE}, \
+ {0x840000000000UL, 0x40000000000UL, \
+ PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \
+ PTL2_BLOCK_NON_SHARE}, \
+ }
+
+#define CONFIG_SYS_MEM_MAP_SIZE 3
+
+#define CONFIG_SYS_VA_BITS 48
+#define CONFIG_SYS_PTL2_BITS 42
+#define CONFIG_SYS_BLOCK_SHIFT 29
+#define CONFIG_SYS_PTL1_ENTRIES 64
+#define CONFIG_SYS_PTL2_ENTRIES 8192
+
+#define CONFIG_SYS_PGTABLE_SIZE \
+ ((CONFIG_SYS_PTL1_ENTRIES + \
+ CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8)
+#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32)
+#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16)
+#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16)
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE 0x00500000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+
+#define CONFIG_SYS_MEMTEST_START MEM_BASE
+#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* PL011 Serial Configuration */
+
+#define CONFIG_PL01X_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_CONS_INDEX 1
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE (0x801000000000)
+#define GICR_BASE (0x801000002000)
+#define CONFIG_SYS_SERIAL0 0x87e024000000
+#define CONFIG_SYS_SERIAL1 0x87e025000000
+
+#define CONFIG_BAUDRATE 115200
+
+/* Command line configuration */
+#define CONFIG_MENU
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Initial environment variables */
+#define UBOOT_IMG_HEAD_SIZE 0x40
+/* C80000 - 0x40 */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr=08007ffc0\0" \
+ "fdt_addr=0x94C00000\0" \
+ "fdt_high=0x9fffffff\0"
+
+#define CONFIG_BOOTARGS \
+ "console=ttyAMA0,115200n8 " \
+ "earlycon=pl011,0x87e024000000 " \
+ "debug maxcpus=48 rootwait rw "\
+ "root=/dev/sda2 coherent_pool=16M"
+#define CONFIG_BOOTDELAY 5
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+#define CONFIG_NO_RELOCATION 1
+#define CONFIG_LIB_RAND
+#define PLL_REF_CLK 50000000 /* 50 MHz */
+#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
+
+#endif /* __THUNDERX_88XX_H__ */
#endif
#include <config_distro_defaults.h>
+#define CONFIG_CMD_EXT4_WRITE
#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SYS_NAND_BASE 0x30000000
#endif
/*
* Environment setup
*/
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance"; "\
+ "setenv bootpart " #instance":2 ; "\
+ "run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(LEGACY_MMC, legacy_mmc, 1) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadbootenv; then " \
- "run importbootenv; " \
- "fi;" \
- "if test -n ${uenvcmd}; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcboot; " \
- "fi; " \
- "if run loaduimage; then " \
- "run uimageboot;" \
- "fi; " \
- "fi"
+ BOOTENV
/*
* Defines for SPL
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"ramdisk_addr_r=0x84a00000\0" \
"ramdisk_size=0x00600000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
- "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
+ "norboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
+ "setexpr kernel_addr $nor_base + $kernel_addr &&" \
"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
"setexpr fdt_addr $nor_base + $fdt_addr &&" \
"bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
- "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
+ "nandboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
+ "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
- "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
+ "tftpboot=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
+ "tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
"nand write $loadaddr 0x00010000 0x000f0000\0" \
LINUXBOOT_ENV_SETTINGS
+#define CONFIG_SYS_BOOTMAPSZ 0x20000000
+
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
+#define CONFIG_SYS_TEXT_BASE 0x87000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
#define CONFIG_HOSTNAME x86
#define CONFIG_BOOTFILE "bzImage"
#define CONFIG_LOADADDR 0x1000000
+#define CONFIG_RAMDISK_ADDR 0x4000000
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"othbootargs=acpi=off\0" \
- "ramdiskaddr=0x2000000\0" \
+ "ramdiskaddr=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
#define CONFIG_RAMBOOTCOMMAND \
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DDR_SPD_H_
*/
fdt_addr_t dev_get_addr(struct udevice *dev);
+/**
+ * dev_get_addr_index() - Get the indexed reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
+
/**
* device_has_children() - check if a device has any children
*
--- /dev/null
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LPC32XX_HSUART_PLAT_H
+#define _LPC32XX_HSUART_PLAT_H
+
+/**
+ * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ *
+ * @base: Base register address
+ */
+struct lpc32xx_hsuart_platdata {
+ unsigned long base;
+};
+
+#endif
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __DS4510_H_
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
+ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_COUNT,
};
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _FS_H
#define _FS_H
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef FSL_DDR_MAIN_H
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef DDR2_DIMM_PARAMS_H
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef FSL_DDR_MEMCTL_H
int hash_block(const char *algo_name, const void *data, unsigned int len,
uint8_t *output, int *output_size);
-/**
- * hash_show() - Print out a hash algorithm and value
- *
- * You will get a message like this (without a newline at the end):
- *
- * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257"
- *
- * @algo: Algorithm used for hash
- * @addr: Address of data that was hashed
- * @len: Length of data that was hashed
- * @output: Hash value to display
- */
-void hash_show(struct hash_algo *algo, ulong addr, ulong len,
- uint8_t *output);
-
#endif /* !USE_HOSTCC */
/**
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
-#define LBAF "%llx"
-#define LBAFU "%llu"
+#define LBAFlength "ll"
#else
typedef ulong lbaint_t;
-#define LBAF "%lx"
-#define LBAFU "%lu"
+#define LBAFlength "l"
#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
/*
* Function Prototypes
*/
void ide_init(void);
-ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer);
-ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt,
+typedef struct block_dev_desc block_dev_desc_t;
+ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer);
+ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer);
#ifdef CONFIG_IDE_PREINIT
/*
* Generic binary BCH encoding/decoding library
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 51
- * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: GPL-2.0
*
* Copyright © 2011 Parrot S.A.
*
* information is used to identify BIOS boot disk. The code in setup.S
* is very sensitive to the size of these structures.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2.0 as published by
- * the Free Software Foundation
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _LINUX_EDD_H
#define _LINUX_EDD_H
/*
* Copyright (c) 1999-2002 Vojtech Pavlik
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _LINUX_INPUT_H
--- /dev/null
+/*
+ * ARM Power State and Coordination Interface (PSCI) header
+ *
+ * This header holds common PSCI defines and macros shared
+ * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space.
+ *
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Anup Patel <anup.patel@linaro.org>
+ */
+
+#ifndef _UAPI_LINUX_PSCI_H
+#define _UAPI_LINUX_PSCI_H
+
+/*
+ * PSCI v0.1 interface
+ *
+ * The PSCI v0.1 function numbers are implementation defined.
+ *
+ * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
+ * INVALID_PARAMS, and DENIED defined below are applicable
+ * to PSCI v0.1.
+ */
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
+#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff
+#define PSCI_0_2_POWER_STATE_ID_SHIFT 0
+#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16
+#define PSCI_0_2_POWER_STATE_TYPE_MASK \
+ (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
+#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24
+#define PSCI_0_2_POWER_STATE_AFFL_MASK \
+ (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
+
+/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
+#define PSCI_0_2_AFFINITY_LEVEL_ON 0
+#define PSCI_0_2_AFFINITY_LEVEL_OFF 1
+#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2
+
+/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
+#define PSCI_0_2_TOS_UP_MIGRATE 0
+#define PSCI_0_2_TOS_UP_NO_MIGRATE 1
+#define PSCI_0_2_TOS_MP 2
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+
+#endif /* _UAPI_LINUX_PSCI_H */
u8 part_attr;
u8 wr_rel_set;
char part_config;
- char part_num;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
*/
#define SDRAM_INTERVAL_REFINT 0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT 16
-#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
/*
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _NAND_H_
extern struct eth_device *eth_current;
-static inline __attribute__((always_inline))
-struct eth_device *eth_get_dev(void)
+static __always_inline struct eth_device *eth_get_dev(void)
{
return eth_current;
}
/* Used only when NetConsole is enabled */
int eth_is_active(struct eth_device *dev); /* Test device for active state */
/* Set active state */
-static inline __attribute__((always_inline)) int eth_init_state_only(void)
+static __always_inline int eth_init_state_only(void)
{
eth_get_dev()->state = ETH_STATE_ACTIVE;
return 0;
}
/* Set passive state */
-static inline __attribute__((always_inline)) void eth_halt_state_only(void)
+static __always_inline void eth_halt_state_only(void)
{
eth_get_dev()->state = ETH_STATE_PASSIVE;
}
unsigned src_port, unsigned len);
#endif
-static inline __attribute__((always_inline)) int eth_is_on_demand_init(void)
+static __always_inline int eth_is_on_demand_init(void)
{
#ifdef CONFIG_NETCONSOLE
extern enum proto_t net_loop_last_protocol;
#include <ide.h>
#include <common.h>
-typedef struct block_dev_desc {
+typedef struct block_dev_desc block_dev_desc_t;
+
+struct block_dev_desc {
int if_type; /* type of the interface */
int dev; /* device number */
unsigned char part_type; /* partition type */
unsigned char target; /* target SCSI ID */
unsigned char lun; /* target LUN */
+ unsigned char hwpart; /* HW partition, e.g. for eMMC */
unsigned char type; /* device type */
unsigned char removable; /* removable device */
#ifdef CONFIG_LBA48
char vendor [40+1]; /* IDE model, SCSI Vendor */
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
- unsigned long (*block_read)(int dev,
+ unsigned long (*block_read)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt,
void *buffer);
- unsigned long (*block_write)(int dev,
+ unsigned long (*block_write)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt,
const void *buffer);
- unsigned long (*block_erase)(int dev,
+ unsigned long (*block_erase)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt);
void *priv; /* driver private struct pointer */
-}block_dev_desc_t;
+};
#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __PCA953X_H_
#define __CORE_PMIC_H_
#include <i2c.h>
-#include <spi.h>
#include <linux/list.h>
#include <power/power_chrg.h>
#define _SPI_H_
/* SPI mode flags */
-#define SPI_CPHA 0x01 /* clock phase */
-#define SPI_CPOL 0x02 /* clock polarity */
-#define SPI_MODE_0 (0|0) /* (original MicroWire) */
-#define SPI_MODE_1 (0|SPI_CPHA)
-#define SPI_MODE_2 (SPI_CPOL|0)
-#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
-#define SPI_CS_HIGH 0x04 /* CS active high */
-#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
-#define SPI_3WIRE 0x10 /* SI/SO signals shared */
-#define SPI_LOOP 0x20 /* loopback mode */
-#define SPI_SLAVE 0x40 /* slave mode */
-#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
-
-/* SPI transfer flags */
-#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
-#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
-#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
-#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
-#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE (1 << 5)
-
-/* SPI TX operation modes */
-#define SPI_OPM_TX_QPP (1 << 0)
-#define SPI_OPM_TX_BP (1 << 1)
-
-/* SPI RX operation modes */
-#define SPI_OPM_RX_AS (1 << 0)
-#define SPI_OPM_RX_AF (1 << 1)
-#define SPI_OPM_RX_DOUT (1 << 2)
-#define SPI_OPM_RX_DIO (1 << 3)
-#define SPI_OPM_RX_QOF (1 << 4)
-#define SPI_OPM_RX_QIOF (1 << 5)
-#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
- SPI_OPM_RX_QIOF)
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_MODE_0 (0|0) /* (original MicroWire) */
+#define SPI_MODE_1 (0|SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL|0)
+#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
+#define SPI_CS_HIGH BIT(2) /* CS active high */
+#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
+#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
+#define SPI_LOOP BIT(5) /* loopback mode */
+#define SPI_SLAVE BIT(6) /* slave mode */
+#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */
+#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
+#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
+#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
+
+/* SPI mode_rx flags */
+#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */
+#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
+#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
/* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 << 0)
* @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
*/
struct dm_spi_slave_platdata {
unsigned int cs;
uint max_hz;
uint mode;
+ u8 mode_rx;
};
#endif /* CONFIG_DM_SPI */
*
* @dev: SPI slave device
* @max_hz: Maximum speed for this slave
- * @mode: SPI mode to use for this slave (see SPI mode flags)
* @speed: Current bus speed. This is 0 until the bus is first
* claimed.
* @bus: ID of the bus that the slave is attached to. For
* driver model this is the sequence number of the SPI
* bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave.
- * @op_mode_rx: SPI RX operation mode.
- * @op_mode_tx: SPI TX operation mode.
+ * @mode: SPI mode to use for this slave (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
struct udevice *dev; /* struct spi_slave is dev->parentdata */
uint max_hz;
uint speed;
- uint mode;
#else
unsigned int bus;
unsigned int cs;
#endif
- u8 op_mode_rx;
- u8 op_mode_tx;
+ uint mode;
+ u8 mode_rx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
u8 option;
+
u8 flags;
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */
+#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */
+#define SPI_XFER_U_PAGE BIT(4)
};
/**
* Copyright (C) 2008 Atmel Corporation
* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _SPI_FLASH_H_
/* Compatibility function - this is the old U-Boot API */
void spi_flash_free(struct spi_flash *flash);
-int spi_flash_remove(struct udevice *flash);
-
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{
*
* Copyright (C) 2003-2006 Christophe Devine
*
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License, version 2.1 as published by the Free Software Foundation.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier: LGPL-2.1
*/
/*
* The SHA-1 standard was published by NIST in 1993.
* Original Copyrights follow:
* Copyright (C) 2010 Nokia Corporation
*
- * This software is distributed under the terms of the GNU General
- * Public License ("GPL") as published by the Free Software Foundation,
- * version 2 of that License.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __USB_ULPI_H__
unsigned int start_sector;
unsigned int num_sectors;
const char *name;
- block_dev_desc_t *block_dev;
+ block_dev_desc_t block_dev;
};
-extern struct ums *ums;
-
-int fsg_init(struct ums *);
+int fsg_init(struct ums *ums_devs, int count);
void fsg_cleanup(void);
int fsg_main_thread(void *);
int fsg_add(struct usb_configuration *c);
int vsprintf(char *buf, const char *fmt, va_list args);
char *simple_itoa(ulong i);
-#ifdef CONFIG_SYS_VSNPRINTF
/**
* Format a string and place it in a buffer
*
* See the vsprintf() documentation for format string extensions over C99.
*/
int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
-#else
-/*
- * Use macros to silently drop the size parameter. Note that the 'cn'
- * versions are the same as the 'n' versions since the functions assume
- * there is always enough buffer space when !CONFIG_SYS_VSNPRINTF
- */
-#define snprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args)
-#define scnprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args)
-#define vsnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args)
-#define vscnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args)
-#endif /* CONFIG_SYS_VSNPRINTF */
/**
* print_grouped_ull() - print a value with digits grouped by ','
get_timer() must operate in milliseconds and this option must be
set to 1000.
-config SYS_VSNPRINTF
- bool "Enable safe version of sprintf()"
- help
- Since sprintf() can overflow its buffer, it is common to use
- snprintf() instead, which knows the buffer size and can avoid
- overflow. However, this does increase code size slightly (for
- Thumb-2, about 420 bytes). Enable this option for safety when
- using sprintf() with data you do not control.
-
config USE_TINY_PRINTF
bool "Enable tiny printf() version"
help
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/*
* Generic binary BCH encoding/decoding library
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 51
- * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: GPL-2.0
*
* Copyright © 2011 Parrot S.A.
*
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+ COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
return zunzip(dst, dstlen, src, lenp, 1, i);
}
+#ifdef CONFIG_CMD_UNZIP
__weak
void gzwrite_progress_init(u64 expectedsize)
{
gzwrite_progress(iteration++,
totalfilled,
szexpected);
- blocks_written = dev->block_write(dev->dev,
- outblock,
+ blocks_written = dev->block_write(dev, outblock,
writeblocks,
writebuf);
outblock += blocks_written;
return r;
}
+#endif
/*
* Uncompress blocks compressed with zlib without headers
*
* Copyright (C) 2003-2006 Christophe Devine
*
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License, version 2.1 as published by the Free Software Foundation.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier: LGPL-2.1
*/
/*
* The SHA-1 standard was published by NIST in 1993.
#define SMALL 32 /* Must be 32 == 0x20 */
#define SPECIAL 64 /* 0x */
-#ifdef CONFIG_SYS_VSNPRINTF
/*
* Macro to add a new character to our output string, but only if it will
* fit. The macro moves to the next character position in the output string.
*(str) = (ch); \
++str; \
} while (0)
-#else
-#define ADDCH(str, ch) (*(str)++ = (ch))
-#endif
static char *number(char *buf, char *end, u64 num,
int base, int size, int precision, int type)
/* 't' added for ptrdiff_t */
char *end = buf + size;
-#ifdef CONFIG_SYS_VSNPRINTF
/* Make sure end is always >= buf - do we want this in U-Boot? */
if (end < buf) {
end = ((void *)-1);
size = end - buf;
}
-#endif
str = buf;
for (; *fmt ; ++fmt) {
flags);
}
-#ifdef CONFIG_SYS_VSNPRINTF
if (size > 0) {
ADDCH(str, '\0');
if (str > end)
end[-1] = '\0';
--str;
}
-#else
- *str = '\0';
-#endif
/* the trailing null byte doesn't count towards the total */
return str - buf;
}
-#ifdef CONFIG_SYS_VSNPRINTF
int vsnprintf(char *buf, size_t size, const char *fmt,
va_list args)
{
return i;
}
-#endif /* CONFIG_SYS_VSNPRINT */
/**
* Format a string and place it in a buffer (va_list version)
# When our migration to Kconfig is done
# (= When we move all CONFIGs from header files to Kconfig)
# this makefile can be deleted.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
__all: include/autoconf.mk include/autoconf.mk.dep
# ==========================================================================
# Building
# ==========================================================================
+#
+# SPDX-License-Identifier: GPL-2.0
+#
# Modified for U-Boot
prefix := tpl
# ==========================================================================
# Cleaning up
# ==========================================================================
+#
+# SPDX-License-Identifier: GPL-2.0
+#
src := $(obj)
# $(call cc-option, -W...) handles gcc -W.. options which
# are not supported by all versions of the compiler
# ==========================================================================
+#
+# SPDX-License-Identifier: GPL-2.0
+#
ifeq ("$(origin W)", "command line")
export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
# qconf-objs := menu.o
# Will compile qconf as a C++ program, and menu as a C program.
# They are linked as C++ code to the executable qconf
+#
+# SPDX-License-Identifier: GPL-2.0
+#
__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
+#
+# SPDX-License-Identifier: GPL-2.0
+#
# Backward compatibility
asflags-y += $(EXTRA_AFLAGS)
ccflags-y += $(EXTRA_CFLAGS)
# Makefile version of include/config_uncmd_spl.h
#
+# SPDX-License-Identifier: GPL-2.0+
+#
# TODO: Invent a better way
ifdef CONFIG_SPL_BUILD
* Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
*
* AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <sys/types.h>
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <stdarg.h>
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
data->targets[k] = pos->target;
k++;
} else {
- sprintf(header, " ");
+ strcpy(header, " ");
}
memcpy(buf + pos->offset, header, sizeof(header) - 1);
/* Read a few blocks and look for the string we expect */
ut_asserteq(512, dev_desc->blksz);
memset(cmp, '\0', sizeof(cmp));
- ut_asserteq(2, dev_desc->block_read(dev_desc->dev, 0, 2, cmp));
+ ut_asserteq(2, dev_desc->block_read(dev_desc, 0, 2, cmp));
ut_assertok(strcmp(cmp, "this is a test"));
return 0;
# We save time by not deleting and recreating the file system images
function prepare_env() {
rm -f ${MD5_FILE}.* ${OUT}.*
- mkdir ${OUT_DIR}
+ mkdir -p ${OUT_DIR}
}
# 1st parameter is the name of the image file to be created
fi
if [ ! -f "$1" ]; then
fallocate -l 3G "$1" &> /dev/null
+ if [ $? -ne 0 ]; then
+ echo fallocate failed - using dd instead
+ dd if=/dev/zero of=$1 bs=1024 count=$((3 * 1024 * 1024))
+ if [ $? -ne 0 ]; then
+ echo Could not create empty disk image
+ exit $?
+ fi
+ fi
mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null
if [ $? -ne 0 -a "$2" = "fat" ]; then
# If we fail and we did fat, try vfat.
mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null
fi
+ if [ $? -ne 0 ]; then
+ echo Could not create filesystem
+ exit $?
+ fi
fi
}
HOSTCFLAGS_ubsha1.o := -pedantic
hostprogs-$(CONFIG_KIRKWOOD) += kwboot
-hostprogs-$(CONFIG_ARMADA_XP) += kwboot
+hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot
hostprogs-y += proftool
hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
* 2008. Chapter 24.2 "BootROM Firmware".
*/
+#include "kwbimage.h"
+#include "mkimage.h"
+
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
+#include <image.h>
#include <libgen.h>
#include <fcntl.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/stat.h>
-#include "kwbimage.h"
-
#ifdef __GNUC__
#define PACKED __attribute((packed))
#else
hdr->blockid = IBR_HDR_UART_ID;
+ /*
+ * Subtract mkimage header size from destination address
+ * as this header is not expected by the Marvell BootROM.
+ * This way, the execution address is identical to the
+ * one the image is compiled for (TEXT_BASE).
+ */
+ hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
+
if (image_ver == 0) {
struct main_hdr_v0 *hdr_v0 = img;
name = os.path.splitext(name)[0]
data = []
with open(fname) as fd:
+ license_start = False
+ license_end = False
for line in fd:
line = line.rstrip()
+ if len(line) >= 2:
+ if line[0] == '/' and line[1] == '*':
+ license_start = True
+ continue
+ if line[0] == '*' and line[1] == '/':
+ license_end = True
+ continue
+ if license_start and not license_end:
+ # Ignore blank line
+ if len(line) > 0:
+ license_text.append(line)
+ continue
# Omit anything after the last comma
words = line.split(',')[:-1]
data += [word + ',' for word in words]
projects / karo-tx-uboot.git / commitdiff